1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek UART APDMA driver.
5 * Copyright (c) 2019 MediaTek Inc.
6 * Author: Long Cheng <long.cheng@mediatek.com>
10 #include <linux/dmaengine.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/err.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/iopoll.h>
16 #include <linux/kernel.h>
17 #include <linux/list.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/of_dma.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
26 #include "../virt-dma.h"
28 /* The default number of virtual channel */
29 #define MTK_UART_APDMA_NR_VCHANS 8
31 #define VFF_EN_B BIT(0)
32 #define VFF_STOP_B BIT(0)
33 #define VFF_FLUSH_B BIT(0)
34 #define VFF_4G_EN_B BIT(0)
35 /* rx valid size >= vff thre */
36 #define VFF_RX_INT_EN_B (BIT(0) | BIT(1))
37 /* tx left size >= vff thre */
38 #define VFF_TX_INT_EN_B BIT(0)
39 #define VFF_WARM_RST_B BIT(0)
40 #define VFF_RX_INT_CLR_B (BIT(0) | BIT(1))
41 #define VFF_TX_INT_CLR_B 0
42 #define VFF_STOP_CLR_B 0
43 #define VFF_EN_CLR_B 0
44 #define VFF_INT_EN_CLR_B 0
45 #define VFF_4G_SUPPORT_CLR_B 0
48 * interrupt trigger level for tx
49 * if threshold is n, no polling is required to start tx.
50 * otherwise need polling VFF_FLUSH.
52 #define VFF_TX_THRE(n) (n)
53 /* interrupt trigger level for rx */
54 #define VFF_RX_THRE(n) ((n) * 3 / 4)
56 #define VFF_RING_SIZE 0xffff
57 /* invert this bit when wrap ring head again */
58 #define VFF_RING_WRAP 0x10000
60 #define VFF_INT_FLAG 0x00
61 #define VFF_INT_EN 0x04
65 #define VFF_FLUSH 0x14
71 /* TX: the buffer size HW can read. RX: the buffer size SW can read. */
72 #define VFF_VALID_SIZE 0x3c
73 /* TX: the buffer size SW can write. RX: the buffer size HW can write. */
74 #define VFF_LEFT_SIZE 0x40
75 #define VFF_DEBUG_STATUS 0x50
76 #define VFF_4G_SUPPORT 0x54
78 struct mtk_uart_apdmadev {
79 struct dma_device ddev;
82 unsigned int dma_requests;
85 struct mtk_uart_apdma_desc {
86 struct virt_dma_desc vd;
89 unsigned int avail_len;
93 struct virt_dma_chan vc;
94 struct dma_slave_config cfg;
95 struct mtk_uart_apdma_desc *desc;
96 enum dma_transfer_direction dir;
101 unsigned int rx_status;
104 static inline struct mtk_uart_apdmadev *
105 to_mtk_uart_apdma_dev(struct dma_device *d)
107 return container_of(d, struct mtk_uart_apdmadev, ddev);
110 static inline struct mtk_chan *to_mtk_uart_apdma_chan(struct dma_chan *c)
112 return container_of(c, struct mtk_chan, vc.chan);
115 static inline struct mtk_uart_apdma_desc *to_mtk_uart_apdma_desc
116 (struct dma_async_tx_descriptor *t)
118 return container_of(t, struct mtk_uart_apdma_desc, vd.tx);
121 static void mtk_uart_apdma_write(struct mtk_chan *c,
122 unsigned int reg, unsigned int val)
124 writel(val, c->base + reg);
127 static unsigned int mtk_uart_apdma_read(struct mtk_chan *c, unsigned int reg)
129 return readl(c->base + reg);
132 static void mtk_uart_apdma_desc_free(struct virt_dma_desc *vd)
134 kfree(container_of(vd, struct mtk_uart_apdma_desc, vd));
137 static void mtk_uart_apdma_start_tx(struct mtk_chan *c)
139 struct mtk_uart_apdmadev *mtkd =
140 to_mtk_uart_apdma_dev(c->vc.chan.device);
141 struct mtk_uart_apdma_desc *d = c->desc;
142 unsigned int wpt, vff_sz;
144 vff_sz = c->cfg.dst_port_window_size;
145 if (!mtk_uart_apdma_read(c, VFF_LEN)) {
146 mtk_uart_apdma_write(c, VFF_ADDR, d->addr);
147 mtk_uart_apdma_write(c, VFF_LEN, vff_sz);
148 mtk_uart_apdma_write(c, VFF_THRE, VFF_TX_THRE(vff_sz));
149 mtk_uart_apdma_write(c, VFF_WPT, 0);
150 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B);
152 if (mtkd->support_33bits)
153 mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_EN_B);
156 mtk_uart_apdma_write(c, VFF_EN, VFF_EN_B);
157 if (mtk_uart_apdma_read(c, VFF_EN) != VFF_EN_B)
158 dev_err(c->vc.chan.device->dev, "Enable TX fail\n");
160 if (!mtk_uart_apdma_read(c, VFF_LEFT_SIZE)) {
161 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_TX_INT_EN_B);
165 wpt = mtk_uart_apdma_read(c, VFF_WPT);
167 wpt += c->desc->avail_len;
168 if ((wpt & VFF_RING_SIZE) == vff_sz)
169 wpt = (wpt & VFF_RING_WRAP) ^ VFF_RING_WRAP;
171 /* Let DMA start moving data */
172 mtk_uart_apdma_write(c, VFF_WPT, wpt);
174 /* HW auto set to 0 when left size >= threshold */
175 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_TX_INT_EN_B);
176 if (!mtk_uart_apdma_read(c, VFF_FLUSH))
177 mtk_uart_apdma_write(c, VFF_FLUSH, VFF_FLUSH_B);
180 static void mtk_uart_apdma_start_rx(struct mtk_chan *c)
182 struct mtk_uart_apdmadev *mtkd =
183 to_mtk_uart_apdma_dev(c->vc.chan.device);
184 struct mtk_uart_apdma_desc *d = c->desc;
187 vff_sz = c->cfg.src_port_window_size;
188 if (!mtk_uart_apdma_read(c, VFF_LEN)) {
189 mtk_uart_apdma_write(c, VFF_ADDR, d->addr);
190 mtk_uart_apdma_write(c, VFF_LEN, vff_sz);
191 mtk_uart_apdma_write(c, VFF_THRE, VFF_RX_THRE(vff_sz));
192 mtk_uart_apdma_write(c, VFF_RPT, 0);
193 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B);
195 if (mtkd->support_33bits)
196 mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_EN_B);
199 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_RX_INT_EN_B);
200 mtk_uart_apdma_write(c, VFF_EN, VFF_EN_B);
201 if (mtk_uart_apdma_read(c, VFF_EN) != VFF_EN_B)
202 dev_err(c->vc.chan.device->dev, "Enable RX fail\n");
205 static void mtk_uart_apdma_tx_handler(struct mtk_chan *c)
207 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B);
208 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B);
209 mtk_uart_apdma_write(c, VFF_EN, VFF_EN_CLR_B);
212 static void mtk_uart_apdma_rx_handler(struct mtk_chan *c)
214 struct mtk_uart_apdma_desc *d = c->desc;
215 unsigned int len, wg, rg;
218 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B);
220 if (!mtk_uart_apdma_read(c, VFF_VALID_SIZE))
223 mtk_uart_apdma_write(c, VFF_EN, VFF_EN_CLR_B);
224 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B);
226 len = c->cfg.src_port_window_size;
227 rg = mtk_uart_apdma_read(c, VFF_RPT);
228 wg = mtk_uart_apdma_read(c, VFF_WPT);
229 cnt = (wg & VFF_RING_SIZE) - (rg & VFF_RING_SIZE);
232 * The buffer is ring buffer. If wrap bit different,
233 * represents the start of the next cycle for WPT
235 if ((rg ^ wg) & VFF_RING_WRAP)
238 c->rx_status = d->avail_len - cnt;
239 mtk_uart_apdma_write(c, VFF_RPT, wg);
242 static void mtk_uart_apdma_chan_complete_handler(struct mtk_chan *c)
244 struct mtk_uart_apdma_desc *d = c->desc;
247 list_del(&d->vd.node);
248 vchan_cookie_complete(&d->vd);
253 static irqreturn_t mtk_uart_apdma_irq_handler(int irq, void *dev_id)
255 struct dma_chan *chan = (struct dma_chan *)dev_id;
256 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
259 spin_lock_irqsave(&c->vc.lock, flags);
260 if (c->dir == DMA_DEV_TO_MEM)
261 mtk_uart_apdma_rx_handler(c);
262 else if (c->dir == DMA_MEM_TO_DEV)
263 mtk_uart_apdma_tx_handler(c);
264 mtk_uart_apdma_chan_complete_handler(c);
265 spin_unlock_irqrestore(&c->vc.lock, flags);
270 static int mtk_uart_apdma_alloc_chan_resources(struct dma_chan *chan)
272 struct mtk_uart_apdmadev *mtkd = to_mtk_uart_apdma_dev(chan->device);
273 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
277 ret = pm_runtime_resume_and_get(mtkd->ddev.dev);
279 pm_runtime_put_noidle(chan->device->dev);
283 mtk_uart_apdma_write(c, VFF_ADDR, 0);
284 mtk_uart_apdma_write(c, VFF_THRE, 0);
285 mtk_uart_apdma_write(c, VFF_LEN, 0);
286 mtk_uart_apdma_write(c, VFF_RST, VFF_WARM_RST_B);
288 ret = readx_poll_timeout(readl, c->base + VFF_EN,
289 status, !status, 10, 100);
293 ret = request_irq(c->irq, mtk_uart_apdma_irq_handler,
294 IRQF_TRIGGER_NONE, KBUILD_MODNAME, chan);
296 dev_err(chan->device->dev, "Can't request dma IRQ\n");
301 if (mtkd->support_33bits)
302 mtk_uart_apdma_write(c, VFF_4G_SUPPORT, VFF_4G_SUPPORT_CLR_B);
305 pm_runtime_put_noidle(mtkd->ddev.dev);
309 static void mtk_uart_apdma_free_chan_resources(struct dma_chan *chan)
311 struct mtk_uart_apdmadev *mtkd = to_mtk_uart_apdma_dev(chan->device);
312 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
314 free_irq(c->irq, chan);
316 tasklet_kill(&c->vc.task);
318 vchan_free_chan_resources(&c->vc);
320 pm_runtime_put_sync(mtkd->ddev.dev);
323 static enum dma_status mtk_uart_apdma_tx_status(struct dma_chan *chan,
325 struct dma_tx_state *txstate)
327 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
330 ret = dma_cookie_status(chan, cookie, txstate);
334 dma_set_residue(txstate, c->rx_status);
340 * dmaengine_prep_slave_single will call the function. and sglen is 1.
341 * 8250 uart using one ring buffer, and deal with one sg.
343 static struct dma_async_tx_descriptor *mtk_uart_apdma_prep_slave_sg
344 (struct dma_chan *chan, struct scatterlist *sgl,
345 unsigned int sglen, enum dma_transfer_direction dir,
346 unsigned long tx_flags, void *context)
348 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
349 struct mtk_uart_apdma_desc *d;
351 if (!is_slave_direction(dir) || sglen != 1)
354 /* Now allocate and setup the descriptor */
355 d = kzalloc(sizeof(*d), GFP_NOWAIT);
359 d->avail_len = sg_dma_len(sgl);
360 d->addr = sg_dma_address(sgl);
363 return vchan_tx_prep(&c->vc, &d->vd, tx_flags);
366 static void mtk_uart_apdma_issue_pending(struct dma_chan *chan)
368 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
369 struct virt_dma_desc *vd;
372 spin_lock_irqsave(&c->vc.lock, flags);
373 if (vchan_issue_pending(&c->vc) && !c->desc) {
374 vd = vchan_next_desc(&c->vc);
375 c->desc = to_mtk_uart_apdma_desc(&vd->tx);
377 if (c->dir == DMA_DEV_TO_MEM)
378 mtk_uart_apdma_start_rx(c);
379 else if (c->dir == DMA_MEM_TO_DEV)
380 mtk_uart_apdma_start_tx(c);
383 spin_unlock_irqrestore(&c->vc.lock, flags);
386 static int mtk_uart_apdma_slave_config(struct dma_chan *chan,
387 struct dma_slave_config *config)
389 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
391 memcpy(&c->cfg, config, sizeof(*config));
396 static int mtk_uart_apdma_terminate_all(struct dma_chan *chan)
398 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
404 mtk_uart_apdma_write(c, VFF_FLUSH, VFF_FLUSH_B);
406 ret = readx_poll_timeout(readl, c->base + VFF_FLUSH,
407 status, status != VFF_FLUSH_B, 10, 100);
409 dev_err(c->vc.chan.device->dev, "flush: fail, status=0x%x\n",
410 mtk_uart_apdma_read(c, VFF_DEBUG_STATUS));
418 mtk_uart_apdma_write(c, VFF_STOP, VFF_STOP_B);
419 ret = readx_poll_timeout(readl, c->base + VFF_EN,
420 status, !status, 10, 100);
422 dev_err(c->vc.chan.device->dev, "stop: fail, status=0x%x\n",
423 mtk_uart_apdma_read(c, VFF_DEBUG_STATUS));
425 mtk_uart_apdma_write(c, VFF_STOP, VFF_STOP_CLR_B);
426 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B);
428 if (c->dir == DMA_DEV_TO_MEM)
429 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_RX_INT_CLR_B);
430 else if (c->dir == DMA_MEM_TO_DEV)
431 mtk_uart_apdma_write(c, VFF_INT_FLAG, VFF_TX_INT_CLR_B);
433 synchronize_irq(c->irq);
435 spin_lock_irqsave(&c->vc.lock, flags);
436 vchan_get_all_descriptors(&c->vc, &head);
437 spin_unlock_irqrestore(&c->vc.lock, flags);
439 vchan_dma_desc_free_list(&c->vc, &head);
444 static int mtk_uart_apdma_device_pause(struct dma_chan *chan)
446 struct mtk_chan *c = to_mtk_uart_apdma_chan(chan);
449 spin_lock_irqsave(&c->vc.lock, flags);
451 mtk_uart_apdma_write(c, VFF_EN, VFF_EN_CLR_B);
452 mtk_uart_apdma_write(c, VFF_INT_EN, VFF_INT_EN_CLR_B);
454 spin_unlock_irqrestore(&c->vc.lock, flags);
455 synchronize_irq(c->irq);
460 static void mtk_uart_apdma_free(struct mtk_uart_apdmadev *mtkd)
462 while (!list_empty(&mtkd->ddev.channels)) {
463 struct mtk_chan *c = list_first_entry(&mtkd->ddev.channels,
464 struct mtk_chan, vc.chan.device_node);
466 list_del(&c->vc.chan.device_node);
467 tasklet_kill(&c->vc.task);
471 static const struct of_device_id mtk_uart_apdma_match[] = {
472 { .compatible = "mediatek,mt6577-uart-dma", },
475 MODULE_DEVICE_TABLE(of, mtk_uart_apdma_match);
477 static int mtk_uart_apdma_probe(struct platform_device *pdev)
479 struct device_node *np = pdev->dev.of_node;
480 struct mtk_uart_apdmadev *mtkd;
481 int bit_mask = 32, rc;
485 mtkd = devm_kzalloc(&pdev->dev, sizeof(*mtkd), GFP_KERNEL);
489 mtkd->clk = devm_clk_get(&pdev->dev, NULL);
490 if (IS_ERR(mtkd->clk)) {
491 dev_err(&pdev->dev, "No clock specified\n");
492 rc = PTR_ERR(mtkd->clk);
496 if (of_property_read_bool(np, "mediatek,dma-33bits"))
497 mtkd->support_33bits = true;
499 if (mtkd->support_33bits)
502 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(bit_mask));
506 dma_cap_set(DMA_SLAVE, mtkd->ddev.cap_mask);
507 mtkd->ddev.device_alloc_chan_resources =
508 mtk_uart_apdma_alloc_chan_resources;
509 mtkd->ddev.device_free_chan_resources =
510 mtk_uart_apdma_free_chan_resources;
511 mtkd->ddev.device_tx_status = mtk_uart_apdma_tx_status;
512 mtkd->ddev.device_issue_pending = mtk_uart_apdma_issue_pending;
513 mtkd->ddev.device_prep_slave_sg = mtk_uart_apdma_prep_slave_sg;
514 mtkd->ddev.device_config = mtk_uart_apdma_slave_config;
515 mtkd->ddev.device_pause = mtk_uart_apdma_device_pause;
516 mtkd->ddev.device_terminate_all = mtk_uart_apdma_terminate_all;
517 mtkd->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE);
518 mtkd->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE);
519 mtkd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
520 mtkd->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
521 mtkd->ddev.dev = &pdev->dev;
522 INIT_LIST_HEAD(&mtkd->ddev.channels);
524 mtkd->dma_requests = MTK_UART_APDMA_NR_VCHANS;
525 if (of_property_read_u32(np, "dma-requests", &mtkd->dma_requests)) {
527 "Using %u as missing dma-requests property\n",
528 MTK_UART_APDMA_NR_VCHANS);
531 for (i = 0; i < mtkd->dma_requests; i++) {
532 c = devm_kzalloc(mtkd->ddev.dev, sizeof(*c), GFP_KERNEL);
538 c->base = devm_platform_ioremap_resource(pdev, i);
539 if (IS_ERR(c->base)) {
540 rc = PTR_ERR(c->base);
543 c->vc.desc_free = mtk_uart_apdma_desc_free;
544 vchan_init(&c->vc, &mtkd->ddev);
546 rc = platform_get_irq(pdev, i);
552 pm_runtime_enable(&pdev->dev);
553 pm_runtime_set_active(&pdev->dev);
555 rc = dma_async_device_register(&mtkd->ddev);
559 platform_set_drvdata(pdev, mtkd);
561 /* Device-tree DMA controller registration */
562 rc = of_dma_controller_register(np, of_dma_xlate_by_chan_id, mtkd);
569 dma_async_device_unregister(&mtkd->ddev);
571 pm_runtime_disable(&pdev->dev);
573 mtk_uart_apdma_free(mtkd);
577 static int mtk_uart_apdma_remove(struct platform_device *pdev)
579 struct mtk_uart_apdmadev *mtkd = platform_get_drvdata(pdev);
581 of_dma_controller_free(pdev->dev.of_node);
583 mtk_uart_apdma_free(mtkd);
585 dma_async_device_unregister(&mtkd->ddev);
587 pm_runtime_disable(&pdev->dev);
592 #ifdef CONFIG_PM_SLEEP
593 static int mtk_uart_apdma_suspend(struct device *dev)
595 struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
597 if (!pm_runtime_suspended(dev))
598 clk_disable_unprepare(mtkd->clk);
603 static int mtk_uart_apdma_resume(struct device *dev)
606 struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
608 if (!pm_runtime_suspended(dev)) {
609 ret = clk_prepare_enable(mtkd->clk);
616 #endif /* CONFIG_PM_SLEEP */
619 static int mtk_uart_apdma_runtime_suspend(struct device *dev)
621 struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
623 clk_disable_unprepare(mtkd->clk);
628 static int mtk_uart_apdma_runtime_resume(struct device *dev)
630 struct mtk_uart_apdmadev *mtkd = dev_get_drvdata(dev);
632 return clk_prepare_enable(mtkd->clk);
634 #endif /* CONFIG_PM */
636 static const struct dev_pm_ops mtk_uart_apdma_pm_ops = {
637 SET_SYSTEM_SLEEP_PM_OPS(mtk_uart_apdma_suspend, mtk_uart_apdma_resume)
638 SET_RUNTIME_PM_OPS(mtk_uart_apdma_runtime_suspend,
639 mtk_uart_apdma_runtime_resume, NULL)
642 static struct platform_driver mtk_uart_apdma_driver = {
643 .probe = mtk_uart_apdma_probe,
644 .remove = mtk_uart_apdma_remove,
646 .name = KBUILD_MODNAME,
647 .pm = &mtk_uart_apdma_pm_ops,
648 .of_match_table = of_match_ptr(mtk_uart_apdma_match),
652 module_platform_driver(mtk_uart_apdma_driver);
654 MODULE_DESCRIPTION("MediaTek UART APDMA Controller Driver");
655 MODULE_AUTHOR("Long Cheng <long.cheng@mediatek.com>");
656 MODULE_LICENSE("GPL v2");