2 * Copyright (c) 2013 - 2015 Linaro Ltd.
3 * Copyright (c) 2013 Hisilicon Limited.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 #include <linux/sched.h>
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/dmapool.h>
13 #include <linux/dmaengine.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/spinlock.h>
21 #include <linux/of_device.h>
23 #include <linux/clk.h>
24 #include <linux/of_dma.h>
28 #define DRIVER_NAME "k3-dma"
29 #define DMA_MAX_SIZE 0x1ffc
30 #define DMA_CYCLIC_MAX_PERIOD 0x1000
31 #define LLI_BLOCK_SIZE (4 * PAGE_SIZE)
38 #define INT_TC1_MASK 0x18
39 #define INT_TC2_MASK 0x1c
40 #define INT_ERR1_MASK 0x20
41 #define INT_ERR2_MASK 0x24
42 #define INT_TC1_RAW 0x600
43 #define INT_TC2_RAW 0x608
44 #define INT_ERR1_RAW 0x610
45 #define INT_ERR2_RAW 0x618
48 #define CX_CUR_CNT 0x704
56 #define AXI_CFG_DEFAULT 0x201201
58 #define CX_LLI_CHAIN_EN 0x2
60 #define CX_CFG_NODEIRQ BIT(1)
61 #define CX_CFG_MEM2PER (0x1 << 2)
62 #define CX_CFG_PER2MEM (0x2 << 2)
63 #define CX_CFG_SRCINCR (0x1 << 31)
64 #define CX_CFG_DSTINCR (0x1 << 30)
75 struct k3_dma_desc_sw {
76 struct virt_dma_desc vd;
77 dma_addr_t desc_hw_lli;
80 struct k3_desc_hw *desc_hw;
87 struct virt_dma_chan vc;
88 struct k3_dma_phy *phy;
89 struct list_head node;
90 enum dma_transfer_direction dir;
92 enum dma_status status;
99 struct k3_dma_chan *vchan;
100 struct k3_dma_desc_sw *ds_run;
101 struct k3_dma_desc_sw *ds_done;
105 struct dma_device slave;
107 struct tasklet_struct task;
109 struct list_head chan_pending;
110 struct k3_dma_phy *phy;
111 struct k3_dma_chan *chans;
113 struct dma_pool *pool;
119 #define to_k3_dma(dmadev) container_of(dmadev, struct k3_dma_dev, slave)
121 static struct k3_dma_chan *to_k3_chan(struct dma_chan *chan)
123 return container_of(chan, struct k3_dma_chan, vc.chan);
126 static void k3_dma_pause_dma(struct k3_dma_phy *phy, bool on)
131 val = readl_relaxed(phy->base + CX_CFG);
133 writel_relaxed(val, phy->base + CX_CFG);
135 val = readl_relaxed(phy->base + CX_CFG);
137 writel_relaxed(val, phy->base + CX_CFG);
141 static void k3_dma_terminate_chan(struct k3_dma_phy *phy, struct k3_dma_dev *d)
145 k3_dma_pause_dma(phy, false);
147 val = 0x1 << phy->idx;
148 writel_relaxed(val, d->base + INT_TC1_RAW);
149 writel_relaxed(val, d->base + INT_TC2_RAW);
150 writel_relaxed(val, d->base + INT_ERR1_RAW);
151 writel_relaxed(val, d->base + INT_ERR2_RAW);
154 static void k3_dma_set_desc(struct k3_dma_phy *phy, struct k3_desc_hw *hw)
156 writel_relaxed(hw->lli, phy->base + CX_LLI);
157 writel_relaxed(hw->count, phy->base + CX_CNT0);
158 writel_relaxed(hw->saddr, phy->base + CX_SRC);
159 writel_relaxed(hw->daddr, phy->base + CX_DST);
160 writel_relaxed(AXI_CFG_DEFAULT, phy->base + AXI_CFG);
161 writel_relaxed(hw->config, phy->base + CX_CFG);
164 static u32 k3_dma_get_curr_cnt(struct k3_dma_dev *d, struct k3_dma_phy *phy)
168 cnt = readl_relaxed(d->base + CX_CUR_CNT + phy->idx * 0x10);
173 static u32 k3_dma_get_curr_lli(struct k3_dma_phy *phy)
175 return readl_relaxed(phy->base + CX_LLI);
178 static u32 k3_dma_get_chan_stat(struct k3_dma_dev *d)
180 return readl_relaxed(d->base + CH_STAT);
183 static void k3_dma_enable_dma(struct k3_dma_dev *d, bool on)
186 /* set same priority */
187 writel_relaxed(0x0, d->base + CH_PRI);
190 writel_relaxed(0xffff, d->base + INT_TC1_MASK);
191 writel_relaxed(0xffff, d->base + INT_TC2_MASK);
192 writel_relaxed(0xffff, d->base + INT_ERR1_MASK);
193 writel_relaxed(0xffff, d->base + INT_ERR2_MASK);
196 writel_relaxed(0x0, d->base + INT_TC1_MASK);
197 writel_relaxed(0x0, d->base + INT_TC2_MASK);
198 writel_relaxed(0x0, d->base + INT_ERR1_MASK);
199 writel_relaxed(0x0, d->base + INT_ERR2_MASK);
203 static irqreturn_t k3_dma_int_handler(int irq, void *dev_id)
205 struct k3_dma_dev *d = (struct k3_dma_dev *)dev_id;
206 struct k3_dma_phy *p;
207 struct k3_dma_chan *c;
208 u32 stat = readl_relaxed(d->base + INT_STAT);
209 u32 tc1 = readl_relaxed(d->base + INT_TC1);
210 u32 tc2 = readl_relaxed(d->base + INT_TC2);
211 u32 err1 = readl_relaxed(d->base + INT_ERR1);
212 u32 err2 = readl_relaxed(d->base + INT_ERR2);
218 if (likely(tc1 & BIT(i)) || (tc2 & BIT(i))) {
223 if (c && (tc1 & BIT(i))) {
224 spin_lock_irqsave(&c->vc.lock, flags);
225 if (p->ds_run != NULL) {
226 vchan_cookie_complete(&p->ds_run->vd);
227 p->ds_done = p->ds_run;
230 spin_unlock_irqrestore(&c->vc.lock, flags);
232 if (c && (tc2 & BIT(i))) {
233 spin_lock_irqsave(&c->vc.lock, flags);
234 if (p->ds_run != NULL)
235 vchan_cyclic_callback(&p->ds_run->vd);
236 spin_unlock_irqrestore(&c->vc.lock, flags);
240 if (unlikely((err1 & BIT(i)) || (err2 & BIT(i))))
241 dev_warn(d->slave.dev, "DMA ERR\n");
244 writel_relaxed(irq_chan, d->base + INT_TC1_RAW);
245 writel_relaxed(irq_chan, d->base + INT_TC2_RAW);
246 writel_relaxed(err1, d->base + INT_ERR1_RAW);
247 writel_relaxed(err2, d->base + INT_ERR2_RAW);
250 tasklet_schedule(&d->task);
252 if (irq_chan || err1 || err2)
258 static int k3_dma_start_txd(struct k3_dma_chan *c)
260 struct k3_dma_dev *d = to_k3_dma(c->vc.chan.device);
261 struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
266 if (BIT(c->phy->idx) & k3_dma_get_chan_stat(d))
269 /* Avoid losing track of ds_run if a transaction is in flight */
274 struct k3_dma_desc_sw *ds =
275 container_of(vd, struct k3_dma_desc_sw, vd);
277 * fetch and remove request from vc->desc_issued
278 * so vc->desc_issued only contains desc pending
280 list_del(&ds->vd.node);
283 c->phy->ds_done = NULL;
285 k3_dma_set_desc(c->phy, &ds->desc_hw[0]);
288 c->phy->ds_run = NULL;
289 c->phy->ds_done = NULL;
293 static void k3_dma_tasklet(unsigned long arg)
295 struct k3_dma_dev *d = (struct k3_dma_dev *)arg;
296 struct k3_dma_phy *p;
297 struct k3_dma_chan *c, *cn;
298 unsigned pch, pch_alloc = 0;
300 /* check new dma request of running channel in vc->desc_issued */
301 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
302 spin_lock_irq(&c->vc.lock);
304 if (p && p->ds_done) {
305 if (k3_dma_start_txd(c)) {
306 /* No current txd associated with this channel */
307 dev_dbg(d->slave.dev, "pchan %u: free\n", p->idx);
308 /* Mark this channel free */
313 spin_unlock_irq(&c->vc.lock);
316 /* check new channel request in d->chan_pending */
317 spin_lock_irq(&d->lock);
318 for (pch = 0; pch < d->dma_channels; pch++) {
321 if (p->vchan == NULL && !list_empty(&d->chan_pending)) {
322 c = list_first_entry(&d->chan_pending,
323 struct k3_dma_chan, node);
324 /* remove from d->chan_pending */
325 list_del_init(&c->node);
326 pch_alloc |= 1 << pch;
327 /* Mark this channel allocated */
330 dev_dbg(d->slave.dev, "pchan %u: alloc vchan %p\n", pch, &c->vc);
333 spin_unlock_irq(&d->lock);
335 for (pch = 0; pch < d->dma_channels; pch++) {
336 if (pch_alloc & (1 << pch)) {
340 spin_lock_irq(&c->vc.lock);
342 spin_unlock_irq(&c->vc.lock);
348 static void k3_dma_free_chan_resources(struct dma_chan *chan)
350 struct k3_dma_chan *c = to_k3_chan(chan);
351 struct k3_dma_dev *d = to_k3_dma(chan->device);
354 spin_lock_irqsave(&d->lock, flags);
355 list_del_init(&c->node);
356 spin_unlock_irqrestore(&d->lock, flags);
358 vchan_free_chan_resources(&c->vc);
362 static enum dma_status k3_dma_tx_status(struct dma_chan *chan,
363 dma_cookie_t cookie, struct dma_tx_state *state)
365 struct k3_dma_chan *c = to_k3_chan(chan);
366 struct k3_dma_dev *d = to_k3_dma(chan->device);
367 struct k3_dma_phy *p;
368 struct virt_dma_desc *vd;
373 ret = dma_cookie_status(&c->vc.chan, cookie, state);
374 if (ret == DMA_COMPLETE)
377 spin_lock_irqsave(&c->vc.lock, flags);
382 * If the cookie is on our issue queue, then the residue is
385 vd = vchan_find_desc(&c->vc, cookie);
386 if (vd && !c->cyclic) {
387 bytes = container_of(vd, struct k3_dma_desc_sw, vd)->size;
388 } else if ((!p) || (!p->ds_run)) {
391 struct k3_dma_desc_sw *ds = p->ds_run;
392 u32 clli = 0, index = 0;
394 bytes = k3_dma_get_curr_cnt(d, p);
395 clli = k3_dma_get_curr_lli(p);
396 index = ((clli - ds->desc_hw_lli) /
397 sizeof(struct k3_desc_hw)) + 1;
398 for (; index < ds->desc_num; index++) {
399 bytes += ds->desc_hw[index].count;
401 if (!ds->desc_hw[index].lli)
405 spin_unlock_irqrestore(&c->vc.lock, flags);
406 dma_set_residue(state, bytes);
410 static void k3_dma_issue_pending(struct dma_chan *chan)
412 struct k3_dma_chan *c = to_k3_chan(chan);
413 struct k3_dma_dev *d = to_k3_dma(chan->device);
416 spin_lock_irqsave(&c->vc.lock, flags);
417 /* add request to vc->desc_issued */
418 if (vchan_issue_pending(&c->vc)) {
421 if (list_empty(&c->node)) {
422 /* if new channel, add chan_pending */
423 list_add_tail(&c->node, &d->chan_pending);
424 /* check in tasklet */
425 tasklet_schedule(&d->task);
426 dev_dbg(d->slave.dev, "vchan %p: issued\n", &c->vc);
429 spin_unlock(&d->lock);
431 dev_dbg(d->slave.dev, "vchan %p: nothing to issue\n", &c->vc);
432 spin_unlock_irqrestore(&c->vc.lock, flags);
435 static void k3_dma_fill_desc(struct k3_dma_desc_sw *ds, dma_addr_t dst,
436 dma_addr_t src, size_t len, u32 num, u32 ccfg)
438 if (num != ds->desc_num - 1)
439 ds->desc_hw[num].lli = ds->desc_hw_lli + (num + 1) *
440 sizeof(struct k3_desc_hw);
442 ds->desc_hw[num].lli |= CX_LLI_CHAIN_EN;
443 ds->desc_hw[num].count = len;
444 ds->desc_hw[num].saddr = src;
445 ds->desc_hw[num].daddr = dst;
446 ds->desc_hw[num].config = ccfg;
449 static struct k3_dma_desc_sw *k3_dma_alloc_desc_resource(int num,
450 struct dma_chan *chan)
452 struct k3_dma_chan *c = to_k3_chan(chan);
453 struct k3_dma_desc_sw *ds;
454 struct k3_dma_dev *d = to_k3_dma(chan->device);
455 int lli_limit = LLI_BLOCK_SIZE / sizeof(struct k3_desc_hw);
457 if (num > lli_limit) {
458 dev_dbg(chan->device->dev, "vch %p: sg num %d exceed max %d\n",
459 &c->vc, num, lli_limit);
463 ds = kzalloc(sizeof(*ds), GFP_NOWAIT);
467 ds->desc_hw = dma_pool_zalloc(d->pool, GFP_NOWAIT, &ds->desc_hw_lli);
469 dev_dbg(chan->device->dev, "vch %p: dma alloc fail\n", &c->vc);
477 static struct dma_async_tx_descriptor *k3_dma_prep_memcpy(
478 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
479 size_t len, unsigned long flags)
481 struct k3_dma_chan *c = to_k3_chan(chan);
482 struct k3_dma_desc_sw *ds;
489 num = DIV_ROUND_UP(len, DMA_MAX_SIZE);
491 ds = k3_dma_alloc_desc_resource(num, chan);
500 /* default is memtomem, without calling device_config */
501 c->ccfg = CX_CFG_SRCINCR | CX_CFG_DSTINCR | CX_CFG_EN;
502 c->ccfg |= (0xf << 20) | (0xf << 24); /* burst = 16 */
503 c->ccfg |= (0x3 << 12) | (0x3 << 16); /* width = 64 bit */
507 copy = min_t(size_t, len, DMA_MAX_SIZE);
508 k3_dma_fill_desc(ds, dst, src, copy, num++, c->ccfg);
510 if (c->dir == DMA_MEM_TO_DEV) {
512 } else if (c->dir == DMA_DEV_TO_MEM) {
521 ds->desc_hw[num-1].lli = 0; /* end of link */
522 return vchan_tx_prep(&c->vc, &ds->vd, flags);
525 static struct dma_async_tx_descriptor *k3_dma_prep_slave_sg(
526 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sglen,
527 enum dma_transfer_direction dir, unsigned long flags, void *context)
529 struct k3_dma_chan *c = to_k3_chan(chan);
530 struct k3_dma_desc_sw *ds;
531 size_t len, avail, total = 0;
532 struct scatterlist *sg;
533 dma_addr_t addr, src = 0, dst = 0;
541 for_each_sg(sgl, sg, sglen, i) {
542 avail = sg_dma_len(sg);
543 if (avail > DMA_MAX_SIZE)
544 num += DIV_ROUND_UP(avail, DMA_MAX_SIZE) - 1;
547 ds = k3_dma_alloc_desc_resource(num, chan);
552 for_each_sg(sgl, sg, sglen, i) {
553 addr = sg_dma_address(sg);
554 avail = sg_dma_len(sg);
558 len = min_t(size_t, avail, DMA_MAX_SIZE);
560 if (dir == DMA_MEM_TO_DEV) {
563 } else if (dir == DMA_DEV_TO_MEM) {
568 k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg);
575 ds->desc_hw[num-1].lli = 0; /* end of link */
577 return vchan_tx_prep(&c->vc, &ds->vd, flags);
580 static struct dma_async_tx_descriptor *
581 k3_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
582 size_t buf_len, size_t period_len,
583 enum dma_transfer_direction dir,
586 struct k3_dma_chan *c = to_k3_chan(chan);
587 struct k3_dma_desc_sw *ds;
588 size_t len, avail, total = 0;
589 dma_addr_t addr, src = 0, dst = 0;
590 int num = 1, since = 0;
591 size_t modulo = DMA_CYCLIC_MAX_PERIOD;
594 dev_dbg(chan->device->dev, "%s: buf %pad, dst %pad, buf len %zu, period_len = %zu, dir %d\n",
595 __func__, &buf_addr, &to_k3_chan(chan)->dev_addr,
596 buf_len, period_len, (int)dir);
600 num += DIV_ROUND_UP(avail, modulo) - 1;
602 ds = k3_dma_alloc_desc_resource(num, chan);
612 if (period_len < modulo)
616 len = min_t(size_t, avail, modulo);
618 if (dir == DMA_MEM_TO_DEV) {
621 } else if (dir == DMA_DEV_TO_MEM) {
626 if (since >= period_len) {
627 /* descriptor asks for TC2 interrupt on completion */
628 en_tc2 = CX_CFG_NODEIRQ;
633 k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg | en_tc2);
639 /* "Cyclic" == end of link points back to start of link */
640 ds->desc_hw[num - 1].lli |= ds->desc_hw_lli;
644 return vchan_tx_prep(&c->vc, &ds->vd, flags);
647 static int k3_dma_config(struct dma_chan *chan,
648 struct dma_slave_config *cfg)
650 struct k3_dma_chan *c = to_k3_chan(chan);
651 u32 maxburst = 0, val = 0;
652 enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
656 c->dir = cfg->direction;
657 if (c->dir == DMA_DEV_TO_MEM) {
658 c->ccfg = CX_CFG_DSTINCR;
659 c->dev_addr = cfg->src_addr;
660 maxburst = cfg->src_maxburst;
661 width = cfg->src_addr_width;
662 } else if (c->dir == DMA_MEM_TO_DEV) {
663 c->ccfg = CX_CFG_SRCINCR;
664 c->dev_addr = cfg->dst_addr;
665 maxburst = cfg->dst_maxburst;
666 width = cfg->dst_addr_width;
669 case DMA_SLAVE_BUSWIDTH_1_BYTE:
670 case DMA_SLAVE_BUSWIDTH_2_BYTES:
671 case DMA_SLAVE_BUSWIDTH_4_BYTES:
672 case DMA_SLAVE_BUSWIDTH_8_BYTES:
679 c->ccfg |= (val << 12) | (val << 16);
681 if ((maxburst == 0) || (maxburst > 16))
685 c->ccfg |= (val << 20) | (val << 24);
686 c->ccfg |= CX_CFG_MEM2PER | CX_CFG_EN;
688 /* specific request line */
689 c->ccfg |= c->vc.chan.chan_id << 4;
694 static void k3_dma_free_desc(struct virt_dma_desc *vd)
696 struct k3_dma_desc_sw *ds =
697 container_of(vd, struct k3_dma_desc_sw, vd);
698 struct k3_dma_dev *d = to_k3_dma(vd->tx.chan->device);
700 dma_pool_free(d->pool, ds->desc_hw, ds->desc_hw_lli);
704 static int k3_dma_terminate_all(struct dma_chan *chan)
706 struct k3_dma_chan *c = to_k3_chan(chan);
707 struct k3_dma_dev *d = to_k3_dma(chan->device);
708 struct k3_dma_phy *p = c->phy;
712 dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc);
714 /* Prevent this channel being scheduled */
716 list_del_init(&c->node);
717 spin_unlock(&d->lock);
719 /* Clear the tx descriptor lists */
720 spin_lock_irqsave(&c->vc.lock, flags);
721 vchan_get_all_descriptors(&c->vc, &head);
723 /* vchan is assigned to a pchan - stop the channel */
724 k3_dma_terminate_chan(p, d);
728 k3_dma_free_desc(&p->ds_run->vd);
733 spin_unlock_irqrestore(&c->vc.lock, flags);
734 vchan_dma_desc_free_list(&c->vc, &head);
739 static int k3_dma_transfer_pause(struct dma_chan *chan)
741 struct k3_dma_chan *c = to_k3_chan(chan);
742 struct k3_dma_dev *d = to_k3_dma(chan->device);
743 struct k3_dma_phy *p = c->phy;
745 dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc);
746 if (c->status == DMA_IN_PROGRESS) {
747 c->status = DMA_PAUSED;
749 k3_dma_pause_dma(p, false);
752 list_del_init(&c->node);
753 spin_unlock(&d->lock);
760 static int k3_dma_transfer_resume(struct dma_chan *chan)
762 struct k3_dma_chan *c = to_k3_chan(chan);
763 struct k3_dma_dev *d = to_k3_dma(chan->device);
764 struct k3_dma_phy *p = c->phy;
767 dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc);
768 spin_lock_irqsave(&c->vc.lock, flags);
769 if (c->status == DMA_PAUSED) {
770 c->status = DMA_IN_PROGRESS;
772 k3_dma_pause_dma(p, true);
773 } else if (!list_empty(&c->vc.desc_issued)) {
775 list_add_tail(&c->node, &d->chan_pending);
776 spin_unlock(&d->lock);
779 spin_unlock_irqrestore(&c->vc.lock, flags);
784 static const struct of_device_id k3_pdma_dt_ids[] = {
785 { .compatible = "hisilicon,k3-dma-1.0", },
788 MODULE_DEVICE_TABLE(of, k3_pdma_dt_ids);
790 static struct dma_chan *k3_of_dma_simple_xlate(struct of_phandle_args *dma_spec,
791 struct of_dma *ofdma)
793 struct k3_dma_dev *d = ofdma->of_dma_data;
794 unsigned int request = dma_spec->args[0];
796 if (request >= d->dma_requests)
799 return dma_get_slave_channel(&(d->chans[request].vc.chan));
802 static int k3_dma_probe(struct platform_device *op)
804 struct k3_dma_dev *d;
805 const struct of_device_id *of_id;
806 struct resource *iores;
809 iores = platform_get_resource(op, IORESOURCE_MEM, 0);
813 d = devm_kzalloc(&op->dev, sizeof(*d), GFP_KERNEL);
817 d->base = devm_ioremap_resource(&op->dev, iores);
819 return PTR_ERR(d->base);
821 of_id = of_match_device(k3_pdma_dt_ids, &op->dev);
823 of_property_read_u32((&op->dev)->of_node,
824 "dma-channels", &d->dma_channels);
825 of_property_read_u32((&op->dev)->of_node,
826 "dma-requests", &d->dma_requests);
829 d->clk = devm_clk_get(&op->dev, NULL);
830 if (IS_ERR(d->clk)) {
831 dev_err(&op->dev, "no dma clk\n");
832 return PTR_ERR(d->clk);
835 irq = platform_get_irq(op, 0);
836 ret = devm_request_irq(&op->dev, irq,
837 k3_dma_int_handler, 0, DRIVER_NAME, d);
843 /* A DMA memory pool for LLIs, align on 32-byte boundary */
844 d->pool = dmam_pool_create(DRIVER_NAME, &op->dev,
845 LLI_BLOCK_SIZE, 32, 0);
849 /* init phy channel */
850 d->phy = devm_kzalloc(&op->dev,
851 d->dma_channels * sizeof(struct k3_dma_phy), GFP_KERNEL);
855 for (i = 0; i < d->dma_channels; i++) {
856 struct k3_dma_phy *p = &d->phy[i];
859 p->base = d->base + i * 0x40;
862 INIT_LIST_HEAD(&d->slave.channels);
863 dma_cap_set(DMA_SLAVE, d->slave.cap_mask);
864 dma_cap_set(DMA_MEMCPY, d->slave.cap_mask);
865 dma_cap_set(DMA_CYCLIC, d->slave.cap_mask);
866 d->slave.dev = &op->dev;
867 d->slave.device_free_chan_resources = k3_dma_free_chan_resources;
868 d->slave.device_tx_status = k3_dma_tx_status;
869 d->slave.device_prep_dma_memcpy = k3_dma_prep_memcpy;
870 d->slave.device_prep_slave_sg = k3_dma_prep_slave_sg;
871 d->slave.device_prep_dma_cyclic = k3_dma_prep_dma_cyclic;
872 d->slave.device_issue_pending = k3_dma_issue_pending;
873 d->slave.device_config = k3_dma_config;
874 d->slave.device_pause = k3_dma_transfer_pause;
875 d->slave.device_resume = k3_dma_transfer_resume;
876 d->slave.device_terminate_all = k3_dma_terminate_all;
877 d->slave.copy_align = DMAENGINE_ALIGN_8_BYTES;
879 /* init virtual channel */
880 d->chans = devm_kzalloc(&op->dev,
881 d->dma_requests * sizeof(struct k3_dma_chan), GFP_KERNEL);
882 if (d->chans == NULL)
885 for (i = 0; i < d->dma_requests; i++) {
886 struct k3_dma_chan *c = &d->chans[i];
888 c->status = DMA_IN_PROGRESS;
889 INIT_LIST_HEAD(&c->node);
890 c->vc.desc_free = k3_dma_free_desc;
891 vchan_init(&c->vc, &d->slave);
894 /* Enable clock before accessing registers */
895 ret = clk_prepare_enable(d->clk);
897 dev_err(&op->dev, "clk_prepare_enable failed: %d\n", ret);
901 k3_dma_enable_dma(d, true);
903 ret = dma_async_device_register(&d->slave);
905 goto dma_async_register_fail;
907 ret = of_dma_controller_register((&op->dev)->of_node,
908 k3_of_dma_simple_xlate, d);
910 goto of_dma_register_fail;
912 spin_lock_init(&d->lock);
913 INIT_LIST_HEAD(&d->chan_pending);
914 tasklet_init(&d->task, k3_dma_tasklet, (unsigned long)d);
915 platform_set_drvdata(op, d);
916 dev_info(&op->dev, "initialized\n");
920 of_dma_register_fail:
921 dma_async_device_unregister(&d->slave);
922 dma_async_register_fail:
923 clk_disable_unprepare(d->clk);
927 static int k3_dma_remove(struct platform_device *op)
929 struct k3_dma_chan *c, *cn;
930 struct k3_dma_dev *d = platform_get_drvdata(op);
932 dma_async_device_unregister(&d->slave);
933 of_dma_controller_free((&op->dev)->of_node);
935 devm_free_irq(&op->dev, d->irq, d);
937 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) {
938 list_del(&c->vc.chan.device_node);
939 tasklet_kill(&c->vc.task);
941 tasklet_kill(&d->task);
942 clk_disable_unprepare(d->clk);
946 #ifdef CONFIG_PM_SLEEP
947 static int k3_dma_suspend_dev(struct device *dev)
949 struct k3_dma_dev *d = dev_get_drvdata(dev);
952 stat = k3_dma_get_chan_stat(d);
954 dev_warn(d->slave.dev,
955 "chan %d is running fail to suspend\n", stat);
958 k3_dma_enable_dma(d, false);
959 clk_disable_unprepare(d->clk);
963 static int k3_dma_resume_dev(struct device *dev)
965 struct k3_dma_dev *d = dev_get_drvdata(dev);
968 ret = clk_prepare_enable(d->clk);
970 dev_err(d->slave.dev, "clk_prepare_enable failed: %d\n", ret);
973 k3_dma_enable_dma(d, true);
978 static SIMPLE_DEV_PM_OPS(k3_dma_pmops, k3_dma_suspend_dev, k3_dma_resume_dev);
980 static struct platform_driver k3_pdma_driver = {
984 .of_match_table = k3_pdma_dt_ids,
986 .probe = k3_dma_probe,
987 .remove = k3_dma_remove,
990 module_platform_driver(k3_pdma_driver);
992 MODULE_DESCRIPTION("Hisilicon k3 DMA Driver");
993 MODULE_ALIAS("platform:k3dma");
994 MODULE_LICENSE("GPL v2");