1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel I/OAT DMA Linux driver
4 * Copyright(c) 2004 - 2015 Intel Corporation.
7 #include <linux/init.h>
8 #include <linux/module.h>
9 #include <linux/slab.h>
10 #include <linux/pci.h>
11 #include <linux/interrupt.h>
12 #include <linux/dmaengine.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/workqueue.h>
16 #include <linux/prefetch.h>
17 #include <linux/dca.h>
18 #include <linux/aer.h>
19 #include <linux/sizes.h>
21 #include "registers.h"
24 #include "../dmaengine.h"
26 MODULE_VERSION(IOAT_DMA_VERSION);
27 MODULE_LICENSE("Dual BSD/GPL");
28 MODULE_AUTHOR("Intel Corporation");
30 static const struct pci_device_id ioat_pci_tbl[] = {
31 /* I/OAT v3 platforms */
32 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) },
33 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) },
34 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) },
35 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) },
36 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) },
37 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) },
38 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) },
39 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) },
41 /* I/OAT v3.2 platforms */
42 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) },
43 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) },
44 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) },
45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) },
46 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) },
47 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) },
48 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) },
49 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) },
50 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) },
51 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) },
53 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) },
54 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) },
55 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) },
56 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) },
57 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) },
58 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) },
59 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) },
60 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) },
61 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) },
62 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) },
64 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) },
65 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) },
66 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) },
67 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) },
68 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) },
69 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) },
70 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) },
71 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) },
72 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) },
73 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) },
75 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) },
76 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) },
77 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) },
78 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) },
79 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) },
80 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) },
81 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) },
82 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) },
83 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) },
84 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) },
86 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0) },
87 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1) },
88 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2) },
89 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3) },
90 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4) },
91 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5) },
92 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6) },
93 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7) },
94 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8) },
95 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9) },
97 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SKX) },
99 /* I/OAT v3.3 platforms */
100 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) },
101 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) },
102 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) },
103 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) },
105 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) },
106 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) },
107 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) },
108 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) },
110 /* I/OAT v3.4 platforms */
111 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_ICX) },
115 MODULE_DEVICE_TABLE(pci, ioat_pci_tbl);
117 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
118 static void ioat_remove(struct pci_dev *pdev);
120 ioat_init_channel(struct ioatdma_device *ioat_dma,
121 struct ioatdma_chan *ioat_chan, int idx);
122 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma);
123 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma);
124 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma);
126 static int ioat_dca_enabled = 1;
127 module_param(ioat_dca_enabled, int, 0644);
128 MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)");
129 int ioat_pending_level = 7;
130 module_param(ioat_pending_level, int, 0644);
131 MODULE_PARM_DESC(ioat_pending_level,
132 "high-water mark for pushing ioat descriptors (default: 7)");
133 static char ioat_interrupt_style[32] = "msix";
134 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
135 sizeof(ioat_interrupt_style), 0644);
136 MODULE_PARM_DESC(ioat_interrupt_style,
137 "set ioat interrupt style: msix (default), msi, intx");
139 struct kmem_cache *ioat_cache;
140 struct kmem_cache *ioat_sed_cache;
142 static bool is_jf_ioat(struct pci_dev *pdev)
144 switch (pdev->device) {
145 case PCI_DEVICE_ID_INTEL_IOAT_JSF0:
146 case PCI_DEVICE_ID_INTEL_IOAT_JSF1:
147 case PCI_DEVICE_ID_INTEL_IOAT_JSF2:
148 case PCI_DEVICE_ID_INTEL_IOAT_JSF3:
149 case PCI_DEVICE_ID_INTEL_IOAT_JSF4:
150 case PCI_DEVICE_ID_INTEL_IOAT_JSF5:
151 case PCI_DEVICE_ID_INTEL_IOAT_JSF6:
152 case PCI_DEVICE_ID_INTEL_IOAT_JSF7:
153 case PCI_DEVICE_ID_INTEL_IOAT_JSF8:
154 case PCI_DEVICE_ID_INTEL_IOAT_JSF9:
161 static bool is_snb_ioat(struct pci_dev *pdev)
163 switch (pdev->device) {
164 case PCI_DEVICE_ID_INTEL_IOAT_SNB0:
165 case PCI_DEVICE_ID_INTEL_IOAT_SNB1:
166 case PCI_DEVICE_ID_INTEL_IOAT_SNB2:
167 case PCI_DEVICE_ID_INTEL_IOAT_SNB3:
168 case PCI_DEVICE_ID_INTEL_IOAT_SNB4:
169 case PCI_DEVICE_ID_INTEL_IOAT_SNB5:
170 case PCI_DEVICE_ID_INTEL_IOAT_SNB6:
171 case PCI_DEVICE_ID_INTEL_IOAT_SNB7:
172 case PCI_DEVICE_ID_INTEL_IOAT_SNB8:
173 case PCI_DEVICE_ID_INTEL_IOAT_SNB9:
180 static bool is_ivb_ioat(struct pci_dev *pdev)
182 switch (pdev->device) {
183 case PCI_DEVICE_ID_INTEL_IOAT_IVB0:
184 case PCI_DEVICE_ID_INTEL_IOAT_IVB1:
185 case PCI_DEVICE_ID_INTEL_IOAT_IVB2:
186 case PCI_DEVICE_ID_INTEL_IOAT_IVB3:
187 case PCI_DEVICE_ID_INTEL_IOAT_IVB4:
188 case PCI_DEVICE_ID_INTEL_IOAT_IVB5:
189 case PCI_DEVICE_ID_INTEL_IOAT_IVB6:
190 case PCI_DEVICE_ID_INTEL_IOAT_IVB7:
191 case PCI_DEVICE_ID_INTEL_IOAT_IVB8:
192 case PCI_DEVICE_ID_INTEL_IOAT_IVB9:
200 static bool is_hsw_ioat(struct pci_dev *pdev)
202 switch (pdev->device) {
203 case PCI_DEVICE_ID_INTEL_IOAT_HSW0:
204 case PCI_DEVICE_ID_INTEL_IOAT_HSW1:
205 case PCI_DEVICE_ID_INTEL_IOAT_HSW2:
206 case PCI_DEVICE_ID_INTEL_IOAT_HSW3:
207 case PCI_DEVICE_ID_INTEL_IOAT_HSW4:
208 case PCI_DEVICE_ID_INTEL_IOAT_HSW5:
209 case PCI_DEVICE_ID_INTEL_IOAT_HSW6:
210 case PCI_DEVICE_ID_INTEL_IOAT_HSW7:
211 case PCI_DEVICE_ID_INTEL_IOAT_HSW8:
212 case PCI_DEVICE_ID_INTEL_IOAT_HSW9:
220 static bool is_bdx_ioat(struct pci_dev *pdev)
222 switch (pdev->device) {
223 case PCI_DEVICE_ID_INTEL_IOAT_BDX0:
224 case PCI_DEVICE_ID_INTEL_IOAT_BDX1:
225 case PCI_DEVICE_ID_INTEL_IOAT_BDX2:
226 case PCI_DEVICE_ID_INTEL_IOAT_BDX3:
227 case PCI_DEVICE_ID_INTEL_IOAT_BDX4:
228 case PCI_DEVICE_ID_INTEL_IOAT_BDX5:
229 case PCI_DEVICE_ID_INTEL_IOAT_BDX6:
230 case PCI_DEVICE_ID_INTEL_IOAT_BDX7:
231 case PCI_DEVICE_ID_INTEL_IOAT_BDX8:
232 case PCI_DEVICE_ID_INTEL_IOAT_BDX9:
239 static inline bool is_skx_ioat(struct pci_dev *pdev)
241 return (pdev->device == PCI_DEVICE_ID_INTEL_IOAT_SKX) ? true : false;
244 static bool is_xeon_cb32(struct pci_dev *pdev)
246 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) ||
247 is_hsw_ioat(pdev) || is_bdx_ioat(pdev) || is_skx_ioat(pdev);
250 bool is_bwd_ioat(struct pci_dev *pdev)
252 switch (pdev->device) {
253 case PCI_DEVICE_ID_INTEL_IOAT_BWD0:
254 case PCI_DEVICE_ID_INTEL_IOAT_BWD1:
255 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
256 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
257 /* even though not Atom, BDX-DE has same DMA silicon */
258 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
259 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
260 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
261 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
268 static bool is_bwd_noraid(struct pci_dev *pdev)
270 switch (pdev->device) {
271 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
272 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
273 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
274 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
275 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
276 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
285 * Perform a IOAT transaction to verify the HW works.
287 #define IOAT_TEST_SIZE 2000
289 static void ioat_dma_test_callback(void *dma_async_param)
291 struct completion *cmp = dma_async_param;
297 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
298 * @ioat_dma: dma device to be tested
300 static int ioat_dma_self_test(struct ioatdma_device *ioat_dma)
305 struct dma_device *dma = &ioat_dma->dma_dev;
306 struct device *dev = &ioat_dma->pdev->dev;
307 struct dma_chan *dma_chan;
308 struct dma_async_tx_descriptor *tx;
309 dma_addr_t dma_dest, dma_src;
312 struct completion cmp;
316 src = kzalloc(IOAT_TEST_SIZE, GFP_KERNEL);
319 dest = kzalloc(IOAT_TEST_SIZE, GFP_KERNEL);
325 /* Fill in src buffer */
326 for (i = 0; i < IOAT_TEST_SIZE; i++)
329 /* Start copy, using first DMA channel */
330 dma_chan = container_of(dma->channels.next, struct dma_chan,
332 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
333 dev_err(dev, "selftest cannot allocate chan resource\n");
338 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
339 if (dma_mapping_error(dev, dma_src)) {
340 dev_err(dev, "mapping src buffer failed\n");
344 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
345 if (dma_mapping_error(dev, dma_dest)) {
346 dev_err(dev, "mapping dest buffer failed\n");
350 flags = DMA_PREP_INTERRUPT;
351 tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest,
352 dma_src, IOAT_TEST_SIZE,
355 dev_err(dev, "Self-test prep failed, disabling\n");
361 init_completion(&cmp);
362 tx->callback = ioat_dma_test_callback;
363 tx->callback_param = &cmp;
364 cookie = tx->tx_submit(tx);
366 dev_err(dev, "Self-test setup failed, disabling\n");
370 dma->device_issue_pending(dma_chan);
372 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
375 dma->device_tx_status(dma_chan, cookie, NULL)
377 dev_err(dev, "Self-test copy timed out, disabling\n");
381 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
382 dev_err(dev, "Self-test copy failed compare, disabling\n");
388 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
390 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
392 dma->device_free_chan_resources(dma_chan);
400 * ioat_dma_setup_interrupts - setup interrupt handler
401 * @ioat_dma: ioat dma device
403 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma)
405 struct ioatdma_chan *ioat_chan;
406 struct pci_dev *pdev = ioat_dma->pdev;
407 struct device *dev = &pdev->dev;
408 struct msix_entry *msix;
413 if (!strcmp(ioat_interrupt_style, "msix"))
415 if (!strcmp(ioat_interrupt_style, "msi"))
417 if (!strcmp(ioat_interrupt_style, "intx"))
419 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
423 /* The number of MSI-X vectors should equal the number of channels */
424 msixcnt = ioat_dma->dma_dev.chancnt;
425 for (i = 0; i < msixcnt; i++)
426 ioat_dma->msix_entries[i].entry = i;
428 err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt);
432 for (i = 0; i < msixcnt; i++) {
433 msix = &ioat_dma->msix_entries[i];
434 ioat_chan = ioat_chan_by_index(ioat_dma, i);
435 err = devm_request_irq(dev, msix->vector,
436 ioat_dma_do_interrupt_msix, 0,
437 "ioat-msix", ioat_chan);
439 for (j = 0; j < i; j++) {
440 msix = &ioat_dma->msix_entries[j];
441 ioat_chan = ioat_chan_by_index(ioat_dma, j);
442 devm_free_irq(dev, msix->vector, ioat_chan);
447 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
448 ioat_dma->irq_mode = IOAT_MSIX;
452 err = pci_enable_msi(pdev);
456 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
457 "ioat-msi", ioat_dma);
459 pci_disable_msi(pdev);
462 ioat_dma->irq_mode = IOAT_MSI;
466 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
467 IRQF_SHARED, "ioat-intx", ioat_dma);
471 ioat_dma->irq_mode = IOAT_INTX;
473 if (is_bwd_ioat(pdev))
474 ioat_intr_quirk(ioat_dma);
475 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
476 writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
480 /* Disable all interrupt generation */
481 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
482 ioat_dma->irq_mode = IOAT_NOIRQ;
483 dev_err(dev, "no usable interrupts\n");
487 static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma)
489 /* Disable all interrupt generation */
490 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
493 static int ioat_probe(struct ioatdma_device *ioat_dma)
496 struct dma_device *dma = &ioat_dma->dma_dev;
497 struct pci_dev *pdev = ioat_dma->pdev;
498 struct device *dev = &pdev->dev;
500 ioat_dma->completion_pool = dma_pool_create("completion_pool", dev,
505 if (!ioat_dma->completion_pool) {
510 ioat_enumerate_channels(ioat_dma);
512 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
513 dma->dev = &pdev->dev;
516 dev_err(dev, "channel enumeration error\n");
517 goto err_setup_interrupts;
520 err = ioat_dma_setup_interrupts(ioat_dma);
522 goto err_setup_interrupts;
524 err = ioat3_dma_self_test(ioat_dma);
531 ioat_disable_interrupts(ioat_dma);
532 err_setup_interrupts:
533 dma_pool_destroy(ioat_dma->completion_pool);
538 static int ioat_register(struct ioatdma_device *ioat_dma)
540 int err = dma_async_device_register(&ioat_dma->dma_dev);
543 ioat_disable_interrupts(ioat_dma);
544 dma_pool_destroy(ioat_dma->completion_pool);
550 static void ioat_dma_remove(struct ioatdma_device *ioat_dma)
552 struct dma_device *dma = &ioat_dma->dma_dev;
554 ioat_disable_interrupts(ioat_dma);
556 ioat_kobject_del(ioat_dma);
558 dma_async_device_unregister(dma);
562 * ioat_enumerate_channels - find and initialize the device's channels
563 * @ioat_dma: the ioat dma device to be enumerated
565 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma)
567 struct ioatdma_chan *ioat_chan;
568 struct device *dev = &ioat_dma->pdev->dev;
569 struct dma_device *dma = &ioat_dma->dma_dev;
573 INIT_LIST_HEAD(&dma->channels);
574 dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET);
575 dma->chancnt &= 0x1f; /* bits [4:0] valid */
576 if (dma->chancnt > ARRAY_SIZE(ioat_dma->idx)) {
577 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
578 dma->chancnt, ARRAY_SIZE(ioat_dma->idx));
579 dma->chancnt = ARRAY_SIZE(ioat_dma->idx);
581 xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET);
582 xfercap_log &= 0x1f; /* bits [4:0] valid */
583 if (xfercap_log == 0)
585 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
587 for (i = 0; i < dma->chancnt; i++) {
588 ioat_chan = kzalloc(sizeof(*ioat_chan), GFP_KERNEL);
592 ioat_init_channel(ioat_dma, ioat_chan, i);
593 ioat_chan->xfercap_log = xfercap_log;
594 spin_lock_init(&ioat_chan->prep_lock);
595 if (ioat_reset_hw(ioat_chan)) {
604 * ioat_free_chan_resources - release all the descriptors
605 * @c: the channel to be cleaned
607 static void ioat_free_chan_resources(struct dma_chan *c)
609 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
610 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
611 struct ioat_ring_ent *desc;
612 const int total_descs = 1 << ioat_chan->alloc_order;
616 /* Before freeing channel resources first check
617 * if they have been previously allocated for this channel.
619 if (!ioat_chan->ring)
622 ioat_stop(ioat_chan);
624 if (!test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) {
625 ioat_reset_hw(ioat_chan);
627 /* Put LTR to idle */
628 if (ioat_dma->version >= IOAT_VER_3_4)
629 writeb(IOAT_CHAN_LTR_SWSEL_IDLE,
630 ioat_chan->reg_base +
631 IOAT_CHAN_LTR_SWSEL_OFFSET);
634 spin_lock_bh(&ioat_chan->cleanup_lock);
635 spin_lock_bh(&ioat_chan->prep_lock);
636 descs = ioat_ring_space(ioat_chan);
637 dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs);
638 for (i = 0; i < descs; i++) {
639 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i);
640 ioat_free_ring_ent(desc, c);
643 if (descs < total_descs)
644 dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n",
645 total_descs - descs);
647 for (i = 0; i < total_descs - descs; i++) {
648 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i);
649 dump_desc_dbg(ioat_chan, desc);
650 ioat_free_ring_ent(desc, c);
653 for (i = 0; i < ioat_chan->desc_chunks; i++) {
654 dma_free_coherent(to_dev(ioat_chan), IOAT_CHUNK_SIZE,
655 ioat_chan->descs[i].virt,
656 ioat_chan->descs[i].hw);
657 ioat_chan->descs[i].virt = NULL;
658 ioat_chan->descs[i].hw = 0;
660 ioat_chan->desc_chunks = 0;
662 kfree(ioat_chan->ring);
663 ioat_chan->ring = NULL;
664 ioat_chan->alloc_order = 0;
665 dma_pool_free(ioat_dma->completion_pool, ioat_chan->completion,
666 ioat_chan->completion_dma);
667 spin_unlock_bh(&ioat_chan->prep_lock);
668 spin_unlock_bh(&ioat_chan->cleanup_lock);
670 ioat_chan->last_completion = 0;
671 ioat_chan->completion_dma = 0;
672 ioat_chan->dmacount = 0;
675 /* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring
676 * @chan: channel to be initialized
678 static int ioat_alloc_chan_resources(struct dma_chan *c)
680 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
681 struct ioat_ring_ent **ring;
687 /* have we already been set up? */
689 return 1 << ioat_chan->alloc_order;
691 /* Setup register to interrupt and write completion status on error */
692 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
694 /* allocate a completion writeback area */
695 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
696 ioat_chan->completion =
697 dma_pool_zalloc(ioat_chan->ioat_dma->completion_pool,
698 GFP_NOWAIT, &ioat_chan->completion_dma);
699 if (!ioat_chan->completion)
702 writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF,
703 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
704 writel(((u64)ioat_chan->completion_dma) >> 32,
705 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
707 order = IOAT_MAX_ORDER;
708 ring = ioat_alloc_ring(c, order, GFP_NOWAIT);
712 spin_lock_bh(&ioat_chan->cleanup_lock);
713 spin_lock_bh(&ioat_chan->prep_lock);
714 ioat_chan->ring = ring;
716 ioat_chan->issued = 0;
718 ioat_chan->alloc_order = order;
719 set_bit(IOAT_RUN, &ioat_chan->state);
720 spin_unlock_bh(&ioat_chan->prep_lock);
721 spin_unlock_bh(&ioat_chan->cleanup_lock);
723 /* Setting up LTR values for 3.4 or later */
724 if (ioat_chan->ioat_dma->version >= IOAT_VER_3_4) {
727 lat_val = IOAT_CHAN_LTR_ACTIVE_SNVAL |
728 IOAT_CHAN_LTR_ACTIVE_SNLATSCALE |
729 IOAT_CHAN_LTR_ACTIVE_SNREQMNT;
730 writel(lat_val, ioat_chan->reg_base +
731 IOAT_CHAN_LTR_ACTIVE_OFFSET);
733 lat_val = IOAT_CHAN_LTR_IDLE_SNVAL |
734 IOAT_CHAN_LTR_IDLE_SNLATSCALE |
735 IOAT_CHAN_LTR_IDLE_SNREQMNT;
736 writel(lat_val, ioat_chan->reg_base +
737 IOAT_CHAN_LTR_IDLE_OFFSET);
739 /* Select to active */
740 writeb(IOAT_CHAN_LTR_SWSEL_ACTIVE,
741 ioat_chan->reg_base +
742 IOAT_CHAN_LTR_SWSEL_OFFSET);
745 ioat_start_null_desc(ioat_chan);
747 /* check that we got off the ground */
750 status = ioat_chansts(ioat_chan);
751 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status));
753 if (is_ioat_active(status) || is_ioat_idle(status))
754 return 1 << ioat_chan->alloc_order;
756 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
758 dev_WARN(to_dev(ioat_chan),
759 "failed to start channel chanerr: %#x\n", chanerr);
760 ioat_free_chan_resources(c);
764 /* common channel initialization */
766 ioat_init_channel(struct ioatdma_device *ioat_dma,
767 struct ioatdma_chan *ioat_chan, int idx)
769 struct dma_device *dma = &ioat_dma->dma_dev;
771 ioat_chan->ioat_dma = ioat_dma;
772 ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1));
773 spin_lock_init(&ioat_chan->cleanup_lock);
774 ioat_chan->dma_chan.device = dma;
775 dma_cookie_init(&ioat_chan->dma_chan);
776 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels);
777 ioat_dma->idx[idx] = ioat_chan;
778 timer_setup(&ioat_chan->timer, ioat_timer_event, 0);
779 tasklet_setup(&ioat_chan->cleanup_task, ioat_cleanup_event);
782 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
783 static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma)
787 struct page *xor_srcs[IOAT_NUM_SRC_TEST];
788 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1];
789 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1];
791 struct dma_async_tx_descriptor *tx;
792 struct dma_chan *dma_chan;
798 struct completion cmp;
800 struct device *dev = &ioat_dma->pdev->dev;
801 struct dma_device *dma = &ioat_dma->dma_dev;
804 dev_dbg(dev, "%s\n", __func__);
806 if (!dma_has_cap(DMA_XOR, dma->cap_mask))
809 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
810 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
811 if (!xor_srcs[src_idx]) {
813 __free_page(xor_srcs[src_idx]);
818 dest = alloc_page(GFP_KERNEL);
821 __free_page(xor_srcs[src_idx]);
825 /* Fill in src buffers */
826 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
827 u8 *ptr = page_address(xor_srcs[src_idx]);
829 for (i = 0; i < PAGE_SIZE; i++)
830 ptr[i] = (1 << src_idx);
833 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++)
834 cmp_byte ^= (u8) (1 << src_idx);
836 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
837 (cmp_byte << 8) | cmp_byte;
839 memset(page_address(dest), 0, PAGE_SIZE);
841 dma_chan = container_of(dma->channels.next, struct dma_chan,
843 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
851 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE);
852 if (dma_mapping_error(dev, dest_dma)) {
857 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) {
858 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE,
860 if (dma_mapping_error(dev, dma_srcs[i])) {
865 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
866 IOAT_NUM_SRC_TEST, PAGE_SIZE,
870 dev_err(dev, "Self-test xor prep failed\n");
876 init_completion(&cmp);
877 tx->callback = ioat_dma_test_callback;
878 tx->callback_param = &cmp;
879 cookie = tx->tx_submit(tx);
881 dev_err(dev, "Self-test xor setup failed\n");
885 dma->device_issue_pending(dma_chan);
887 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
890 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
891 dev_err(dev, "Self-test xor timed out\n");
896 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
897 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
899 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
900 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
901 u32 *ptr = page_address(dest);
903 if (ptr[i] != cmp_word) {
904 dev_err(dev, "Self-test xor failed compare\n");
909 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
911 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
913 /* skip validate if the capability is not present */
914 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
917 op = IOAT_OP_XOR_VAL;
919 /* validate the sources with the destintation page */
920 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
921 xor_val_srcs[i] = xor_srcs[i];
922 xor_val_srcs[i] = dest;
926 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
927 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
929 if (dma_mapping_error(dev, dma_srcs[i])) {
934 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
935 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
936 &xor_val_result, DMA_PREP_INTERRUPT);
938 dev_err(dev, "Self-test zero prep failed\n");
944 init_completion(&cmp);
945 tx->callback = ioat_dma_test_callback;
946 tx->callback_param = &cmp;
947 cookie = tx->tx_submit(tx);
949 dev_err(dev, "Self-test zero setup failed\n");
953 dma->device_issue_pending(dma_chan);
955 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
958 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
959 dev_err(dev, "Self-test validate timed out\n");
964 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
965 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
967 if (xor_val_result != 0) {
968 dev_err(dev, "Self-test validate failed compare\n");
973 memset(page_address(dest), 0, PAGE_SIZE);
975 /* test for non-zero parity sum */
976 op = IOAT_OP_XOR_VAL;
979 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
980 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
982 if (dma_mapping_error(dev, dma_srcs[i])) {
987 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
988 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
989 &xor_val_result, DMA_PREP_INTERRUPT);
991 dev_err(dev, "Self-test 2nd zero prep failed\n");
997 init_completion(&cmp);
998 tx->callback = ioat_dma_test_callback;
999 tx->callback_param = &cmp;
1000 cookie = tx->tx_submit(tx);
1002 dev_err(dev, "Self-test 2nd zero setup failed\n");
1006 dma->device_issue_pending(dma_chan);
1008 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
1011 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
1012 dev_err(dev, "Self-test 2nd validate timed out\n");
1017 if (xor_val_result != SUM_CHECK_P_RESULT) {
1018 dev_err(dev, "Self-test validate failed compare\n");
1023 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1024 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
1026 goto free_resources;
1028 if (op == IOAT_OP_XOR) {
1030 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1032 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
1033 } else if (op == IOAT_OP_XOR_VAL) {
1035 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1039 dma->device_free_chan_resources(dma_chan);
1041 src_idx = IOAT_NUM_SRC_TEST;
1043 __free_page(xor_srcs[src_idx]);
1048 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma)
1052 rc = ioat_dma_self_test(ioat_dma);
1056 rc = ioat_xor_val_self_test(ioat_dma);
1061 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma)
1063 struct dma_device *dma;
1065 struct ioatdma_chan *ioat_chan;
1068 dma = &ioat_dma->dma_dev;
1071 * if we have descriptor write back error status, we mask the
1074 if (ioat_dma->cap & IOAT_CAP_DWBES) {
1075 list_for_each_entry(c, &dma->channels, device_node) {
1076 ioat_chan = to_ioat_chan(c);
1077 errmask = readl(ioat_chan->reg_base +
1078 IOAT_CHANERR_MASK_OFFSET);
1079 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR |
1080 IOAT_CHANERR_XOR_Q_ERR;
1081 writel(errmask, ioat_chan->reg_base +
1082 IOAT_CHANERR_MASK_OFFSET);
1087 static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca)
1089 struct pci_dev *pdev = ioat_dma->pdev;
1090 int dca_en = system_has_dca_enabled(pdev);
1091 struct dma_device *dma;
1093 struct ioatdma_chan *ioat_chan;
1097 dma = &ioat_dma->dma_dev;
1098 dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock;
1099 dma->device_issue_pending = ioat_issue_pending;
1100 dma->device_alloc_chan_resources = ioat_alloc_chan_resources;
1101 dma->device_free_chan_resources = ioat_free_chan_resources;
1103 dma_cap_set(DMA_INTERRUPT, dma->cap_mask);
1104 dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock;
1106 ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET);
1108 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev))
1110 ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS);
1112 /* dca is incompatible with raid operations */
1113 if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ)))
1114 ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ);
1116 if (ioat_dma->cap & IOAT_CAP_XOR) {
1119 dma_cap_set(DMA_XOR, dma->cap_mask);
1120 dma->device_prep_dma_xor = ioat_prep_xor;
1122 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1123 dma->device_prep_dma_xor_val = ioat_prep_xor_val;
1126 if (ioat_dma->cap & IOAT_CAP_PQ) {
1128 dma->device_prep_dma_pq = ioat_prep_pq;
1129 dma->device_prep_dma_pq_val = ioat_prep_pq_val;
1130 dma_cap_set(DMA_PQ, dma->cap_mask);
1131 dma_cap_set(DMA_PQ_VAL, dma->cap_mask);
1133 if (ioat_dma->cap & IOAT_CAP_RAID16SS)
1134 dma_set_maxpq(dma, 16, 0);
1136 dma_set_maxpq(dma, 8, 0);
1138 if (!(ioat_dma->cap & IOAT_CAP_XOR)) {
1139 dma->device_prep_dma_xor = ioat_prep_pqxor;
1140 dma->device_prep_dma_xor_val = ioat_prep_pqxor_val;
1141 dma_cap_set(DMA_XOR, dma->cap_mask);
1142 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1144 if (ioat_dma->cap & IOAT_CAP_RAID16SS)
1151 dma->device_tx_status = ioat_tx_status;
1153 /* starting with CB3.3 super extended descriptors are supported */
1154 if (ioat_dma->cap & IOAT_CAP_RAID16SS) {
1158 for (i = 0; i < MAX_SED_POOLS; i++) {
1159 snprintf(pool_name, 14, "ioat_hw%d_sed", i);
1161 /* allocate SED DMA pool */
1162 ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name,
1164 SED_SIZE * (i + 1), 64, 0);
1165 if (!ioat_dma->sed_hw_pool[i])
1171 if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ)))
1172 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1174 err = ioat_probe(ioat_dma);
1178 list_for_each_entry(c, &dma->channels, device_node) {
1179 ioat_chan = to_ioat_chan(c);
1180 writel(IOAT_DMA_DCA_ANY_CPU,
1181 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
1184 err = ioat_register(ioat_dma);
1188 ioat_kobject_add(ioat_dma, &ioat_ktype);
1191 ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base);
1193 /* disable relaxed ordering */
1194 err = pcie_capability_read_word(pdev, IOAT_DEVCTRL_OFFSET, &val16);
1196 return pcibios_err_to_errno(err);
1198 /* clear relaxed ordering enable */
1199 val16 &= ~IOAT_DEVCTRL_ROE;
1200 err = pcie_capability_write_word(pdev, IOAT_DEVCTRL_OFFSET, val16);
1202 return pcibios_err_to_errno(err);
1204 if (ioat_dma->cap & IOAT_CAP_DPS)
1205 writeb(ioat_pending_level + 1,
1206 ioat_dma->reg_base + IOAT_PREFETCH_LIMIT_OFFSET);
1211 static void ioat_shutdown(struct pci_dev *pdev)
1213 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev);
1214 struct ioatdma_chan *ioat_chan;
1220 for (i = 0; i < IOAT_MAX_CHANS; i++) {
1221 ioat_chan = ioat_dma->idx[i];
1225 spin_lock_bh(&ioat_chan->prep_lock);
1226 set_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
1227 spin_unlock_bh(&ioat_chan->prep_lock);
1229 * Synchronization rule for del_timer_sync():
1230 * - The caller must not hold locks which would prevent
1231 * completion of the timer's handler.
1232 * So prep_lock cannot be held before calling it.
1234 del_timer_sync(&ioat_chan->timer);
1236 /* this should quiesce then reset */
1237 ioat_reset_hw(ioat_chan);
1240 ioat_disable_interrupts(ioat_dma);
1243 static void ioat_resume(struct ioatdma_device *ioat_dma)
1245 struct ioatdma_chan *ioat_chan;
1249 for (i = 0; i < IOAT_MAX_CHANS; i++) {
1250 ioat_chan = ioat_dma->idx[i];
1254 spin_lock_bh(&ioat_chan->prep_lock);
1255 clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
1256 spin_unlock_bh(&ioat_chan->prep_lock);
1258 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
1259 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
1261 /* no need to reset as shutdown already did that */
1265 #define DRV_NAME "ioatdma"
1267 static pci_ers_result_t ioat_pcie_error_detected(struct pci_dev *pdev,
1268 pci_channel_state_t error)
1270 dev_dbg(&pdev->dev, "%s: PCIe AER error %d\n", DRV_NAME, error);
1272 /* quiesce and block I/O */
1273 ioat_shutdown(pdev);
1275 return PCI_ERS_RESULT_NEED_RESET;
1278 static pci_ers_result_t ioat_pcie_error_slot_reset(struct pci_dev *pdev)
1280 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
1282 dev_dbg(&pdev->dev, "%s post reset handling\n", DRV_NAME);
1284 if (pci_enable_device_mem(pdev) < 0) {
1286 "Failed to enable PCIe device after reset.\n");
1287 result = PCI_ERS_RESULT_DISCONNECT;
1289 pci_set_master(pdev);
1290 pci_restore_state(pdev);
1291 pci_save_state(pdev);
1292 pci_wake_from_d3(pdev, false);
1298 static void ioat_pcie_error_resume(struct pci_dev *pdev)
1300 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev);
1302 dev_dbg(&pdev->dev, "%s: AER handling resuming\n", DRV_NAME);
1304 /* initialize and bring everything back */
1305 ioat_resume(ioat_dma);
1308 static const struct pci_error_handlers ioat_err_handler = {
1309 .error_detected = ioat_pcie_error_detected,
1310 .slot_reset = ioat_pcie_error_slot_reset,
1311 .resume = ioat_pcie_error_resume,
1314 static struct pci_driver ioat_pci_driver = {
1316 .id_table = ioat_pci_tbl,
1317 .probe = ioat_pci_probe,
1318 .remove = ioat_remove,
1319 .shutdown = ioat_shutdown,
1320 .err_handler = &ioat_err_handler,
1323 static void release_ioatdma(struct dma_device *device)
1325 struct ioatdma_device *d = to_ioatdma_device(device);
1328 for (i = 0; i < IOAT_MAX_CHANS; i++)
1331 dma_pool_destroy(d->completion_pool);
1335 static struct ioatdma_device *
1336 alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase)
1338 struct ioatdma_device *d = kzalloc(sizeof(*d), GFP_KERNEL);
1343 d->reg_base = iobase;
1344 d->dma_dev.device_release = release_ioatdma;
1348 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1350 void __iomem * const *iomap;
1351 struct device *dev = &pdev->dev;
1352 struct ioatdma_device *device;
1355 err = pcim_enable_device(pdev);
1359 err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME);
1362 iomap = pcim_iomap_table(pdev);
1366 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1368 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1372 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1374 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1378 device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]);
1381 pci_set_master(pdev);
1382 pci_set_drvdata(pdev, device);
1384 device->version = readb(device->reg_base + IOAT_VER_OFFSET);
1385 if (device->version >= IOAT_VER_3_4)
1386 ioat_dca_enabled = 0;
1387 if (device->version >= IOAT_VER_3_0) {
1388 if (is_skx_ioat(pdev))
1389 device->version = IOAT_VER_3_2;
1390 err = ioat3_dma_probe(device, ioat_dca_enabled);
1392 if (device->version >= IOAT_VER_3_3)
1393 pci_enable_pcie_error_reporting(pdev);
1398 dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n");
1399 pci_disable_pcie_error_reporting(pdev);
1406 static void ioat_remove(struct pci_dev *pdev)
1408 struct ioatdma_device *device = pci_get_drvdata(pdev);
1413 ioat_shutdown(pdev);
1415 dev_err(&pdev->dev, "Removing dma and dca services\n");
1417 unregister_dca_provider(device->dca, &pdev->dev);
1418 free_dca_provider(device->dca);
1422 pci_disable_pcie_error_reporting(pdev);
1423 ioat_dma_remove(device);
1426 static int __init ioat_init_module(void)
1430 pr_info("%s: Intel(R) QuickData Technology Driver %s\n",
1431 DRV_NAME, IOAT_DMA_VERSION);
1433 ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent),
1434 0, SLAB_HWCACHE_ALIGN, NULL);
1438 ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0);
1439 if (!ioat_sed_cache)
1440 goto err_ioat_cache;
1442 err = pci_register_driver(&ioat_pci_driver);
1444 goto err_ioat3_cache;
1449 kmem_cache_destroy(ioat_sed_cache);
1452 kmem_cache_destroy(ioat_cache);
1456 module_init(ioat_init_module);
1458 static void __exit ioat_exit_module(void)
1460 pci_unregister_driver(&ioat_pci_driver);
1461 kmem_cache_destroy(ioat_cache);
1463 module_exit(ioat_exit_module);