2 * Intel I/OAT DMA Linux driver
3 * Copyright(c) 2004 - 2015 Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in
15 * the file called "COPYING".
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/slab.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/dmaengine.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/workqueue.h>
28 #include <linux/prefetch.h>
29 #include <linux/dca.h>
30 #include <linux/aer.h>
31 #include <linux/sizes.h>
33 #include "registers.h"
36 #include "../dmaengine.h"
38 MODULE_VERSION(IOAT_DMA_VERSION);
39 MODULE_LICENSE("Dual BSD/GPL");
40 MODULE_AUTHOR("Intel Corporation");
42 static struct pci_device_id ioat_pci_tbl[] = {
43 /* I/OAT v3 platforms */
44 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) },
45 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) },
46 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) },
47 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) },
48 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) },
49 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) },
50 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) },
51 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) },
53 /* I/OAT v3.2 platforms */
54 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) },
55 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) },
56 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) },
57 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) },
58 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) },
59 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) },
60 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) },
61 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) },
62 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) },
63 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) },
65 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) },
66 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) },
67 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) },
68 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) },
69 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) },
70 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) },
71 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) },
72 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) },
73 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) },
74 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) },
76 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) },
77 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) },
78 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) },
79 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) },
80 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) },
81 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) },
82 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) },
83 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) },
84 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) },
85 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) },
87 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) },
88 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) },
89 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) },
90 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) },
91 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) },
92 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) },
93 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) },
94 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) },
95 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) },
96 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) },
98 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX0) },
99 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX1) },
100 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX2) },
101 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX3) },
102 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX4) },
103 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX5) },
104 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX6) },
105 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX7) },
106 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX8) },
107 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDX9) },
109 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SKX) },
111 /* I/OAT v3.3 platforms */
112 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD0) },
113 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD1) },
114 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD2) },
115 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BWD3) },
117 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE0) },
118 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE1) },
119 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE2) },
120 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_BDXDE3) },
124 MODULE_DEVICE_TABLE(pci, ioat_pci_tbl);
126 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
127 static void ioat_remove(struct pci_dev *pdev);
129 ioat_init_channel(struct ioatdma_device *ioat_dma,
130 struct ioatdma_chan *ioat_chan, int idx);
131 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma);
132 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma);
133 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma);
135 static int ioat_dca_enabled = 1;
136 module_param(ioat_dca_enabled, int, 0644);
137 MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)");
138 int ioat_pending_level = 4;
139 module_param(ioat_pending_level, int, 0644);
140 MODULE_PARM_DESC(ioat_pending_level,
141 "high-water mark for pushing ioat descriptors (default: 4)");
142 static char ioat_interrupt_style[32] = "msix";
143 module_param_string(ioat_interrupt_style, ioat_interrupt_style,
144 sizeof(ioat_interrupt_style), 0644);
145 MODULE_PARM_DESC(ioat_interrupt_style,
146 "set ioat interrupt style: msix (default), msi, intx");
148 struct kmem_cache *ioat_cache;
149 struct kmem_cache *ioat_sed_cache;
151 static bool is_jf_ioat(struct pci_dev *pdev)
153 switch (pdev->device) {
154 case PCI_DEVICE_ID_INTEL_IOAT_JSF0:
155 case PCI_DEVICE_ID_INTEL_IOAT_JSF1:
156 case PCI_DEVICE_ID_INTEL_IOAT_JSF2:
157 case PCI_DEVICE_ID_INTEL_IOAT_JSF3:
158 case PCI_DEVICE_ID_INTEL_IOAT_JSF4:
159 case PCI_DEVICE_ID_INTEL_IOAT_JSF5:
160 case PCI_DEVICE_ID_INTEL_IOAT_JSF6:
161 case PCI_DEVICE_ID_INTEL_IOAT_JSF7:
162 case PCI_DEVICE_ID_INTEL_IOAT_JSF8:
163 case PCI_DEVICE_ID_INTEL_IOAT_JSF9:
170 static bool is_snb_ioat(struct pci_dev *pdev)
172 switch (pdev->device) {
173 case PCI_DEVICE_ID_INTEL_IOAT_SNB0:
174 case PCI_DEVICE_ID_INTEL_IOAT_SNB1:
175 case PCI_DEVICE_ID_INTEL_IOAT_SNB2:
176 case PCI_DEVICE_ID_INTEL_IOAT_SNB3:
177 case PCI_DEVICE_ID_INTEL_IOAT_SNB4:
178 case PCI_DEVICE_ID_INTEL_IOAT_SNB5:
179 case PCI_DEVICE_ID_INTEL_IOAT_SNB6:
180 case PCI_DEVICE_ID_INTEL_IOAT_SNB7:
181 case PCI_DEVICE_ID_INTEL_IOAT_SNB8:
182 case PCI_DEVICE_ID_INTEL_IOAT_SNB9:
189 static bool is_ivb_ioat(struct pci_dev *pdev)
191 switch (pdev->device) {
192 case PCI_DEVICE_ID_INTEL_IOAT_IVB0:
193 case PCI_DEVICE_ID_INTEL_IOAT_IVB1:
194 case PCI_DEVICE_ID_INTEL_IOAT_IVB2:
195 case PCI_DEVICE_ID_INTEL_IOAT_IVB3:
196 case PCI_DEVICE_ID_INTEL_IOAT_IVB4:
197 case PCI_DEVICE_ID_INTEL_IOAT_IVB5:
198 case PCI_DEVICE_ID_INTEL_IOAT_IVB6:
199 case PCI_DEVICE_ID_INTEL_IOAT_IVB7:
200 case PCI_DEVICE_ID_INTEL_IOAT_IVB8:
201 case PCI_DEVICE_ID_INTEL_IOAT_IVB9:
209 static bool is_hsw_ioat(struct pci_dev *pdev)
211 switch (pdev->device) {
212 case PCI_DEVICE_ID_INTEL_IOAT_HSW0:
213 case PCI_DEVICE_ID_INTEL_IOAT_HSW1:
214 case PCI_DEVICE_ID_INTEL_IOAT_HSW2:
215 case PCI_DEVICE_ID_INTEL_IOAT_HSW3:
216 case PCI_DEVICE_ID_INTEL_IOAT_HSW4:
217 case PCI_DEVICE_ID_INTEL_IOAT_HSW5:
218 case PCI_DEVICE_ID_INTEL_IOAT_HSW6:
219 case PCI_DEVICE_ID_INTEL_IOAT_HSW7:
220 case PCI_DEVICE_ID_INTEL_IOAT_HSW8:
221 case PCI_DEVICE_ID_INTEL_IOAT_HSW9:
229 static bool is_bdx_ioat(struct pci_dev *pdev)
231 switch (pdev->device) {
232 case PCI_DEVICE_ID_INTEL_IOAT_BDX0:
233 case PCI_DEVICE_ID_INTEL_IOAT_BDX1:
234 case PCI_DEVICE_ID_INTEL_IOAT_BDX2:
235 case PCI_DEVICE_ID_INTEL_IOAT_BDX3:
236 case PCI_DEVICE_ID_INTEL_IOAT_BDX4:
237 case PCI_DEVICE_ID_INTEL_IOAT_BDX5:
238 case PCI_DEVICE_ID_INTEL_IOAT_BDX6:
239 case PCI_DEVICE_ID_INTEL_IOAT_BDX7:
240 case PCI_DEVICE_ID_INTEL_IOAT_BDX8:
241 case PCI_DEVICE_ID_INTEL_IOAT_BDX9:
248 static inline bool is_skx_ioat(struct pci_dev *pdev)
250 return (pdev->device == PCI_DEVICE_ID_INTEL_IOAT_SKX) ? true : false;
253 static bool is_xeon_cb32(struct pci_dev *pdev)
255 return is_jf_ioat(pdev) || is_snb_ioat(pdev) || is_ivb_ioat(pdev) ||
256 is_hsw_ioat(pdev) || is_bdx_ioat(pdev) || is_skx_ioat(pdev);
259 bool is_bwd_ioat(struct pci_dev *pdev)
261 switch (pdev->device) {
262 case PCI_DEVICE_ID_INTEL_IOAT_BWD0:
263 case PCI_DEVICE_ID_INTEL_IOAT_BWD1:
264 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
265 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
266 /* even though not Atom, BDX-DE has same DMA silicon */
267 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
268 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
269 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
270 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
277 static bool is_bwd_noraid(struct pci_dev *pdev)
279 switch (pdev->device) {
280 case PCI_DEVICE_ID_INTEL_IOAT_BWD2:
281 case PCI_DEVICE_ID_INTEL_IOAT_BWD3:
282 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE0:
283 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE1:
284 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE2:
285 case PCI_DEVICE_ID_INTEL_IOAT_BDXDE3:
294 * Perform a IOAT transaction to verify the HW works.
296 #define IOAT_TEST_SIZE 2000
298 static void ioat_dma_test_callback(void *dma_async_param)
300 struct completion *cmp = dma_async_param;
306 * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works.
307 * @ioat_dma: dma device to be tested
309 static int ioat_dma_self_test(struct ioatdma_device *ioat_dma)
314 struct dma_device *dma = &ioat_dma->dma_dev;
315 struct device *dev = &ioat_dma->pdev->dev;
316 struct dma_chan *dma_chan;
317 struct dma_async_tx_descriptor *tx;
318 dma_addr_t dma_dest, dma_src;
321 struct completion cmp;
325 src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
328 dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL);
334 /* Fill in src buffer */
335 for (i = 0; i < IOAT_TEST_SIZE; i++)
338 /* Start copy, using first DMA channel */
339 dma_chan = container_of(dma->channels.next, struct dma_chan,
341 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
342 dev_err(dev, "selftest cannot allocate chan resource\n");
347 dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
348 if (dma_mapping_error(dev, dma_src)) {
349 dev_err(dev, "mapping src buffer failed\n");
352 dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
353 if (dma_mapping_error(dev, dma_dest)) {
354 dev_err(dev, "mapping dest buffer failed\n");
357 flags = DMA_PREP_INTERRUPT;
358 tx = ioat_dma->dma_dev.device_prep_dma_memcpy(dma_chan, dma_dest,
359 dma_src, IOAT_TEST_SIZE,
362 dev_err(dev, "Self-test prep failed, disabling\n");
368 init_completion(&cmp);
369 tx->callback = ioat_dma_test_callback;
370 tx->callback_param = &cmp;
371 cookie = tx->tx_submit(tx);
373 dev_err(dev, "Self-test setup failed, disabling\n");
377 dma->device_issue_pending(dma_chan);
379 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
382 dma->device_tx_status(dma_chan, cookie, NULL)
384 dev_err(dev, "Self-test copy timed out, disabling\n");
388 if (memcmp(src, dest, IOAT_TEST_SIZE)) {
389 dev_err(dev, "Self-test copy failed compare, disabling\n");
395 dma_unmap_single(dev, dma_dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE);
397 dma_unmap_single(dev, dma_src, IOAT_TEST_SIZE, DMA_TO_DEVICE);
399 dma->device_free_chan_resources(dma_chan);
407 * ioat_dma_setup_interrupts - setup interrupt handler
408 * @ioat_dma: ioat dma device
410 int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma)
412 struct ioatdma_chan *ioat_chan;
413 struct pci_dev *pdev = ioat_dma->pdev;
414 struct device *dev = &pdev->dev;
415 struct msix_entry *msix;
420 if (!strcmp(ioat_interrupt_style, "msix"))
422 if (!strcmp(ioat_interrupt_style, "msi"))
424 if (!strcmp(ioat_interrupt_style, "intx"))
426 dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style);
430 /* The number of MSI-X vectors should equal the number of channels */
431 msixcnt = ioat_dma->dma_dev.chancnt;
432 for (i = 0; i < msixcnt; i++)
433 ioat_dma->msix_entries[i].entry = i;
435 err = pci_enable_msix_exact(pdev, ioat_dma->msix_entries, msixcnt);
439 for (i = 0; i < msixcnt; i++) {
440 msix = &ioat_dma->msix_entries[i];
441 ioat_chan = ioat_chan_by_index(ioat_dma, i);
442 err = devm_request_irq(dev, msix->vector,
443 ioat_dma_do_interrupt_msix, 0,
444 "ioat-msix", ioat_chan);
446 for (j = 0; j < i; j++) {
447 msix = &ioat_dma->msix_entries[j];
448 ioat_chan = ioat_chan_by_index(ioat_dma, j);
449 devm_free_irq(dev, msix->vector, ioat_chan);
454 intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL;
455 ioat_dma->irq_mode = IOAT_MSIX;
459 err = pci_enable_msi(pdev);
463 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0,
464 "ioat-msi", ioat_dma);
466 pci_disable_msi(pdev);
469 ioat_dma->irq_mode = IOAT_MSI;
473 err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt,
474 IRQF_SHARED, "ioat-intx", ioat_dma);
478 ioat_dma->irq_mode = IOAT_INTX;
480 if (is_bwd_ioat(pdev))
481 ioat_intr_quirk(ioat_dma);
482 intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN;
483 writeb(intrctrl, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
487 /* Disable all interrupt generation */
488 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
489 ioat_dma->irq_mode = IOAT_NOIRQ;
490 dev_err(dev, "no usable interrupts\n");
494 static void ioat_disable_interrupts(struct ioatdma_device *ioat_dma)
496 /* Disable all interrupt generation */
497 writeb(0, ioat_dma->reg_base + IOAT_INTRCTRL_OFFSET);
500 static int ioat_probe(struct ioatdma_device *ioat_dma)
503 struct dma_device *dma = &ioat_dma->dma_dev;
504 struct pci_dev *pdev = ioat_dma->pdev;
505 struct device *dev = &pdev->dev;
507 ioat_dma->completion_pool = dma_pool_create("completion_pool", dev,
512 if (!ioat_dma->completion_pool) {
517 ioat_enumerate_channels(ioat_dma);
519 dma_cap_set(DMA_MEMCPY, dma->cap_mask);
520 dma->dev = &pdev->dev;
523 dev_err(dev, "channel enumeration error\n");
524 goto err_setup_interrupts;
527 err = ioat_dma_setup_interrupts(ioat_dma);
529 goto err_setup_interrupts;
531 err = ioat3_dma_self_test(ioat_dma);
538 ioat_disable_interrupts(ioat_dma);
539 err_setup_interrupts:
540 dma_pool_destroy(ioat_dma->completion_pool);
545 static int ioat_register(struct ioatdma_device *ioat_dma)
547 int err = dma_async_device_register(&ioat_dma->dma_dev);
550 ioat_disable_interrupts(ioat_dma);
551 dma_pool_destroy(ioat_dma->completion_pool);
557 static void ioat_dma_remove(struct ioatdma_device *ioat_dma)
559 struct dma_device *dma = &ioat_dma->dma_dev;
561 ioat_disable_interrupts(ioat_dma);
563 ioat_kobject_del(ioat_dma);
565 dma_async_device_unregister(dma);
567 dma_pool_destroy(ioat_dma->completion_pool);
569 INIT_LIST_HEAD(&dma->channels);
573 * ioat_enumerate_channels - find and initialize the device's channels
574 * @ioat_dma: the ioat dma device to be enumerated
576 static void ioat_enumerate_channels(struct ioatdma_device *ioat_dma)
578 struct ioatdma_chan *ioat_chan;
579 struct device *dev = &ioat_dma->pdev->dev;
580 struct dma_device *dma = &ioat_dma->dma_dev;
584 INIT_LIST_HEAD(&dma->channels);
585 dma->chancnt = readb(ioat_dma->reg_base + IOAT_CHANCNT_OFFSET);
586 dma->chancnt &= 0x1f; /* bits [4:0] valid */
587 if (dma->chancnt > ARRAY_SIZE(ioat_dma->idx)) {
588 dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n",
589 dma->chancnt, ARRAY_SIZE(ioat_dma->idx));
590 dma->chancnt = ARRAY_SIZE(ioat_dma->idx);
592 xfercap_log = readb(ioat_dma->reg_base + IOAT_XFERCAP_OFFSET);
593 xfercap_log &= 0x1f; /* bits [4:0] valid */
594 if (xfercap_log == 0)
596 dev_dbg(dev, "%s: xfercap = %d\n", __func__, 1 << xfercap_log);
598 for (i = 0; i < dma->chancnt; i++) {
599 ioat_chan = devm_kzalloc(dev, sizeof(*ioat_chan), GFP_KERNEL);
603 ioat_init_channel(ioat_dma, ioat_chan, i);
604 ioat_chan->xfercap_log = xfercap_log;
605 spin_lock_init(&ioat_chan->prep_lock);
606 if (ioat_reset_hw(ioat_chan)) {
615 * ioat_free_chan_resources - release all the descriptors
616 * @chan: the channel to be cleaned
618 static void ioat_free_chan_resources(struct dma_chan *c)
620 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
621 struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma;
622 struct ioat_ring_ent *desc;
623 const int total_descs = 1 << ioat_chan->alloc_order;
627 /* Before freeing channel resources first check
628 * if they have been previously allocated for this channel.
630 if (!ioat_chan->ring)
633 ioat_stop(ioat_chan);
634 ioat_reset_hw(ioat_chan);
636 spin_lock_bh(&ioat_chan->cleanup_lock);
637 spin_lock_bh(&ioat_chan->prep_lock);
638 descs = ioat_ring_space(ioat_chan);
639 dev_dbg(to_dev(ioat_chan), "freeing %d idle descriptors\n", descs);
640 for (i = 0; i < descs; i++) {
641 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head + i);
642 ioat_free_ring_ent(desc, c);
645 if (descs < total_descs)
646 dev_err(to_dev(ioat_chan), "Freeing %d in use descriptors!\n",
647 total_descs - descs);
649 for (i = 0; i < total_descs - descs; i++) {
650 desc = ioat_get_ring_ent(ioat_chan, ioat_chan->tail + i);
651 dump_desc_dbg(ioat_chan, desc);
652 ioat_free_ring_ent(desc, c);
655 for (i = 0; i < ioat_chan->desc_chunks; i++) {
656 dma_free_coherent(to_dev(ioat_chan), SZ_2M,
657 ioat_chan->descs[i].virt,
658 ioat_chan->descs[i].hw);
659 ioat_chan->descs[i].virt = NULL;
660 ioat_chan->descs[i].hw = 0;
662 ioat_chan->desc_chunks = 0;
664 kfree(ioat_chan->ring);
665 ioat_chan->ring = NULL;
666 ioat_chan->alloc_order = 0;
667 dma_pool_free(ioat_dma->completion_pool, ioat_chan->completion,
668 ioat_chan->completion_dma);
669 spin_unlock_bh(&ioat_chan->prep_lock);
670 spin_unlock_bh(&ioat_chan->cleanup_lock);
672 ioat_chan->last_completion = 0;
673 ioat_chan->completion_dma = 0;
674 ioat_chan->dmacount = 0;
677 /* ioat_alloc_chan_resources - allocate/initialize ioat descriptor ring
678 * @chan: channel to be initialized
680 static int ioat_alloc_chan_resources(struct dma_chan *c)
682 struct ioatdma_chan *ioat_chan = to_ioat_chan(c);
683 struct ioat_ring_ent **ring;
689 /* have we already been set up? */
691 return 1 << ioat_chan->alloc_order;
693 /* Setup register to interrupt and write completion status on error */
694 writew(IOAT_CHANCTRL_RUN, ioat_chan->reg_base + IOAT_CHANCTRL_OFFSET);
696 /* allocate a completion writeback area */
697 /* doing 2 32bit writes to mmio since 1 64b write doesn't work */
698 ioat_chan->completion =
699 dma_pool_zalloc(ioat_chan->ioat_dma->completion_pool,
700 GFP_NOWAIT, &ioat_chan->completion_dma);
701 if (!ioat_chan->completion)
704 writel(((u64)ioat_chan->completion_dma) & 0x00000000FFFFFFFF,
705 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_LOW);
706 writel(((u64)ioat_chan->completion_dma) >> 32,
707 ioat_chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH);
709 order = IOAT_MAX_ORDER;
710 ring = ioat_alloc_ring(c, order, GFP_NOWAIT);
714 spin_lock_bh(&ioat_chan->cleanup_lock);
715 spin_lock_bh(&ioat_chan->prep_lock);
716 ioat_chan->ring = ring;
718 ioat_chan->issued = 0;
720 ioat_chan->alloc_order = order;
721 set_bit(IOAT_RUN, &ioat_chan->state);
722 spin_unlock_bh(&ioat_chan->prep_lock);
723 spin_unlock_bh(&ioat_chan->cleanup_lock);
725 ioat_start_null_desc(ioat_chan);
727 /* check that we got off the ground */
730 status = ioat_chansts(ioat_chan);
731 } while (i++ < 20 && !is_ioat_active(status) && !is_ioat_idle(status));
733 if (is_ioat_active(status) || is_ioat_idle(status))
734 return 1 << ioat_chan->alloc_order;
736 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
738 dev_WARN(to_dev(ioat_chan),
739 "failed to start channel chanerr: %#x\n", chanerr);
740 ioat_free_chan_resources(c);
744 /* common channel initialization */
746 ioat_init_channel(struct ioatdma_device *ioat_dma,
747 struct ioatdma_chan *ioat_chan, int idx)
749 struct dma_device *dma = &ioat_dma->dma_dev;
750 struct dma_chan *c = &ioat_chan->dma_chan;
751 unsigned long data = (unsigned long) c;
753 ioat_chan->ioat_dma = ioat_dma;
754 ioat_chan->reg_base = ioat_dma->reg_base + (0x80 * (idx + 1));
755 spin_lock_init(&ioat_chan->cleanup_lock);
756 ioat_chan->dma_chan.device = dma;
757 dma_cookie_init(&ioat_chan->dma_chan);
758 list_add_tail(&ioat_chan->dma_chan.device_node, &dma->channels);
759 ioat_dma->idx[idx] = ioat_chan;
760 init_timer(&ioat_chan->timer);
761 ioat_chan->timer.function = ioat_timer_event;
762 ioat_chan->timer.data = data;
763 tasklet_init(&ioat_chan->cleanup_task, ioat_cleanup_event, data);
766 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
767 static int ioat_xor_val_self_test(struct ioatdma_device *ioat_dma)
771 struct page *xor_srcs[IOAT_NUM_SRC_TEST];
772 struct page *xor_val_srcs[IOAT_NUM_SRC_TEST + 1];
773 dma_addr_t dma_srcs[IOAT_NUM_SRC_TEST + 1];
775 struct dma_async_tx_descriptor *tx;
776 struct dma_chan *dma_chan;
782 struct completion cmp;
784 struct device *dev = &ioat_dma->pdev->dev;
785 struct dma_device *dma = &ioat_dma->dma_dev;
788 dev_dbg(dev, "%s\n", __func__);
790 if (!dma_has_cap(DMA_XOR, dma->cap_mask))
793 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
794 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
795 if (!xor_srcs[src_idx]) {
797 __free_page(xor_srcs[src_idx]);
802 dest = alloc_page(GFP_KERNEL);
805 __free_page(xor_srcs[src_idx]);
809 /* Fill in src buffers */
810 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++) {
811 u8 *ptr = page_address(xor_srcs[src_idx]);
813 for (i = 0; i < PAGE_SIZE; i++)
814 ptr[i] = (1 << src_idx);
817 for (src_idx = 0; src_idx < IOAT_NUM_SRC_TEST; src_idx++)
818 cmp_byte ^= (u8) (1 << src_idx);
820 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
821 (cmp_byte << 8) | cmp_byte;
823 memset(page_address(dest), 0, PAGE_SIZE);
825 dma_chan = container_of(dma->channels.next, struct dma_chan,
827 if (dma->device_alloc_chan_resources(dma_chan) < 1) {
835 dest_dma = dma_map_page(dev, dest, 0, PAGE_SIZE, DMA_FROM_DEVICE);
836 if (dma_mapping_error(dev, dest_dma))
839 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
840 dma_srcs[i] = DMA_ERROR_CODE;
841 for (i = 0; i < IOAT_NUM_SRC_TEST; i++) {
842 dma_srcs[i] = dma_map_page(dev, xor_srcs[i], 0, PAGE_SIZE,
844 if (dma_mapping_error(dev, dma_srcs[i]))
847 tx = dma->device_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
848 IOAT_NUM_SRC_TEST, PAGE_SIZE,
852 dev_err(dev, "Self-test xor prep failed\n");
858 init_completion(&cmp);
859 tx->callback = ioat_dma_test_callback;
860 tx->callback_param = &cmp;
861 cookie = tx->tx_submit(tx);
863 dev_err(dev, "Self-test xor setup failed\n");
867 dma->device_issue_pending(dma_chan);
869 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
872 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
873 dev_err(dev, "Self-test xor timed out\n");
878 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
879 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
881 dma_sync_single_for_cpu(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
882 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
883 u32 *ptr = page_address(dest);
885 if (ptr[i] != cmp_word) {
886 dev_err(dev, "Self-test xor failed compare\n");
891 dma_sync_single_for_device(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
893 dma_unmap_page(dev, dest_dma, PAGE_SIZE, DMA_FROM_DEVICE);
895 /* skip validate if the capability is not present */
896 if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask))
899 op = IOAT_OP_XOR_VAL;
901 /* validate the sources with the destintation page */
902 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
903 xor_val_srcs[i] = xor_srcs[i];
904 xor_val_srcs[i] = dest;
908 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
909 dma_srcs[i] = DMA_ERROR_CODE;
910 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
911 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
913 if (dma_mapping_error(dev, dma_srcs[i]))
916 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
917 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
918 &xor_val_result, DMA_PREP_INTERRUPT);
920 dev_err(dev, "Self-test zero prep failed\n");
926 init_completion(&cmp);
927 tx->callback = ioat_dma_test_callback;
928 tx->callback_param = &cmp;
929 cookie = tx->tx_submit(tx);
931 dev_err(dev, "Self-test zero setup failed\n");
935 dma->device_issue_pending(dma_chan);
937 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
940 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
941 dev_err(dev, "Self-test validate timed out\n");
946 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
947 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
949 if (xor_val_result != 0) {
950 dev_err(dev, "Self-test validate failed compare\n");
955 memset(page_address(dest), 0, PAGE_SIZE);
957 /* test for non-zero parity sum */
958 op = IOAT_OP_XOR_VAL;
961 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
962 dma_srcs[i] = DMA_ERROR_CODE;
963 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++) {
964 dma_srcs[i] = dma_map_page(dev, xor_val_srcs[i], 0, PAGE_SIZE,
966 if (dma_mapping_error(dev, dma_srcs[i]))
969 tx = dma->device_prep_dma_xor_val(dma_chan, dma_srcs,
970 IOAT_NUM_SRC_TEST + 1, PAGE_SIZE,
971 &xor_val_result, DMA_PREP_INTERRUPT);
973 dev_err(dev, "Self-test 2nd zero prep failed\n");
979 init_completion(&cmp);
980 tx->callback = ioat_dma_test_callback;
981 tx->callback_param = &cmp;
982 cookie = tx->tx_submit(tx);
984 dev_err(dev, "Self-test 2nd zero setup failed\n");
988 dma->device_issue_pending(dma_chan);
990 tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000));
993 dma->device_tx_status(dma_chan, cookie, NULL) != DMA_COMPLETE) {
994 dev_err(dev, "Self-test 2nd validate timed out\n");
999 if (xor_val_result != SUM_CHECK_P_RESULT) {
1000 dev_err(dev, "Self-test validate failed compare\n");
1005 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1006 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE, DMA_TO_DEVICE);
1008 goto free_resources;
1010 if (op == IOAT_OP_XOR) {
1011 if (dest_dma != DMA_ERROR_CODE)
1012 dma_unmap_page(dev, dest_dma, PAGE_SIZE,
1014 for (i = 0; i < IOAT_NUM_SRC_TEST; i++)
1015 if (dma_srcs[i] != DMA_ERROR_CODE)
1016 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1018 } else if (op == IOAT_OP_XOR_VAL) {
1019 for (i = 0; i < IOAT_NUM_SRC_TEST + 1; i++)
1020 if (dma_srcs[i] != DMA_ERROR_CODE)
1021 dma_unmap_page(dev, dma_srcs[i], PAGE_SIZE,
1025 dma->device_free_chan_resources(dma_chan);
1027 src_idx = IOAT_NUM_SRC_TEST;
1029 __free_page(xor_srcs[src_idx]);
1034 static int ioat3_dma_self_test(struct ioatdma_device *ioat_dma)
1038 rc = ioat_dma_self_test(ioat_dma);
1042 rc = ioat_xor_val_self_test(ioat_dma);
1047 static void ioat_intr_quirk(struct ioatdma_device *ioat_dma)
1049 struct dma_device *dma;
1051 struct ioatdma_chan *ioat_chan;
1054 dma = &ioat_dma->dma_dev;
1057 * if we have descriptor write back error status, we mask the
1060 if (ioat_dma->cap & IOAT_CAP_DWBES) {
1061 list_for_each_entry(c, &dma->channels, device_node) {
1062 ioat_chan = to_ioat_chan(c);
1063 errmask = readl(ioat_chan->reg_base +
1064 IOAT_CHANERR_MASK_OFFSET);
1065 errmask |= IOAT_CHANERR_XOR_P_OR_CRC_ERR |
1066 IOAT_CHANERR_XOR_Q_ERR;
1067 writel(errmask, ioat_chan->reg_base +
1068 IOAT_CHANERR_MASK_OFFSET);
1073 static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca)
1075 struct pci_dev *pdev = ioat_dma->pdev;
1076 int dca_en = system_has_dca_enabled(pdev);
1077 struct dma_device *dma;
1079 struct ioatdma_chan *ioat_chan;
1080 bool is_raid_device = false;
1084 dma = &ioat_dma->dma_dev;
1085 dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock;
1086 dma->device_issue_pending = ioat_issue_pending;
1087 dma->device_alloc_chan_resources = ioat_alloc_chan_resources;
1088 dma->device_free_chan_resources = ioat_free_chan_resources;
1090 dma_cap_set(DMA_INTERRUPT, dma->cap_mask);
1091 dma->device_prep_dma_interrupt = ioat_prep_interrupt_lock;
1093 ioat_dma->cap = readl(ioat_dma->reg_base + IOAT_DMA_CAP_OFFSET);
1095 if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev))
1097 ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS);
1099 /* dca is incompatible with raid operations */
1100 if (dca_en && (ioat_dma->cap & (IOAT_CAP_XOR|IOAT_CAP_PQ)))
1101 ioat_dma->cap &= ~(IOAT_CAP_XOR|IOAT_CAP_PQ);
1103 if (ioat_dma->cap & IOAT_CAP_XOR) {
1104 is_raid_device = true;
1107 dma_cap_set(DMA_XOR, dma->cap_mask);
1108 dma->device_prep_dma_xor = ioat_prep_xor;
1110 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1111 dma->device_prep_dma_xor_val = ioat_prep_xor_val;
1114 if (ioat_dma->cap & IOAT_CAP_PQ) {
1115 is_raid_device = true;
1117 dma->device_prep_dma_pq = ioat_prep_pq;
1118 dma->device_prep_dma_pq_val = ioat_prep_pq_val;
1119 dma_cap_set(DMA_PQ, dma->cap_mask);
1120 dma_cap_set(DMA_PQ_VAL, dma->cap_mask);
1122 if (ioat_dma->cap & IOAT_CAP_RAID16SS)
1123 dma_set_maxpq(dma, 16, 0);
1125 dma_set_maxpq(dma, 8, 0);
1127 if (!(ioat_dma->cap & IOAT_CAP_XOR)) {
1128 dma->device_prep_dma_xor = ioat_prep_pqxor;
1129 dma->device_prep_dma_xor_val = ioat_prep_pqxor_val;
1130 dma_cap_set(DMA_XOR, dma->cap_mask);
1131 dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
1133 if (ioat_dma->cap & IOAT_CAP_RAID16SS)
1140 dma->device_tx_status = ioat_tx_status;
1142 /* starting with CB3.3 super extended descriptors are supported */
1143 if (ioat_dma->cap & IOAT_CAP_RAID16SS) {
1147 for (i = 0; i < MAX_SED_POOLS; i++) {
1148 snprintf(pool_name, 14, "ioat_hw%d_sed", i);
1150 /* allocate SED DMA pool */
1151 ioat_dma->sed_hw_pool[i] = dmam_pool_create(pool_name,
1153 SED_SIZE * (i + 1), 64, 0);
1154 if (!ioat_dma->sed_hw_pool[i])
1160 if (!(ioat_dma->cap & (IOAT_CAP_XOR | IOAT_CAP_PQ)))
1161 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1163 err = ioat_probe(ioat_dma);
1167 list_for_each_entry(c, &dma->channels, device_node) {
1168 ioat_chan = to_ioat_chan(c);
1169 writel(IOAT_DMA_DCA_ANY_CPU,
1170 ioat_chan->reg_base + IOAT_DCACTRL_OFFSET);
1173 err = ioat_register(ioat_dma);
1177 ioat_kobject_add(ioat_dma, &ioat_ktype);
1180 ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base);
1182 /* disable relaxed ordering */
1183 err = pcie_capability_read_word(pdev, IOAT_DEVCTRL_OFFSET, &val16);
1187 /* clear relaxed ordering enable */
1188 val16 &= ~IOAT_DEVCTRL_ROE;
1189 err = pcie_capability_write_word(pdev, IOAT_DEVCTRL_OFFSET, val16);
1196 static void ioat_shutdown(struct pci_dev *pdev)
1198 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev);
1199 struct ioatdma_chan *ioat_chan;
1205 for (i = 0; i < IOAT_MAX_CHANS; i++) {
1206 ioat_chan = ioat_dma->idx[i];
1210 spin_lock_bh(&ioat_chan->prep_lock);
1211 set_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
1212 spin_unlock_bh(&ioat_chan->prep_lock);
1214 * Synchronization rule for del_timer_sync():
1215 * - The caller must not hold locks which would prevent
1216 * completion of the timer's handler.
1217 * So prep_lock cannot be held before calling it.
1219 del_timer_sync(&ioat_chan->timer);
1221 /* this should quiesce then reset */
1222 ioat_reset_hw(ioat_chan);
1225 ioat_disable_interrupts(ioat_dma);
1228 static void ioat_resume(struct ioatdma_device *ioat_dma)
1230 struct ioatdma_chan *ioat_chan;
1234 for (i = 0; i < IOAT_MAX_CHANS; i++) {
1235 ioat_chan = ioat_dma->idx[i];
1239 spin_lock_bh(&ioat_chan->prep_lock);
1240 clear_bit(IOAT_CHAN_DOWN, &ioat_chan->state);
1241 spin_unlock_bh(&ioat_chan->prep_lock);
1243 chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
1244 writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
1246 /* no need to reset as shutdown already did that */
1250 #define DRV_NAME "ioatdma"
1252 static pci_ers_result_t ioat_pcie_error_detected(struct pci_dev *pdev,
1253 enum pci_channel_state error)
1255 dev_dbg(&pdev->dev, "%s: PCIe AER error %d\n", DRV_NAME, error);
1257 /* quiesce and block I/O */
1258 ioat_shutdown(pdev);
1260 return PCI_ERS_RESULT_NEED_RESET;
1263 static pci_ers_result_t ioat_pcie_error_slot_reset(struct pci_dev *pdev)
1265 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
1268 dev_dbg(&pdev->dev, "%s post reset handling\n", DRV_NAME);
1270 if (pci_enable_device_mem(pdev) < 0) {
1272 "Failed to enable PCIe device after reset.\n");
1273 result = PCI_ERS_RESULT_DISCONNECT;
1275 pci_set_master(pdev);
1276 pci_restore_state(pdev);
1277 pci_save_state(pdev);
1278 pci_wake_from_d3(pdev, false);
1281 err = pci_cleanup_aer_uncorrect_error_status(pdev);
1284 "AER uncorrect error status clear failed: %#x\n", err);
1290 static void ioat_pcie_error_resume(struct pci_dev *pdev)
1292 struct ioatdma_device *ioat_dma = pci_get_drvdata(pdev);
1294 dev_dbg(&pdev->dev, "%s: AER handling resuming\n", DRV_NAME);
1296 /* initialize and bring everything back */
1297 ioat_resume(ioat_dma);
1300 static const struct pci_error_handlers ioat_err_handler = {
1301 .error_detected = ioat_pcie_error_detected,
1302 .slot_reset = ioat_pcie_error_slot_reset,
1303 .resume = ioat_pcie_error_resume,
1306 static struct pci_driver ioat_pci_driver = {
1308 .id_table = ioat_pci_tbl,
1309 .probe = ioat_pci_probe,
1310 .remove = ioat_remove,
1311 .shutdown = ioat_shutdown,
1312 .err_handler = &ioat_err_handler,
1315 static struct ioatdma_device *
1316 alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase)
1318 struct device *dev = &pdev->dev;
1319 struct ioatdma_device *d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
1324 d->reg_base = iobase;
1328 static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1330 void __iomem * const *iomap;
1331 struct device *dev = &pdev->dev;
1332 struct ioatdma_device *device;
1335 err = pcim_enable_device(pdev);
1339 err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME);
1342 iomap = pcim_iomap_table(pdev);
1346 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1348 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1352 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1354 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1358 device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]);
1361 pci_set_master(pdev);
1362 pci_set_drvdata(pdev, device);
1364 device->version = readb(device->reg_base + IOAT_VER_OFFSET);
1365 if (device->version >= IOAT_VER_3_0) {
1366 if (is_skx_ioat(pdev))
1367 device->version = IOAT_VER_3_2;
1368 err = ioat3_dma_probe(device, ioat_dca_enabled);
1370 if (device->version >= IOAT_VER_3_3)
1371 pci_enable_pcie_error_reporting(pdev);
1376 dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n");
1377 pci_disable_pcie_error_reporting(pdev);
1384 static void ioat_remove(struct pci_dev *pdev)
1386 struct ioatdma_device *device = pci_get_drvdata(pdev);
1391 dev_err(&pdev->dev, "Removing dma and dca services\n");
1393 unregister_dca_provider(device->dca, &pdev->dev);
1394 free_dca_provider(device->dca);
1398 pci_disable_pcie_error_reporting(pdev);
1399 ioat_dma_remove(device);
1402 static int __init ioat_init_module(void)
1406 pr_info("%s: Intel(R) QuickData Technology Driver %s\n",
1407 DRV_NAME, IOAT_DMA_VERSION);
1409 ioat_cache = kmem_cache_create("ioat", sizeof(struct ioat_ring_ent),
1410 0, SLAB_HWCACHE_ALIGN, NULL);
1414 ioat_sed_cache = KMEM_CACHE(ioat_sed_ent, 0);
1415 if (!ioat_sed_cache)
1416 goto err_ioat_cache;
1418 err = pci_register_driver(&ioat_pci_driver);
1420 goto err_ioat3_cache;
1425 kmem_cache_destroy(ioat_sed_cache);
1428 kmem_cache_destroy(ioat_cache);
1432 module_init(ioat_init_module);
1434 static void __exit ioat_exit_module(void)
1436 pci_unregister_driver(&ioat_pci_driver);
1437 kmem_cache_destroy(ioat_cache);
1439 module_exit(ioat_exit_module);