1 // SPDX-License-Identifier: GPL-2.0+
3 // drivers/dma/imx-sdma.c
5 // This file contains a driver for the Freescale Smart DMA engine
7 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
9 // Based on code from Freescale:
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
13 #include <linux/init.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/types.h>
17 #include <linux/bitops.h>
19 #include <linux/interrupt.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/sched.h>
23 #include <linux/semaphore.h>
24 #include <linux/spinlock.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firmware.h>
28 #include <linux/slab.h>
29 #include <linux/platform_device.h>
30 #include <linux/dmaengine.h>
32 #include <linux/of_address.h>
33 #include <linux/of_device.h>
34 #include <linux/of_dma.h>
35 #include <linux/workqueue.h>
38 #include <linux/platform_data/dma-imx-sdma.h>
39 #include <linux/platform_data/dma-imx.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
44 #include "dmaengine.h"
48 #define SDMA_H_C0PTR 0x000
49 #define SDMA_H_INTR 0x004
50 #define SDMA_H_STATSTOP 0x008
51 #define SDMA_H_START 0x00c
52 #define SDMA_H_EVTOVR 0x010
53 #define SDMA_H_DSPOVR 0x014
54 #define SDMA_H_HOSTOVR 0x018
55 #define SDMA_H_EVTPEND 0x01c
56 #define SDMA_H_DSPENBL 0x020
57 #define SDMA_H_RESET 0x024
58 #define SDMA_H_EVTERR 0x028
59 #define SDMA_H_INTRMSK 0x02c
60 #define SDMA_H_PSW 0x030
61 #define SDMA_H_EVTERRDBG 0x034
62 #define SDMA_H_CONFIG 0x038
63 #define SDMA_ONCE_ENB 0x040
64 #define SDMA_ONCE_DATA 0x044
65 #define SDMA_ONCE_INSTR 0x048
66 #define SDMA_ONCE_STAT 0x04c
67 #define SDMA_ONCE_CMD 0x050
68 #define SDMA_EVT_MIRROR 0x054
69 #define SDMA_ILLINSTADDR 0x058
70 #define SDMA_CHN0ADDR 0x05c
71 #define SDMA_ONCE_RTB 0x060
72 #define SDMA_XTRIG_CONF1 0x070
73 #define SDMA_XTRIG_CONF2 0x074
74 #define SDMA_CHNENBL0_IMX35 0x200
75 #define SDMA_CHNENBL0_IMX31 0x080
76 #define SDMA_CHNPRI_0 0x100
79 * Buffer descriptor status values.
90 * Data Node descriptor status values.
92 #define DND_END_OF_FRAME 0x80
93 #define DND_END_OF_XFER 0x40
95 #define DND_UNUSED 0x01
98 * IPCV2 descriptor status values.
100 #define BD_IPCV2_END_OF_FRAME 0x40
102 #define IPCV2_MAX_NODES 50
104 * Error bit set in the CCB status field by the SDMA,
105 * in setbd routine, in case of a transfer error
107 #define DATA_ERROR 0x10000000
110 * Buffer descriptor commands.
115 #define C0_SETCTX 0x07
116 #define C0_GETCTX 0x03
117 #define C0_SETDM 0x01
118 #define C0_SETPM 0x04
119 #define C0_GETDM 0x02
120 #define C0_GETPM 0x08
122 * Change endianness indicator in the BD command field
124 #define CHANGE_ENDIANNESS 0x80
127 * p_2_p watermark_level description
128 * Bits Name Description
129 * 0-7 Lower WML Lower watermark level
130 * 8 PS 1: Pad Swallowing
131 * 0: No Pad Swallowing
134 * 10 SPDIF If this bit is set both source
135 * and destination are on SPBA
136 * 11 Source Bit(SP) 1: Source on SPBA
138 * 12 Destination Bit(DP) 1: Destination on SPBA
139 * 0: Destination on AIPS
140 * 13-15 --------- MUST BE 0
141 * 16-23 Higher WML HWML
142 * 24-27 N Total number of samples after
143 * which Pad adding/Swallowing
144 * must be done. It must be odd.
145 * 28 Lower WML Event(LWE) SDMA events reg to check for
147 * 0: LWE in EVENTS register
148 * 1: LWE in EVENTS2 register
149 * 29 Higher WML Event(HWE) SDMA events reg to check for
151 * 0: HWE in EVENTS register
152 * 1: HWE in EVENTS2 register
153 * 30 --------- MUST BE 0
154 * 31 CONT 1: Amount of samples to be
155 * transferred is unknown and
156 * script will keep on
157 * transferring samples as long as
158 * both events are detected and
159 * script must be manually stopped
161 * 0: The amount of samples to be
162 * transferred is equal to the
163 * count field of mode word
165 #define SDMA_WATERMARK_LEVEL_LWML 0xFF
166 #define SDMA_WATERMARK_LEVEL_PS BIT(8)
167 #define SDMA_WATERMARK_LEVEL_PA BIT(9)
168 #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10)
169 #define SDMA_WATERMARK_LEVEL_SP BIT(11)
170 #define SDMA_WATERMARK_LEVEL_DP BIT(12)
171 #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16)
172 #define SDMA_WATERMARK_LEVEL_LWE BIT(28)
173 #define SDMA_WATERMARK_LEVEL_HWE BIT(29)
174 #define SDMA_WATERMARK_LEVEL_CONT BIT(31)
176 #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
177 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
178 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
180 #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \
181 BIT(DMA_MEM_TO_DEV) | \
185 * Mode/Count of data node descriptors - IPCv2
187 struct sdma_mode_count {
188 #define SDMA_BD_MAX_CNT 0xffff
189 u32 count : 16; /* size of the buffer pointed by this BD */
190 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
191 u32 command : 8; /* command mostly used for channel 0 */
197 struct sdma_buffer_descriptor {
198 struct sdma_mode_count mode;
199 u32 buffer_addr; /* address of the buffer described */
200 u32 ext_buffer_addr; /* extended buffer address */
201 } __attribute__ ((packed));
204 * struct sdma_channel_control - Channel control Block
206 * @current_bd_ptr: current buffer descriptor processed
207 * @base_bd_ptr: first element of buffer descriptor array
208 * @unused: padding. The SDMA engine expects an array of 128 byte
211 struct sdma_channel_control {
215 } __attribute__ ((packed));
218 * struct sdma_state_registers - SDMA context for a channel
220 * @pc: program counter
222 * @t: test bit: status of arithmetic & test instruction
223 * @rpc: return program counter
225 * @sf: source fault while loading data
226 * @spc: loop start program counter
228 * @df: destination fault while storing data
229 * @epc: loop end program counter
232 struct sdma_state_registers {
244 } __attribute__ ((packed));
247 * struct sdma_context_data - sdma context specific to a channel
249 * @channel_state: channel state bits
250 * @gReg: general registers
251 * @mda: burst dma destination address register
252 * @msa: burst dma source address register
253 * @ms: burst dma status register
254 * @md: burst dma data register
255 * @pda: peripheral dma destination address register
256 * @psa: peripheral dma source address register
257 * @ps: peripheral dma status register
258 * @pd: peripheral dma data register
259 * @ca: CRC polynomial register
260 * @cs: CRC accumulator register
261 * @dda: dedicated core destination address register
262 * @dsa: dedicated core source address register
263 * @ds: dedicated core status register
264 * @dd: dedicated core data register
265 * @scratch0: 1st word of dedicated ram for context switch
266 * @scratch1: 2nd word of dedicated ram for context switch
267 * @scratch2: 3rd word of dedicated ram for context switch
268 * @scratch3: 4th word of dedicated ram for context switch
269 * @scratch4: 5th word of dedicated ram for context switch
270 * @scratch5: 6th word of dedicated ram for context switch
271 * @scratch6: 7th word of dedicated ram for context switch
272 * @scratch7: 8th word of dedicated ram for context switch
274 struct sdma_context_data {
275 struct sdma_state_registers channel_state;
299 } __attribute__ ((packed));
305 * struct sdma_desc - descriptor structor for one transfer
306 * @vd: descriptor for virt dma
307 * @num_bd: number of descriptors currently handling
308 * @bd_phys: physical address of bd
309 * @buf_tail: ID of the buffer that was processed
310 * @buf_ptail: ID of the previous buffer that was processed
311 * @period_len: period length, used in cyclic.
312 * @chn_real_count: the real count updated from bd->mode.count
313 * @chn_count: the transfer count set
314 * @sdmac: sdma_channel pointer
315 * @bd: pointer of allocate bd
318 struct virt_dma_desc vd;
321 unsigned int buf_tail;
322 unsigned int buf_ptail;
323 unsigned int period_len;
324 unsigned int chn_real_count;
325 unsigned int chn_count;
326 struct sdma_channel *sdmac;
327 struct sdma_buffer_descriptor *bd;
331 * struct sdma_channel - housekeeping for a SDMA channel
333 * @vc: virt_dma base structure
334 * @desc: sdma description including vd and other special member
335 * @sdma: pointer to the SDMA engine for this channel
336 * @channel: the channel number, matches dmaengine chan_id + 1
337 * @direction: transfer type. Needed for setting SDMA script
338 * @slave_config Slave configuration
339 * @peripheral_type: Peripheral type. Needed for setting SDMA script
340 * @event_id0: aka dma request line
341 * @event_id1: for channels that use 2 events
342 * @word_size: peripheral access size
343 * @pc_from_device: script address for those device_2_memory
344 * @pc_to_device: script address for those memory_2_device
345 * @device_to_device: script address for those device_2_device
346 * @pc_to_pc: script address for those memory_2_memory
347 * @flags: loop mode or not
348 * @per_address: peripheral source or destination address in common case
349 * destination address in p_2_p case
350 * @per_address2: peripheral source address in p_2_p case
351 * @event_mask: event mask used in p_2_p script
352 * @watermark_level: value for gReg[7], some script will extend it from
353 * basic watermark such as p_2_p
354 * @shp_addr: value for gReg[6]
355 * @per_addr: value for gReg[2]
356 * @status: status of dma channel
357 * @data: specific sdma interface structure
358 * @bd_pool: dma_pool for bd
360 struct sdma_channel {
361 struct virt_dma_chan vc;
362 struct sdma_desc *desc;
363 struct sdma_engine *sdma;
364 unsigned int channel;
365 enum dma_transfer_direction direction;
366 struct dma_slave_config slave_config;
367 enum sdma_peripheral_type peripheral_type;
368 unsigned int event_id0;
369 unsigned int event_id1;
370 enum dma_slave_buswidth word_size;
371 unsigned int pc_from_device, pc_to_device;
372 unsigned int device_to_device;
373 unsigned int pc_to_pc;
375 dma_addr_t per_address, per_address2;
376 unsigned long event_mask[2];
377 unsigned long watermark_level;
378 u32 shp_addr, per_addr;
379 enum dma_status status;
380 struct imx_dma_data data;
381 struct work_struct terminate_worker;
384 #define IMX_DMA_SG_LOOP BIT(0)
386 #define MAX_DMA_CHANNELS 32
387 #define MXC_SDMA_DEFAULT_PRIORITY 1
388 #define MXC_SDMA_MIN_PRIORITY 1
389 #define MXC_SDMA_MAX_PRIORITY 7
391 #define SDMA_FIRMWARE_MAGIC 0x414d4453
394 * struct sdma_firmware_header - Layout of the firmware image
397 * @version_major: increased whenever layout of struct
398 * sdma_script_start_addrs changes.
399 * @version_minor: firmware minor version (for binary compatible changes)
400 * @script_addrs_start: offset of struct sdma_script_start_addrs in this image
401 * @num_script_addrs: Number of script addresses in this image
402 * @ram_code_start: offset of SDMA ram image in this firmware image
403 * @ram_code_size: size of SDMA ram image
404 * @script_addrs: Stores the start address of the SDMA scripts
405 * (in SDMA memory space)
407 struct sdma_firmware_header {
411 u32 script_addrs_start;
412 u32 num_script_addrs;
417 struct sdma_driver_data {
420 struct sdma_script_start_addrs *script_addrs;
426 struct device_dma_parameters dma_parms;
427 struct sdma_channel channel[MAX_DMA_CHANNELS];
428 struct sdma_channel_control *channel_control;
430 struct sdma_context_data *context;
431 dma_addr_t context_phys;
432 struct dma_device dma_device;
435 spinlock_t channel_0_lock;
437 struct sdma_script_start_addrs *script_addrs;
438 const struct sdma_driver_data *drvdata;
443 struct sdma_buffer_descriptor *bd0;
444 /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
448 static int sdma_config_write(struct dma_chan *chan,
449 struct dma_slave_config *dmaengine_cfg,
450 enum dma_transfer_direction direction);
452 static struct sdma_driver_data sdma_imx31 = {
453 .chnenbl0 = SDMA_CHNENBL0_IMX31,
457 static struct sdma_script_start_addrs sdma_script_imx25 = {
459 .uart_2_mcu_addr = 904,
460 .per_2_app_addr = 1255,
461 .mcu_2_app_addr = 834,
462 .uartsh_2_mcu_addr = 1120,
463 .per_2_shp_addr = 1329,
464 .mcu_2_shp_addr = 1048,
465 .ata_2_mcu_addr = 1560,
466 .mcu_2_ata_addr = 1479,
467 .app_2_per_addr = 1189,
468 .app_2_mcu_addr = 770,
469 .shp_2_per_addr = 1407,
470 .shp_2_mcu_addr = 979,
473 static struct sdma_driver_data sdma_imx25 = {
474 .chnenbl0 = SDMA_CHNENBL0_IMX35,
476 .script_addrs = &sdma_script_imx25,
479 static struct sdma_driver_data sdma_imx35 = {
480 .chnenbl0 = SDMA_CHNENBL0_IMX35,
484 static struct sdma_script_start_addrs sdma_script_imx51 = {
486 .uart_2_mcu_addr = 817,
487 .mcu_2_app_addr = 747,
488 .mcu_2_shp_addr = 961,
489 .ata_2_mcu_addr = 1473,
490 .mcu_2_ata_addr = 1392,
491 .app_2_per_addr = 1033,
492 .app_2_mcu_addr = 683,
493 .shp_2_per_addr = 1251,
494 .shp_2_mcu_addr = 892,
497 static struct sdma_driver_data sdma_imx51 = {
498 .chnenbl0 = SDMA_CHNENBL0_IMX35,
500 .script_addrs = &sdma_script_imx51,
503 static struct sdma_script_start_addrs sdma_script_imx53 = {
505 .app_2_mcu_addr = 683,
506 .mcu_2_app_addr = 747,
507 .uart_2_mcu_addr = 817,
508 .shp_2_mcu_addr = 891,
509 .mcu_2_shp_addr = 960,
510 .uartsh_2_mcu_addr = 1032,
511 .spdif_2_mcu_addr = 1100,
512 .mcu_2_spdif_addr = 1134,
513 .firi_2_mcu_addr = 1193,
514 .mcu_2_firi_addr = 1290,
517 static struct sdma_driver_data sdma_imx53 = {
518 .chnenbl0 = SDMA_CHNENBL0_IMX35,
520 .script_addrs = &sdma_script_imx53,
523 static struct sdma_script_start_addrs sdma_script_imx6q = {
525 .uart_2_mcu_addr = 817,
526 .mcu_2_app_addr = 747,
527 .per_2_per_addr = 6331,
528 .uartsh_2_mcu_addr = 1032,
529 .mcu_2_shp_addr = 960,
530 .app_2_mcu_addr = 683,
531 .shp_2_mcu_addr = 891,
532 .spdif_2_mcu_addr = 1100,
533 .mcu_2_spdif_addr = 1134,
536 static struct sdma_driver_data sdma_imx6q = {
537 .chnenbl0 = SDMA_CHNENBL0_IMX35,
539 .script_addrs = &sdma_script_imx6q,
542 static struct sdma_script_start_addrs sdma_script_imx7d = {
544 .uart_2_mcu_addr = 819,
545 .mcu_2_app_addr = 749,
546 .uartsh_2_mcu_addr = 1034,
547 .mcu_2_shp_addr = 962,
548 .app_2_mcu_addr = 685,
549 .shp_2_mcu_addr = 893,
550 .spdif_2_mcu_addr = 1102,
551 .mcu_2_spdif_addr = 1136,
554 static struct sdma_driver_data sdma_imx7d = {
555 .chnenbl0 = SDMA_CHNENBL0_IMX35,
557 .script_addrs = &sdma_script_imx7d,
560 static struct sdma_driver_data sdma_imx8mq = {
561 .chnenbl0 = SDMA_CHNENBL0_IMX35,
563 .script_addrs = &sdma_script_imx7d,
567 static const struct platform_device_id sdma_devtypes[] = {
569 .name = "imx25-sdma",
570 .driver_data = (unsigned long)&sdma_imx25,
572 .name = "imx31-sdma",
573 .driver_data = (unsigned long)&sdma_imx31,
575 .name = "imx35-sdma",
576 .driver_data = (unsigned long)&sdma_imx35,
578 .name = "imx51-sdma",
579 .driver_data = (unsigned long)&sdma_imx51,
581 .name = "imx53-sdma",
582 .driver_data = (unsigned long)&sdma_imx53,
584 .name = "imx6q-sdma",
585 .driver_data = (unsigned long)&sdma_imx6q,
587 .name = "imx7d-sdma",
588 .driver_data = (unsigned long)&sdma_imx7d,
590 .name = "imx8mq-sdma",
591 .driver_data = (unsigned long)&sdma_imx8mq,
596 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
598 static const struct of_device_id sdma_dt_ids[] = {
599 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
600 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
601 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
602 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
603 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
604 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
605 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
606 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
609 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
611 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
612 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
613 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
614 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
616 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
618 u32 chnenbl0 = sdma->drvdata->chnenbl0;
619 return chnenbl0 + event * 4;
622 static int sdma_config_ownership(struct sdma_channel *sdmac,
623 bool event_override, bool mcu_override, bool dsp_override)
625 struct sdma_engine *sdma = sdmac->sdma;
626 int channel = sdmac->channel;
627 unsigned long evt, mcu, dsp;
629 if (event_override && mcu_override && dsp_override)
632 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
633 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
634 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
637 __clear_bit(channel, &dsp);
639 __set_bit(channel, &dsp);
642 __clear_bit(channel, &evt);
644 __set_bit(channel, &evt);
647 __clear_bit(channel, &mcu);
649 __set_bit(channel, &mcu);
651 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
652 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
653 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
658 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
660 writel(BIT(channel), sdma->regs + SDMA_H_START);
664 * sdma_run_channel0 - run a channel and wait till it's done
666 static int sdma_run_channel0(struct sdma_engine *sdma)
671 sdma_enable_channel(sdma, 0);
673 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
674 reg, !(reg & 1), 1, 500);
676 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
678 /* Set bits of CONFIG register with dynamic context switching */
679 reg = readl(sdma->regs + SDMA_H_CONFIG);
680 if ((reg & SDMA_H_CONFIG_CSM) == 0) {
681 reg |= SDMA_H_CONFIG_CSM;
682 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG);
688 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
691 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
697 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL);
702 spin_lock_irqsave(&sdma->channel_0_lock, flags);
704 bd0->mode.command = C0_SETPM;
705 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
706 bd0->mode.count = size / 2;
707 bd0->buffer_addr = buf_phys;
708 bd0->ext_buffer_addr = address;
710 memcpy(buf_virt, buf, size);
712 ret = sdma_run_channel0(sdma);
714 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
716 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys);
721 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
723 struct sdma_engine *sdma = sdmac->sdma;
724 int channel = sdmac->channel;
726 u32 chnenbl = chnenbl_ofs(sdma, event);
728 val = readl_relaxed(sdma->regs + chnenbl);
729 __set_bit(channel, &val);
730 writel_relaxed(val, sdma->regs + chnenbl);
733 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
735 struct sdma_engine *sdma = sdmac->sdma;
736 int channel = sdmac->channel;
737 u32 chnenbl = chnenbl_ofs(sdma, event);
740 val = readl_relaxed(sdma->regs + chnenbl);
741 __clear_bit(channel, &val);
742 writel_relaxed(val, sdma->regs + chnenbl);
745 static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t)
747 return container_of(t, struct sdma_desc, vd.tx);
750 static void sdma_start_desc(struct sdma_channel *sdmac)
752 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc);
753 struct sdma_desc *desc;
754 struct sdma_engine *sdma = sdmac->sdma;
755 int channel = sdmac->channel;
761 sdmac->desc = desc = to_sdma_desc(&vd->tx);
763 * Do not delete the node in desc_issued list in cyclic mode, otherwise
764 * the desc allocated will never be freed in vchan_dma_desc_free_list
766 if (!(sdmac->flags & IMX_DMA_SG_LOOP))
769 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
770 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
771 sdma_enable_channel(sdma, sdmac->channel);
774 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
776 struct sdma_buffer_descriptor *bd;
778 enum dma_status old_status = sdmac->status;
781 * loop mode. Iterate over descriptors, re-setup them and
782 * call callback function.
784 while (sdmac->desc) {
785 struct sdma_desc *desc = sdmac->desc;
787 bd = &desc->bd[desc->buf_tail];
789 if (bd->mode.status & BD_DONE)
792 if (bd->mode.status & BD_RROR) {
793 bd->mode.status &= ~BD_RROR;
794 sdmac->status = DMA_ERROR;
799 * We use bd->mode.count to calculate the residue, since contains
800 * the number of bytes present in the current buffer descriptor.
803 desc->chn_real_count = bd->mode.count;
804 bd->mode.status |= BD_DONE;
805 bd->mode.count = desc->period_len;
806 desc->buf_ptail = desc->buf_tail;
807 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
810 * The callback is called from the interrupt context in order
811 * to reduce latency and to avoid the risk of altering the
812 * SDMA transaction status by the time the client tasklet is
815 spin_unlock(&sdmac->vc.lock);
816 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL);
817 spin_lock(&sdmac->vc.lock);
820 sdmac->status = old_status;
824 static void mxc_sdma_handle_channel_normal(struct sdma_channel *data)
826 struct sdma_channel *sdmac = (struct sdma_channel *) data;
827 struct sdma_buffer_descriptor *bd;
830 sdmac->desc->chn_real_count = 0;
832 * non loop mode. Iterate over all descriptors, collect
833 * errors and call callback function
835 for (i = 0; i < sdmac->desc->num_bd; i++) {
836 bd = &sdmac->desc->bd[i];
838 if (bd->mode.status & (BD_DONE | BD_RROR))
840 sdmac->desc->chn_real_count += bd->mode.count;
844 sdmac->status = DMA_ERROR;
846 sdmac->status = DMA_COMPLETE;
849 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
851 struct sdma_engine *sdma = dev_id;
854 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
855 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
856 /* channel 0 is special and not handled here, see run_channel0() */
860 int channel = fls(stat) - 1;
861 struct sdma_channel *sdmac = &sdma->channel[channel];
862 struct sdma_desc *desc;
864 spin_lock(&sdmac->vc.lock);
867 if (sdmac->flags & IMX_DMA_SG_LOOP) {
868 sdma_update_channel_loop(sdmac);
870 mxc_sdma_handle_channel_normal(sdmac);
871 vchan_cookie_complete(&desc->vd);
872 sdma_start_desc(sdmac);
876 spin_unlock(&sdmac->vc.lock);
877 __clear_bit(channel, &stat);
884 * sets the pc of SDMA script according to the peripheral type
886 static void sdma_get_pc(struct sdma_channel *sdmac,
887 enum sdma_peripheral_type peripheral_type)
889 struct sdma_engine *sdma = sdmac->sdma;
890 int per_2_emi = 0, emi_2_per = 0;
892 * These are needed once we start to support transfers between
893 * two peripherals or memory-to-memory transfers
895 int per_2_per = 0, emi_2_emi = 0;
897 sdmac->pc_from_device = 0;
898 sdmac->pc_to_device = 0;
899 sdmac->device_to_device = 0;
902 switch (peripheral_type) {
903 case IMX_DMATYPE_MEMORY:
904 emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
906 case IMX_DMATYPE_DSP:
907 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
908 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
910 case IMX_DMATYPE_FIRI:
911 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
912 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
914 case IMX_DMATYPE_UART:
915 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
916 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
918 case IMX_DMATYPE_UART_SP:
919 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
920 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
922 case IMX_DMATYPE_ATA:
923 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
924 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
926 case IMX_DMATYPE_CSPI:
927 case IMX_DMATYPE_EXT:
928 case IMX_DMATYPE_SSI:
929 case IMX_DMATYPE_SAI:
930 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
931 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
933 case IMX_DMATYPE_SSI_DUAL:
934 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
935 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
937 case IMX_DMATYPE_SSI_SP:
938 case IMX_DMATYPE_MMC:
939 case IMX_DMATYPE_SDHC:
940 case IMX_DMATYPE_CSPI_SP:
941 case IMX_DMATYPE_ESAI:
942 case IMX_DMATYPE_MSHC_SP:
943 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
944 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
946 case IMX_DMATYPE_ASRC:
947 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
948 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
949 per_2_per = sdma->script_addrs->per_2_per_addr;
951 case IMX_DMATYPE_ASRC_SP:
952 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
953 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
954 per_2_per = sdma->script_addrs->per_2_per_addr;
956 case IMX_DMATYPE_MSHC:
957 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
958 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
960 case IMX_DMATYPE_CCM:
961 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
963 case IMX_DMATYPE_SPDIF:
964 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
965 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
967 case IMX_DMATYPE_IPU_MEMORY:
968 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
974 sdmac->pc_from_device = per_2_emi;
975 sdmac->pc_to_device = emi_2_per;
976 sdmac->device_to_device = per_2_per;
977 sdmac->pc_to_pc = emi_2_emi;
980 static int sdma_load_context(struct sdma_channel *sdmac)
982 struct sdma_engine *sdma = sdmac->sdma;
983 int channel = sdmac->channel;
985 struct sdma_context_data *context = sdma->context;
986 struct sdma_buffer_descriptor *bd0 = sdma->bd0;
990 if (sdmac->direction == DMA_DEV_TO_MEM)
991 load_address = sdmac->pc_from_device;
992 else if (sdmac->direction == DMA_DEV_TO_DEV)
993 load_address = sdmac->device_to_device;
994 else if (sdmac->direction == DMA_MEM_TO_MEM)
995 load_address = sdmac->pc_to_pc;
997 load_address = sdmac->pc_to_device;
999 if (load_address < 0)
1000 return load_address;
1002 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
1003 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
1004 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
1005 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
1006 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
1007 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
1009 spin_lock_irqsave(&sdma->channel_0_lock, flags);
1011 memset(context, 0, sizeof(*context));
1012 context->channel_state.pc = load_address;
1014 /* Send by context the event mask,base address for peripheral
1015 * and watermark level
1017 context->gReg[0] = sdmac->event_mask[1];
1018 context->gReg[1] = sdmac->event_mask[0];
1019 context->gReg[2] = sdmac->per_addr;
1020 context->gReg[6] = sdmac->shp_addr;
1021 context->gReg[7] = sdmac->watermark_level;
1023 bd0->mode.command = C0_SETDM;
1024 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
1025 bd0->mode.count = sizeof(*context) / 4;
1026 bd0->buffer_addr = sdma->context_phys;
1027 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
1028 ret = sdma_run_channel0(sdma);
1030 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
1035 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
1037 return container_of(chan, struct sdma_channel, vc.chan);
1040 static int sdma_disable_channel(struct dma_chan *chan)
1042 struct sdma_channel *sdmac = to_sdma_chan(chan);
1043 struct sdma_engine *sdma = sdmac->sdma;
1044 int channel = sdmac->channel;
1046 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
1047 sdmac->status = DMA_ERROR;
1051 static void sdma_channel_terminate_work(struct work_struct *work)
1053 struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
1055 unsigned long flags;
1059 * According to NXP R&D team a delay of one BD SDMA cost time
1060 * (maximum is 1ms) should be added after disable of the channel
1061 * bit, to ensure SDMA core has really been stopped after SDMA
1062 * clients call .device_terminate_all.
1064 usleep_range(1000, 2000);
1066 spin_lock_irqsave(&sdmac->vc.lock, flags);
1067 vchan_get_all_descriptors(&sdmac->vc, &head);
1069 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1070 vchan_dma_desc_free_list(&sdmac->vc, &head);
1073 static int sdma_disable_channel_async(struct dma_chan *chan)
1075 struct sdma_channel *sdmac = to_sdma_chan(chan);
1077 sdma_disable_channel(chan);
1080 schedule_work(&sdmac->terminate_worker);
1085 static void sdma_channel_synchronize(struct dma_chan *chan)
1087 struct sdma_channel *sdmac = to_sdma_chan(chan);
1089 vchan_synchronize(&sdmac->vc);
1091 flush_work(&sdmac->terminate_worker);
1094 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
1096 struct sdma_engine *sdma = sdmac->sdma;
1098 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
1099 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
1101 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
1102 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
1104 if (sdmac->event_id0 > 31)
1105 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
1107 if (sdmac->event_id1 > 31)
1108 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
1111 * If LWML(src_maxburst) > HWML(dst_maxburst), we need
1112 * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
1113 * r0(event_mask[1]) and r1(event_mask[0]).
1116 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
1117 SDMA_WATERMARK_LEVEL_HWML);
1118 sdmac->watermark_level |= hwml;
1119 sdmac->watermark_level |= lwml << 16;
1120 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
1123 if (sdmac->per_address2 >= sdma->spba_start_addr &&
1124 sdmac->per_address2 <= sdma->spba_end_addr)
1125 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
1127 if (sdmac->per_address >= sdma->spba_start_addr &&
1128 sdmac->per_address <= sdma->spba_end_addr)
1129 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
1131 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
1134 static int sdma_config_channel(struct dma_chan *chan)
1136 struct sdma_channel *sdmac = to_sdma_chan(chan);
1138 sdma_disable_channel(chan);
1140 sdmac->event_mask[0] = 0;
1141 sdmac->event_mask[1] = 0;
1142 sdmac->shp_addr = 0;
1143 sdmac->per_addr = 0;
1145 switch (sdmac->peripheral_type) {
1146 case IMX_DMATYPE_DSP:
1147 sdma_config_ownership(sdmac, false, true, true);
1149 case IMX_DMATYPE_MEMORY:
1150 sdma_config_ownership(sdmac, false, true, false);
1153 sdma_config_ownership(sdmac, true, true, false);
1157 sdma_get_pc(sdmac, sdmac->peripheral_type);
1159 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
1160 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
1161 /* Handle multiple event channels differently */
1162 if (sdmac->event_id1) {
1163 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
1164 sdmac->peripheral_type == IMX_DMATYPE_ASRC)
1165 sdma_set_watermarklevel_for_p2p(sdmac);
1167 __set_bit(sdmac->event_id0, sdmac->event_mask);
1170 sdmac->shp_addr = sdmac->per_address;
1171 sdmac->per_addr = sdmac->per_address2;
1173 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
1179 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1180 unsigned int priority)
1182 struct sdma_engine *sdma = sdmac->sdma;
1183 int channel = sdmac->channel;
1185 if (priority < MXC_SDMA_MIN_PRIORITY
1186 || priority > MXC_SDMA_MAX_PRIORITY) {
1190 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1195 static int sdma_request_channel0(struct sdma_engine *sdma)
1199 sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys,
1206 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
1207 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
1209 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
1217 static int sdma_alloc_bd(struct sdma_desc *desc)
1219 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1222 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size,
1223 &desc->bd_phys, GFP_NOWAIT);
1232 static void sdma_free_bd(struct sdma_desc *desc)
1234 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
1236 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd,
1240 static void sdma_desc_free(struct virt_dma_desc *vd)
1242 struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd);
1248 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1250 struct sdma_channel *sdmac = to_sdma_chan(chan);
1251 struct imx_dma_data *data = chan->private;
1252 struct imx_dma_data mem_data;
1256 * MEMCPY may never setup chan->private by filter function such as
1257 * dmatest, thus create 'struct imx_dma_data mem_data' for this case.
1258 * Please note in any other slave case, you have to setup chan->private
1259 * with 'struct imx_dma_data' in your own filter function if you want to
1260 * request dma channel by dma_request_channel() rather than
1261 * dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear
1262 * to warn you to correct your filter function.
1265 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
1266 mem_data.priority = 2;
1267 mem_data.peripheral_type = IMX_DMATYPE_MEMORY;
1268 mem_data.dma_request = 0;
1269 mem_data.dma_request2 = 0;
1272 sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
1275 switch (data->priority) {
1279 case DMA_PRIO_MEDIUM:
1288 sdmac->peripheral_type = data->peripheral_type;
1289 sdmac->event_id0 = data->dma_request;
1290 sdmac->event_id1 = data->dma_request2;
1292 ret = clk_enable(sdmac->sdma->clk_ipg);
1295 ret = clk_enable(sdmac->sdma->clk_ahb);
1297 goto disable_clk_ipg;
1299 ret = sdma_set_channel_priority(sdmac, prio);
1301 goto disable_clk_ahb;
1306 clk_disable(sdmac->sdma->clk_ahb);
1308 clk_disable(sdmac->sdma->clk_ipg);
1312 static void sdma_free_chan_resources(struct dma_chan *chan)
1314 struct sdma_channel *sdmac = to_sdma_chan(chan);
1315 struct sdma_engine *sdma = sdmac->sdma;
1317 sdma_disable_channel_async(chan);
1319 sdma_channel_synchronize(chan);
1321 if (sdmac->event_id0 >= 0)
1322 sdma_event_disable(sdmac, sdmac->event_id0);
1323 if (sdmac->event_id1)
1324 sdma_event_disable(sdmac, sdmac->event_id1);
1326 sdmac->event_id0 = 0;
1327 sdmac->event_id1 = 0;
1329 sdma_set_channel_priority(sdmac, 0);
1331 clk_disable(sdma->clk_ipg);
1332 clk_disable(sdma->clk_ahb);
1335 static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
1336 enum dma_transfer_direction direction, u32 bds)
1338 struct sdma_desc *desc;
1340 desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
1344 sdmac->status = DMA_IN_PROGRESS;
1345 sdmac->direction = direction;
1348 desc->chn_count = 0;
1349 desc->chn_real_count = 0;
1351 desc->buf_ptail = 0;
1352 desc->sdmac = sdmac;
1355 if (sdma_alloc_bd(desc))
1358 /* No slave_config called in MEMCPY case, so do here */
1359 if (direction == DMA_MEM_TO_MEM)
1360 sdma_config_ownership(sdmac, false, true, false);
1362 if (sdma_load_context(sdmac))
1373 static struct dma_async_tx_descriptor *sdma_prep_memcpy(
1374 struct dma_chan *chan, dma_addr_t dma_dst,
1375 dma_addr_t dma_src, size_t len, unsigned long flags)
1377 struct sdma_channel *sdmac = to_sdma_chan(chan);
1378 struct sdma_engine *sdma = sdmac->sdma;
1379 int channel = sdmac->channel;
1382 struct sdma_buffer_descriptor *bd;
1383 struct sdma_desc *desc;
1388 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n",
1389 &dma_src, &dma_dst, len, channel);
1391 desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM,
1392 len / SDMA_BD_MAX_CNT + 1);
1397 count = min_t(size_t, len, SDMA_BD_MAX_CNT);
1399 bd->buffer_addr = dma_src;
1400 bd->ext_buffer_addr = dma_dst;
1401 bd->mode.count = count;
1402 desc->chn_count += count;
1403 bd->mode.command = 0;
1410 param = BD_DONE | BD_EXTD | BD_CONT;
1418 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n",
1419 i, count, bd->buffer_addr,
1420 param & BD_WRAP ? "wrap" : "",
1421 param & BD_INTR ? " intr" : "");
1423 bd->mode.status = param;
1426 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1429 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1430 struct dma_chan *chan, struct scatterlist *sgl,
1431 unsigned int sg_len, enum dma_transfer_direction direction,
1432 unsigned long flags, void *context)
1434 struct sdma_channel *sdmac = to_sdma_chan(chan);
1435 struct sdma_engine *sdma = sdmac->sdma;
1437 int channel = sdmac->channel;
1438 struct scatterlist *sg;
1439 struct sdma_desc *desc;
1441 sdma_config_write(chan, &sdmac->slave_config, direction);
1443 desc = sdma_transfer_init(sdmac, direction, sg_len);
1447 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1450 for_each_sg(sgl, sg, sg_len, i) {
1451 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1454 bd->buffer_addr = sg->dma_address;
1456 count = sg_dma_len(sg);
1458 if (count > SDMA_BD_MAX_CNT) {
1459 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1460 channel, count, SDMA_BD_MAX_CNT);
1464 bd->mode.count = count;
1465 desc->chn_count += count;
1467 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1470 switch (sdmac->word_size) {
1471 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1472 bd->mode.command = 0;
1473 if (count & 3 || sg->dma_address & 3)
1476 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1477 bd->mode.command = 2;
1478 if (count & 1 || sg->dma_address & 1)
1481 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1482 bd->mode.command = 1;
1488 param = BD_DONE | BD_EXTD | BD_CONT;
1490 if (i + 1 == sg_len) {
1496 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1497 i, count, (u64)sg->dma_address,
1498 param & BD_WRAP ? "wrap" : "",
1499 param & BD_INTR ? " intr" : "");
1501 bd->mode.status = param;
1504 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1509 sdmac->status = DMA_ERROR;
1513 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1514 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1515 size_t period_len, enum dma_transfer_direction direction,
1516 unsigned long flags)
1518 struct sdma_channel *sdmac = to_sdma_chan(chan);
1519 struct sdma_engine *sdma = sdmac->sdma;
1520 int num_periods = buf_len / period_len;
1521 int channel = sdmac->channel;
1523 struct sdma_desc *desc;
1525 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1527 sdma_config_write(chan, &sdmac->slave_config, direction);
1529 desc = sdma_transfer_init(sdmac, direction, num_periods);
1533 desc->period_len = period_len;
1535 sdmac->flags |= IMX_DMA_SG_LOOP;
1537 if (period_len > SDMA_BD_MAX_CNT) {
1538 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
1539 channel, period_len, SDMA_BD_MAX_CNT);
1543 while (buf < buf_len) {
1544 struct sdma_buffer_descriptor *bd = &desc->bd[i];
1547 bd->buffer_addr = dma_addr;
1549 bd->mode.count = period_len;
1551 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1553 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1554 bd->mode.command = 0;
1556 bd->mode.command = sdmac->word_size;
1558 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1559 if (i + 1 == num_periods)
1562 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
1563 i, period_len, (u64)dma_addr,
1564 param & BD_WRAP ? "wrap" : "",
1565 param & BD_INTR ? " intr" : "");
1567 bd->mode.status = param;
1569 dma_addr += period_len;
1575 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
1580 sdmac->status = DMA_ERROR;
1584 static int sdma_config_write(struct dma_chan *chan,
1585 struct dma_slave_config *dmaengine_cfg,
1586 enum dma_transfer_direction direction)
1588 struct sdma_channel *sdmac = to_sdma_chan(chan);
1590 if (direction == DMA_DEV_TO_MEM) {
1591 sdmac->per_address = dmaengine_cfg->src_addr;
1592 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1593 dmaengine_cfg->src_addr_width;
1594 sdmac->word_size = dmaengine_cfg->src_addr_width;
1595 } else if (direction == DMA_DEV_TO_DEV) {
1596 sdmac->per_address2 = dmaengine_cfg->src_addr;
1597 sdmac->per_address = dmaengine_cfg->dst_addr;
1598 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1599 SDMA_WATERMARK_LEVEL_LWML;
1600 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1601 SDMA_WATERMARK_LEVEL_HWML;
1602 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1604 sdmac->per_address = dmaengine_cfg->dst_addr;
1605 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1606 dmaengine_cfg->dst_addr_width;
1607 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1609 sdmac->direction = direction;
1610 return sdma_config_channel(chan);
1613 static int sdma_config(struct dma_chan *chan,
1614 struct dma_slave_config *dmaengine_cfg)
1616 struct sdma_channel *sdmac = to_sdma_chan(chan);
1618 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
1620 /* Set ENBLn earlier to make sure dma request triggered after that */
1621 if (sdmac->event_id0 >= 0) {
1622 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
1624 sdma_event_enable(sdmac, sdmac->event_id0);
1627 if (sdmac->event_id1) {
1628 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
1630 sdma_event_enable(sdmac, sdmac->event_id1);
1636 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1637 dma_cookie_t cookie,
1638 struct dma_tx_state *txstate)
1640 struct sdma_channel *sdmac = to_sdma_chan(chan);
1641 struct sdma_desc *desc;
1643 struct virt_dma_desc *vd;
1644 enum dma_status ret;
1645 unsigned long flags;
1647 ret = dma_cookie_status(chan, cookie, txstate);
1648 if (ret == DMA_COMPLETE || !txstate)
1651 spin_lock_irqsave(&sdmac->vc.lock, flags);
1652 vd = vchan_find_desc(&sdmac->vc, cookie);
1654 desc = to_sdma_desc(&vd->tx);
1655 if (sdmac->flags & IMX_DMA_SG_LOOP)
1656 residue = (desc->num_bd - desc->buf_ptail) *
1657 desc->period_len - desc->chn_real_count;
1659 residue = desc->chn_count - desc->chn_real_count;
1660 } else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) {
1661 residue = sdmac->desc->chn_count - sdmac->desc->chn_real_count;
1665 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1667 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1670 return sdmac->status;
1673 static void sdma_issue_pending(struct dma_chan *chan)
1675 struct sdma_channel *sdmac = to_sdma_chan(chan);
1676 unsigned long flags;
1678 spin_lock_irqsave(&sdmac->vc.lock, flags);
1679 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc)
1680 sdma_start_desc(sdmac);
1681 spin_unlock_irqrestore(&sdmac->vc.lock, flags);
1684 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1685 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1686 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1687 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
1689 static void sdma_add_scripts(struct sdma_engine *sdma,
1690 const struct sdma_script_start_addrs *addr)
1692 s32 *addr_arr = (u32 *)addr;
1693 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1696 /* use the default firmware in ROM if missing external firmware */
1697 if (!sdma->script_number)
1698 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1700 if (sdma->script_number > sizeof(struct sdma_script_start_addrs)
1703 "SDMA script number %d not match with firmware.\n",
1704 sdma->script_number);
1708 for (i = 0; i < sdma->script_number; i++)
1709 if (addr_arr[i] > 0)
1710 saddr_arr[i] = addr_arr[i];
1713 static void sdma_load_firmware(const struct firmware *fw, void *context)
1715 struct sdma_engine *sdma = context;
1716 const struct sdma_firmware_header *header;
1717 const struct sdma_script_start_addrs *addr;
1718 unsigned short *ram_code;
1721 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1722 /* In this case we just use the ROM firmware. */
1726 if (fw->size < sizeof(*header))
1729 header = (struct sdma_firmware_header *)fw->data;
1731 if (header->magic != SDMA_FIRMWARE_MAGIC)
1733 if (header->ram_code_start + header->ram_code_size > fw->size)
1735 switch (header->version_major) {
1737 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1740 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1743 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1746 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
1749 dev_err(sdma->dev, "unknown firmware version\n");
1753 addr = (void *)header + header->script_addrs_start;
1754 ram_code = (void *)header + header->ram_code_start;
1756 clk_enable(sdma->clk_ipg);
1757 clk_enable(sdma->clk_ahb);
1758 /* download the RAM image for SDMA */
1759 sdma_load_script(sdma, ram_code,
1760 header->ram_code_size,
1761 addr->ram_code_start_addr);
1762 clk_disable(sdma->clk_ipg);
1763 clk_disable(sdma->clk_ahb);
1765 sdma_add_scripts(sdma, addr);
1767 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1768 header->version_major,
1769 header->version_minor);
1772 release_firmware(fw);
1775 #define EVENT_REMAP_CELLS 3
1777 static int sdma_event_remap(struct sdma_engine *sdma)
1779 struct device_node *np = sdma->dev->of_node;
1780 struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1781 struct property *event_remap;
1783 char propname[] = "fsl,sdma-event-remap";
1784 u32 reg, val, shift, num_map, i;
1787 if (IS_ERR(np) || !gpr_np)
1790 event_remap = of_find_property(np, propname, NULL);
1791 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1793 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1795 } else if (num_map % EVENT_REMAP_CELLS) {
1796 dev_err(sdma->dev, "the property %s must modulo %d\n",
1797 propname, EVENT_REMAP_CELLS);
1802 gpr = syscon_node_to_regmap(gpr_np);
1804 dev_err(sdma->dev, "failed to get gpr regmap\n");
1809 for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1810 ret = of_property_read_u32_index(np, propname, i, ®);
1812 dev_err(sdma->dev, "failed to read property %s index %d\n",
1817 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1819 dev_err(sdma->dev, "failed to read property %s index %d\n",
1824 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1826 dev_err(sdma->dev, "failed to read property %s index %d\n",
1831 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1836 of_node_put(gpr_np);
1841 static int sdma_get_firmware(struct sdma_engine *sdma,
1842 const char *fw_name)
1846 ret = reject_firmware_nowait(THIS_MODULE,
1847 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1848 GFP_KERNEL, sdma, sdma_load_firmware);
1853 static int sdma_init(struct sdma_engine *sdma)
1856 dma_addr_t ccb_phys;
1858 ret = clk_enable(sdma->clk_ipg);
1861 ret = clk_enable(sdma->clk_ahb);
1863 goto disable_clk_ipg;
1865 if (sdma->drvdata->check_ratio &&
1866 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg)))
1867 sdma->clk_ratio = 1;
1869 /* Be sure SDMA has not started yet */
1870 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1872 sdma->channel_control = dma_alloc_coherent(sdma->dev,
1873 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1874 sizeof(struct sdma_context_data),
1875 &ccb_phys, GFP_KERNEL);
1877 if (!sdma->channel_control) {
1882 sdma->context = (void *)sdma->channel_control +
1883 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1884 sdma->context_phys = ccb_phys +
1885 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1887 /* disable all channels */
1888 for (i = 0; i < sdma->drvdata->num_events; i++)
1889 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1891 /* All channels have priority 0 */
1892 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1893 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1895 ret = sdma_request_channel0(sdma);
1899 sdma_config_ownership(&sdma->channel[0], false, true, false);
1901 /* Set Command Channel (Channel Zero) */
1902 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1904 /* Set bits of CONFIG register but with static context switching */
1905 if (sdma->clk_ratio)
1906 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG);
1908 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1910 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1912 /* Initializes channel's priorities */
1913 sdma_set_channel_priority(&sdma->channel[0], 7);
1915 clk_disable(sdma->clk_ipg);
1916 clk_disable(sdma->clk_ahb);
1921 clk_disable(sdma->clk_ahb);
1923 clk_disable(sdma->clk_ipg);
1924 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1928 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1930 struct sdma_channel *sdmac = to_sdma_chan(chan);
1931 struct imx_dma_data *data = fn_param;
1933 if (!imx_dma_is_general_purpose(chan))
1936 sdmac->data = *data;
1937 chan->private = &sdmac->data;
1942 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1943 struct of_dma *ofdma)
1945 struct sdma_engine *sdma = ofdma->of_dma_data;
1946 dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1947 struct imx_dma_data data;
1949 if (dma_spec->args_count != 3)
1952 data.dma_request = dma_spec->args[0];
1953 data.peripheral_type = dma_spec->args[1];
1954 data.priority = dma_spec->args[2];
1956 * init dma_request2 to zero, which is not used by the dts.
1957 * For P2P, dma_request2 is init from dma_request_channel(),
1958 * chan->private will point to the imx_dma_data, and in
1959 * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1960 * be set to sdmac->event_id1.
1962 data.dma_request2 = 0;
1964 return __dma_request_channel(&mask, sdma_filter_fn, &data,
1968 static int sdma_probe(struct platform_device *pdev)
1970 const struct of_device_id *of_id =
1971 of_match_device(sdma_dt_ids, &pdev->dev);
1972 struct device_node *np = pdev->dev.of_node;
1973 struct device_node *spba_bus;
1974 const char *fw_name;
1977 struct resource *iores;
1978 struct resource spba_res;
1979 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1981 struct sdma_engine *sdma;
1983 const struct sdma_driver_data *drvdata = NULL;
1986 drvdata = of_id->data;
1987 else if (pdev->id_entry)
1988 drvdata = (void *)pdev->id_entry->driver_data;
1991 dev_err(&pdev->dev, "unable to find driver data\n");
1995 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1999 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
2003 spin_lock_init(&sdma->channel_0_lock);
2005 sdma->dev = &pdev->dev;
2006 sdma->drvdata = drvdata;
2008 irq = platform_get_irq(pdev, 0);
2012 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2013 sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
2014 if (IS_ERR(sdma->regs))
2015 return PTR_ERR(sdma->regs);
2017 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2018 if (IS_ERR(sdma->clk_ipg))
2019 return PTR_ERR(sdma->clk_ipg);
2021 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2022 if (IS_ERR(sdma->clk_ahb))
2023 return PTR_ERR(sdma->clk_ahb);
2025 ret = clk_prepare(sdma->clk_ipg);
2029 ret = clk_prepare(sdma->clk_ahb);
2033 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
2040 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
2041 if (!sdma->script_addrs) {
2046 /* initially no scripts available */
2047 saddr_arr = (s32 *)sdma->script_addrs;
2048 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
2049 saddr_arr[i] = -EINVAL;
2051 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
2052 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
2053 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
2055 INIT_LIST_HEAD(&sdma->dma_device.channels);
2056 /* Initialize channel parameters */
2057 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2058 struct sdma_channel *sdmac = &sdma->channel[i];
2063 sdmac->vc.desc_free = sdma_desc_free;
2064 INIT_WORK(&sdmac->terminate_worker,
2065 sdma_channel_terminate_work);
2067 * Add the channel to the DMAC list. Do not add channel 0 though
2068 * because we need it internally in the SDMA driver. This also means
2069 * that channel 0 in dmaengine counting matches sdma channel 1.
2072 vchan_init(&sdmac->vc, &sdma->dma_device);
2075 ret = sdma_init(sdma);
2079 ret = sdma_event_remap(sdma);
2083 if (sdma->drvdata->script_addrs)
2084 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
2085 if (pdata && pdata->script_addrs)
2086 sdma_add_scripts(sdma, pdata->script_addrs);
2088 sdma->dma_device.dev = &pdev->dev;
2090 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
2091 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
2092 sdma->dma_device.device_tx_status = sdma_tx_status;
2093 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
2094 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
2095 sdma->dma_device.device_config = sdma_config;
2096 sdma->dma_device.device_terminate_all = sdma_disable_channel_async;
2097 sdma->dma_device.device_synchronize = sdma_channel_synchronize;
2098 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
2099 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
2100 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
2101 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2102 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy;
2103 sdma->dma_device.device_issue_pending = sdma_issue_pending;
2104 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
2105 sdma->dma_device.copy_align = 2;
2106 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT);
2108 platform_set_drvdata(pdev, sdma);
2110 ret = dma_async_device_register(&sdma->dma_device);
2112 dev_err(&pdev->dev, "unable to register\n");
2117 ret = of_dma_controller_register(np, sdma_xlate, sdma);
2119 dev_err(&pdev->dev, "failed to register controller\n");
2123 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
2124 ret = of_address_to_resource(spba_bus, 0, &spba_res);
2126 sdma->spba_start_addr = spba_res.start;
2127 sdma->spba_end_addr = spba_res.end;
2129 of_node_put(spba_bus);
2133 * Kick off firmware loading as the very last step:
2134 * attempt to load firmware only if we're not on the error path, because
2135 * the firmware callback requires a fully functional and allocated sdma
2139 ret = sdma_get_firmware(sdma, pdata->fw_name);
2141 dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
2144 * Because that device tree does not encode ROM script address,
2145 * the RAM script in firmware is mandatory for device tree
2146 * probe, otherwise it fails.
2148 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
2151 dev_warn(&pdev->dev, "failed to get firmware name\n");
2153 ret = sdma_get_firmware(sdma, fw_name);
2155 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
2162 dma_async_device_unregister(&sdma->dma_device);
2164 kfree(sdma->script_addrs);
2166 clk_unprepare(sdma->clk_ahb);
2168 clk_unprepare(sdma->clk_ipg);
2172 static int sdma_remove(struct platform_device *pdev)
2174 struct sdma_engine *sdma = platform_get_drvdata(pdev);
2177 devm_free_irq(&pdev->dev, sdma->irq, sdma);
2178 dma_async_device_unregister(&sdma->dma_device);
2179 kfree(sdma->script_addrs);
2180 clk_unprepare(sdma->clk_ahb);
2181 clk_unprepare(sdma->clk_ipg);
2182 /* Kill the tasklet */
2183 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
2184 struct sdma_channel *sdmac = &sdma->channel[i];
2186 tasklet_kill(&sdmac->vc.task);
2187 sdma_free_chan_resources(&sdmac->vc.chan);
2190 platform_set_drvdata(pdev, NULL);
2194 static struct platform_driver sdma_driver = {
2197 .of_match_table = sdma_dt_ids,
2199 .id_table = sdma_devtypes,
2200 .remove = sdma_remove,
2201 .probe = sdma_probe,
2204 module_platform_driver(sdma_driver);
2206 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
2207 MODULE_DESCRIPTION("i.MX SDMA driver");
2208 #if IS_ENABLED(CONFIG_SOC_IMX6Q)
2211 #if IS_ENABLED(CONFIG_SOC_IMX7D)
2214 MODULE_LICENSE("GPL");