1 // SPDX-License-Identifier: GPL-2.0+
3 // drivers/dma/imx-dma.c
5 // This file contains a driver for the Freescale i.MX DMA engine
6 // found on i.MX1/21/27
8 // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
9 // Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
11 #include <linux/err.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
15 #include <linux/interrupt.h>
16 #include <linux/spinlock.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/slab.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/dmaengine.h>
23 #include <linux/module.h>
24 #include <linux/of_device.h>
25 #include <linux/of_dma.h>
28 #include <linux/platform_data/dma-imx.h>
30 #include "dmaengine.h"
31 #define IMXDMA_MAX_CHAN_DESCRIPTORS 16
32 #define IMX_DMA_CHANNELS 16
34 #define IMX_DMA_2D_SLOTS 2
35 #define IMX_DMA_2D_SLOT_A 0
36 #define IMX_DMA_2D_SLOT_B 1
38 #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
39 #define IMX_DMA_MEMSIZE_32 (0 << 4)
40 #define IMX_DMA_MEMSIZE_8 (1 << 4)
41 #define IMX_DMA_MEMSIZE_16 (2 << 4)
42 #define IMX_DMA_TYPE_LINEAR (0 << 10)
43 #define IMX_DMA_TYPE_2D (1 << 10)
44 #define IMX_DMA_TYPE_FIFO (2 << 10)
46 #define IMX_DMA_ERR_BURST (1 << 0)
47 #define IMX_DMA_ERR_REQUEST (1 << 1)
48 #define IMX_DMA_ERR_TRANSFER (1 << 2)
49 #define IMX_DMA_ERR_BUFFER (1 << 3)
50 #define IMX_DMA_ERR_TIMEOUT (1 << 4)
52 #define DMA_DCR 0x00 /* Control Register */
53 #define DMA_DISR 0x04 /* Interrupt status Register */
54 #define DMA_DIMR 0x08 /* Interrupt mask Register */
55 #define DMA_DBTOSR 0x0c /* Burst timeout status Register */
56 #define DMA_DRTOSR 0x10 /* Request timeout Register */
57 #define DMA_DSESR 0x14 /* Transfer Error Status Register */
58 #define DMA_DBOSR 0x18 /* Buffer overflow status Register */
59 #define DMA_DBTOCR 0x1c /* Burst timeout control Register */
60 #define DMA_WSRA 0x40 /* W-Size Register A */
61 #define DMA_XSRA 0x44 /* X-Size Register A */
62 #define DMA_YSRA 0x48 /* Y-Size Register A */
63 #define DMA_WSRB 0x4c /* W-Size Register B */
64 #define DMA_XSRB 0x50 /* X-Size Register B */
65 #define DMA_YSRB 0x54 /* Y-Size Register B */
66 #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
67 #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
68 #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
69 #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
70 #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
71 #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
72 #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
73 #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
74 #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
76 #define DCR_DRST (1<<1)
77 #define DCR_DEN (1<<0)
78 #define DBTOCR_EN (1<<15)
79 #define DBTOCR_CNT(x) ((x) & 0x7fff)
80 #define CNTR_CNT(x) ((x) & 0xffffff)
81 #define CCR_ACRPT (1<<14)
82 #define CCR_DMOD_LINEAR (0x0 << 12)
83 #define CCR_DMOD_2D (0x1 << 12)
84 #define CCR_DMOD_FIFO (0x2 << 12)
85 #define CCR_DMOD_EOBFIFO (0x3 << 12)
86 #define CCR_SMOD_LINEAR (0x0 << 10)
87 #define CCR_SMOD_2D (0x1 << 10)
88 #define CCR_SMOD_FIFO (0x2 << 10)
89 #define CCR_SMOD_EOBFIFO (0x3 << 10)
90 #define CCR_MDIR_DEC (1<<9)
91 #define CCR_MSEL_B (1<<8)
92 #define CCR_DSIZ_32 (0x0 << 6)
93 #define CCR_DSIZ_8 (0x1 << 6)
94 #define CCR_DSIZ_16 (0x2 << 6)
95 #define CCR_SSIZ_32 (0x0 << 4)
96 #define CCR_SSIZ_8 (0x1 << 4)
97 #define CCR_SSIZ_16 (0x2 << 4)
98 #define CCR_REN (1<<3)
99 #define CCR_RPT (1<<2)
100 #define CCR_FRC (1<<1)
101 #define CCR_CEN (1<<0)
102 #define RTOR_EN (1<<15)
103 #define RTOR_CLK (1<<14)
104 #define RTOR_PSC (1<<13)
106 enum imxdma_prep_type {
108 IMXDMA_DESC_INTERLEAVED,
109 IMXDMA_DESC_SLAVE_SG,
113 struct imx_dma_2d_config {
121 struct list_head node;
122 struct dma_async_tx_descriptor desc;
123 enum dma_status status;
127 enum dma_transfer_direction direction;
128 enum imxdma_prep_type type;
129 /* For memcpy and interleaved */
130 unsigned int config_port;
131 unsigned int config_mem;
132 /* For interleaved transfers */
136 /* For slave sg and cyclic */
137 struct scatterlist *sg;
138 unsigned int sgcount;
141 struct imxdma_channel {
143 struct timer_list watchdog;
144 struct imxdma_engine *imxdma;
145 unsigned int channel;
147 struct tasklet_struct dma_tasklet;
148 struct list_head ld_free;
149 struct list_head ld_queue;
150 struct list_head ld_active;
152 enum dma_slave_buswidth word_size;
153 dma_addr_t per_address;
155 struct dma_chan chan;
156 struct dma_async_tx_descriptor desc;
157 enum dma_status status;
159 struct scatterlist *sg_list;
165 struct dma_slave_config config;
174 struct imxdma_engine {
176 struct device_dma_parameters dma_parms;
177 struct dma_device dma_device;
182 struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS];
183 struct imxdma_channel channel[IMX_DMA_CHANNELS];
184 enum imx_dma_type devtype;
186 unsigned int irq_err;
190 struct imxdma_filter_data {
191 struct imxdma_engine *imxdma;
195 static const struct platform_device_id imx_dma_devtype[] = {
198 .driver_data = IMX1_DMA,
201 .driver_data = IMX21_DMA,
204 .driver_data = IMX27_DMA,
209 MODULE_DEVICE_TABLE(platform, imx_dma_devtype);
211 static const struct of_device_id imx_dma_of_dev_id[] = {
213 .compatible = "fsl,imx1-dma",
214 .data = &imx_dma_devtype[IMX1_DMA],
216 .compatible = "fsl,imx21-dma",
217 .data = &imx_dma_devtype[IMX21_DMA],
219 .compatible = "fsl,imx27-dma",
220 .data = &imx_dma_devtype[IMX27_DMA],
225 MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id);
227 static inline int is_imx1_dma(struct imxdma_engine *imxdma)
229 return imxdma->devtype == IMX1_DMA;
232 static inline int is_imx27_dma(struct imxdma_engine *imxdma)
234 return imxdma->devtype == IMX27_DMA;
237 static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
239 return container_of(chan, struct imxdma_channel, chan);
242 static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
244 struct imxdma_desc *desc;
246 if (!list_empty(&imxdmac->ld_active)) {
247 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
249 if (desc->type == IMXDMA_DESC_CYCLIC)
257 static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
260 __raw_writel(val, imxdma->base + offset);
263 static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
265 return __raw_readl(imxdma->base + offset);
268 static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
270 struct imxdma_engine *imxdma = imxdmac->imxdma;
272 if (is_imx27_dma(imxdma))
273 return imxdmac->hw_chaining;
279 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
281 static inline void imxdma_sg_next(struct imxdma_desc *d)
283 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
284 struct imxdma_engine *imxdma = imxdmac->imxdma;
285 struct scatterlist *sg = d->sg;
288 now = min_t(size_t, d->len, sg_dma_len(sg));
289 if (d->len != IMX_DMA_LENGTH_LOOP)
292 if (d->direction == DMA_DEV_TO_MEM)
293 imx_dmav1_writel(imxdma, sg->dma_address,
294 DMA_DAR(imxdmac->channel));
296 imx_dmav1_writel(imxdma, sg->dma_address,
297 DMA_SAR(imxdmac->channel));
299 imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
301 dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
302 "size 0x%08x\n", __func__, imxdmac->channel,
303 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
304 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
305 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
308 static void imxdma_enable_hw(struct imxdma_desc *d)
310 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
311 struct imxdma_engine *imxdma = imxdmac->imxdma;
312 int channel = imxdmac->channel;
315 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
317 local_irq_save(flags);
319 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
320 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
321 ~(1 << channel), DMA_DIMR);
322 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
323 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
325 if (!is_imx1_dma(imxdma) &&
326 d->sg && imxdma_hw_chain(imxdmac)) {
327 d->sg = sg_next(d->sg);
331 tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
332 imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
337 local_irq_restore(flags);
340 static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
342 struct imxdma_engine *imxdma = imxdmac->imxdma;
343 int channel = imxdmac->channel;
346 dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
348 if (imxdma_hw_chain(imxdmac))
349 del_timer(&imxdmac->watchdog);
351 local_irq_save(flags);
352 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
353 (1 << channel), DMA_DIMR);
354 imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
355 ~CCR_CEN, DMA_CCR(channel));
356 imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
357 local_irq_restore(flags);
360 static void imxdma_watchdog(struct timer_list *t)
362 struct imxdma_channel *imxdmac = from_timer(imxdmac, t, watchdog);
363 struct imxdma_engine *imxdma = imxdmac->imxdma;
364 int channel = imxdmac->channel;
366 imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
368 /* Tasklet watchdog error handler */
369 tasklet_schedule(&imxdmac->dma_tasklet);
370 dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
374 static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
376 struct imxdma_engine *imxdma = dev_id;
377 unsigned int err_mask;
381 disr = imx_dmav1_readl(imxdma, DMA_DISR);
383 err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
384 imx_dmav1_readl(imxdma, DMA_DRTOSR) |
385 imx_dmav1_readl(imxdma, DMA_DSESR) |
386 imx_dmav1_readl(imxdma, DMA_DBOSR);
391 imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
393 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
394 if (!(err_mask & (1 << i)))
398 if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
399 imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
400 errcode |= IMX_DMA_ERR_BURST;
402 if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
403 imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
404 errcode |= IMX_DMA_ERR_REQUEST;
406 if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
407 imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
408 errcode |= IMX_DMA_ERR_TRANSFER;
410 if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
411 imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
412 errcode |= IMX_DMA_ERR_BUFFER;
414 /* Tasklet error handler */
415 tasklet_schedule(&imxdma->channel[i].dma_tasklet);
417 dev_warn(imxdma->dev,
418 "DMA timeout on channel %d -%s%s%s%s\n", i,
419 errcode & IMX_DMA_ERR_BURST ? " burst" : "",
420 errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
421 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
422 errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
427 static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
429 struct imxdma_engine *imxdma = imxdmac->imxdma;
430 int chno = imxdmac->channel;
431 struct imxdma_desc *desc;
434 spin_lock_irqsave(&imxdma->lock, flags);
435 if (list_empty(&imxdmac->ld_active)) {
436 spin_unlock_irqrestore(&imxdma->lock, flags);
440 desc = list_first_entry(&imxdmac->ld_active,
443 spin_unlock_irqrestore(&imxdma->lock, flags);
447 desc->sg = sg_next(desc->sg);
450 imxdma_sg_next(desc);
452 tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
454 if (imxdma_hw_chain(imxdmac)) {
455 /* FIXME: The timeout should probably be
458 mod_timer(&imxdmac->watchdog,
459 jiffies + msecs_to_jiffies(500));
461 tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
462 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
464 imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
469 imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
471 if (imxdma_chan_is_doing_cyclic(imxdmac))
472 /* Tasklet progression */
473 tasklet_schedule(&imxdmac->dma_tasklet);
478 if (imxdma_hw_chain(imxdmac)) {
479 del_timer(&imxdmac->watchdog);
485 imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
487 tasklet_schedule(&imxdmac->dma_tasklet);
490 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
492 struct imxdma_engine *imxdma = dev_id;
495 if (!is_imx1_dma(imxdma))
496 imxdma_err_handler(irq, dev_id);
498 disr = imx_dmav1_readl(imxdma, DMA_DISR);
500 dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
502 imx_dmav1_writel(imxdma, disr, DMA_DISR);
503 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
505 dma_irq_handle_channel(&imxdma->channel[i]);
511 static int imxdma_xfer_desc(struct imxdma_desc *d)
513 struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
514 struct imxdma_engine *imxdma = imxdmac->imxdma;
518 /* Configure and enable */
520 case IMXDMA_DESC_INTERLEAVED:
521 /* Try to get a free 2D slot */
522 for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
523 if ((imxdma->slots_2d[i].count > 0) &&
524 ((imxdma->slots_2d[i].xsr != d->x) ||
525 (imxdma->slots_2d[i].ysr != d->y) ||
526 (imxdma->slots_2d[i].wsr != d->w)))
534 imxdma->slots_2d[slot].xsr = d->x;
535 imxdma->slots_2d[slot].ysr = d->y;
536 imxdma->slots_2d[slot].wsr = d->w;
537 imxdma->slots_2d[slot].count++;
539 imxdmac->slot_2d = slot;
540 imxdmac->enabled_2d = true;
542 if (slot == IMX_DMA_2D_SLOT_A) {
543 d->config_mem &= ~CCR_MSEL_B;
544 d->config_port &= ~CCR_MSEL_B;
545 imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
546 imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
547 imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
549 d->config_mem |= CCR_MSEL_B;
550 d->config_port |= CCR_MSEL_B;
551 imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
552 imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
553 imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
556 * We fall-through here intentionally, since a 2D transfer is
557 * similar to MEMCPY just adding the 2D slot configuration.
560 case IMXDMA_DESC_MEMCPY:
561 imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
562 imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
563 imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
564 DMA_CCR(imxdmac->channel));
566 imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
569 "%s channel: %d dest=0x%08llx src=0x%08llx dma_length=%zu\n",
570 __func__, imxdmac->channel,
571 (unsigned long long)d->dest,
572 (unsigned long long)d->src, d->len);
575 /* Cyclic transfer is the same as slave_sg with special sg configuration. */
576 case IMXDMA_DESC_CYCLIC:
577 case IMXDMA_DESC_SLAVE_SG:
578 if (d->direction == DMA_DEV_TO_MEM) {
579 imx_dmav1_writel(imxdma, imxdmac->per_address,
580 DMA_SAR(imxdmac->channel));
581 imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
582 DMA_CCR(imxdmac->channel));
585 "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (dev2mem)\n",
586 __func__, imxdmac->channel,
587 d->sg, d->sgcount, d->len,
588 (unsigned long long)imxdmac->per_address);
589 } else if (d->direction == DMA_MEM_TO_DEV) {
590 imx_dmav1_writel(imxdma, imxdmac->per_address,
591 DMA_DAR(imxdmac->channel));
592 imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
593 DMA_CCR(imxdmac->channel));
596 "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (mem2dev)\n",
597 __func__, imxdmac->channel,
598 d->sg, d->sgcount, d->len,
599 (unsigned long long)imxdmac->per_address);
601 dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
602 __func__, imxdmac->channel);
616 static void imxdma_tasklet(unsigned long data)
618 struct imxdma_channel *imxdmac = (void *)data;
619 struct imxdma_engine *imxdma = imxdmac->imxdma;
620 struct imxdma_desc *desc, *next_desc;
623 spin_lock_irqsave(&imxdma->lock, flags);
625 if (list_empty(&imxdmac->ld_active)) {
626 /* Someone might have called terminate all */
627 spin_unlock_irqrestore(&imxdma->lock, flags);
630 desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
632 /* If we are dealing with a cyclic descriptor, keep it on ld_active
633 * and dont mark the descriptor as complete.
634 * Only in non-cyclic cases it would be marked as complete
636 if (imxdma_chan_is_doing_cyclic(imxdmac))
639 dma_cookie_complete(&desc->desc);
641 /* Free 2D slot if it was an interleaved transfer */
642 if (imxdmac->enabled_2d) {
643 imxdma->slots_2d[imxdmac->slot_2d].count--;
644 imxdmac->enabled_2d = false;
647 list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
649 if (!list_empty(&imxdmac->ld_queue)) {
650 next_desc = list_first_entry(&imxdmac->ld_queue,
651 struct imxdma_desc, node);
652 list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
653 if (imxdma_xfer_desc(next_desc) < 0)
654 dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
655 __func__, imxdmac->channel);
658 spin_unlock_irqrestore(&imxdma->lock, flags);
660 dmaengine_desc_get_callback_invoke(&desc->desc, NULL);
663 static int imxdma_terminate_all(struct dma_chan *chan)
665 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
666 struct imxdma_engine *imxdma = imxdmac->imxdma;
669 imxdma_disable_hw(imxdmac);
671 spin_lock_irqsave(&imxdma->lock, flags);
672 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
673 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
674 spin_unlock_irqrestore(&imxdma->lock, flags);
678 static int imxdma_config_write(struct dma_chan *chan,
679 struct dma_slave_config *dmaengine_cfg,
680 enum dma_transfer_direction direction)
682 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
683 struct imxdma_engine *imxdma = imxdmac->imxdma;
684 unsigned int mode = 0;
686 if (direction == DMA_DEV_TO_MEM) {
687 imxdmac->per_address = dmaengine_cfg->src_addr;
688 imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
689 imxdmac->word_size = dmaengine_cfg->src_addr_width;
691 imxdmac->per_address = dmaengine_cfg->dst_addr;
692 imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
693 imxdmac->word_size = dmaengine_cfg->dst_addr_width;
696 switch (imxdmac->word_size) {
697 case DMA_SLAVE_BUSWIDTH_1_BYTE:
698 mode = IMX_DMA_MEMSIZE_8;
700 case DMA_SLAVE_BUSWIDTH_2_BYTES:
701 mode = IMX_DMA_MEMSIZE_16;
704 case DMA_SLAVE_BUSWIDTH_4_BYTES:
705 mode = IMX_DMA_MEMSIZE_32;
709 imxdmac->hw_chaining = 0;
711 imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
712 ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
714 imxdmac->ccr_to_device =
715 (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
716 ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
717 imx_dmav1_writel(imxdma, imxdmac->dma_request,
718 DMA_RSSR(imxdmac->channel));
720 /* Set burst length */
721 imx_dmav1_writel(imxdma, imxdmac->watermark_level *
722 imxdmac->word_size, DMA_BLR(imxdmac->channel));
727 static int imxdma_config(struct dma_chan *chan,
728 struct dma_slave_config *dmaengine_cfg)
730 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
732 memcpy(&imxdmac->config, dmaengine_cfg, sizeof(*dmaengine_cfg));
737 static enum dma_status imxdma_tx_status(struct dma_chan *chan,
739 struct dma_tx_state *txstate)
741 return dma_cookie_status(chan, cookie, txstate);
744 static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
746 struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
747 struct imxdma_engine *imxdma = imxdmac->imxdma;
751 spin_lock_irqsave(&imxdma->lock, flags);
752 list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
753 cookie = dma_cookie_assign(tx);
754 spin_unlock_irqrestore(&imxdma->lock, flags);
759 static int imxdma_alloc_chan_resources(struct dma_chan *chan)
761 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
762 struct imx_dma_data *data = chan->private;
765 imxdmac->dma_request = data->dma_request;
767 while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
768 struct imxdma_desc *desc;
770 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
773 memset(&desc->desc, 0, sizeof(struct dma_async_tx_descriptor));
774 dma_async_tx_descriptor_init(&desc->desc, chan);
775 desc->desc.tx_submit = imxdma_tx_submit;
776 /* txd.flags will be overwritten in prep funcs */
777 desc->desc.flags = DMA_CTRL_ACK;
778 desc->status = DMA_COMPLETE;
780 list_add_tail(&desc->node, &imxdmac->ld_free);
781 imxdmac->descs_allocated++;
784 if (!imxdmac->descs_allocated)
787 return imxdmac->descs_allocated;
790 static void imxdma_free_chan_resources(struct dma_chan *chan)
792 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
793 struct imxdma_engine *imxdma = imxdmac->imxdma;
794 struct imxdma_desc *desc, *_desc;
797 spin_lock_irqsave(&imxdma->lock, flags);
799 imxdma_disable_hw(imxdmac);
800 list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
801 list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
803 spin_unlock_irqrestore(&imxdma->lock, flags);
805 list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
807 imxdmac->descs_allocated--;
809 INIT_LIST_HEAD(&imxdmac->ld_free);
811 kfree(imxdmac->sg_list);
812 imxdmac->sg_list = NULL;
815 static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
816 struct dma_chan *chan, struct scatterlist *sgl,
817 unsigned int sg_len, enum dma_transfer_direction direction,
818 unsigned long flags, void *context)
820 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
821 struct scatterlist *sg;
822 int i, dma_length = 0;
823 struct imxdma_desc *desc;
825 if (list_empty(&imxdmac->ld_free) ||
826 imxdma_chan_is_doing_cyclic(imxdmac))
829 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
831 for_each_sg(sgl, sg, sg_len, i) {
832 dma_length += sg_dma_len(sg);
835 imxdma_config_write(chan, &imxdmac->config, direction);
837 switch (imxdmac->word_size) {
838 case DMA_SLAVE_BUSWIDTH_4_BYTES:
839 if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
842 case DMA_SLAVE_BUSWIDTH_2_BYTES:
843 if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
846 case DMA_SLAVE_BUSWIDTH_1_BYTE:
852 desc->type = IMXDMA_DESC_SLAVE_SG;
854 desc->sgcount = sg_len;
855 desc->len = dma_length;
856 desc->direction = direction;
857 if (direction == DMA_DEV_TO_MEM) {
858 desc->src = imxdmac->per_address;
860 desc->dest = imxdmac->per_address;
862 desc->desc.callback = NULL;
863 desc->desc.callback_param = NULL;
868 static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
869 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
870 size_t period_len, enum dma_transfer_direction direction,
873 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
874 struct imxdma_engine *imxdma = imxdmac->imxdma;
875 struct imxdma_desc *desc;
877 unsigned int periods = buf_len / period_len;
879 dev_dbg(imxdma->dev, "%s channel: %d buf_len=%zu period_len=%zu\n",
880 __func__, imxdmac->channel, buf_len, period_len);
882 if (list_empty(&imxdmac->ld_free) ||
883 imxdma_chan_is_doing_cyclic(imxdmac))
886 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
888 kfree(imxdmac->sg_list);
890 imxdmac->sg_list = kcalloc(periods + 1,
891 sizeof(struct scatterlist), GFP_ATOMIC);
892 if (!imxdmac->sg_list)
895 sg_init_table(imxdmac->sg_list, periods);
897 for (i = 0; i < periods; i++) {
898 sg_assign_page(&imxdmac->sg_list[i], NULL);
899 imxdmac->sg_list[i].offset = 0;
900 imxdmac->sg_list[i].dma_address = dma_addr;
901 sg_dma_len(&imxdmac->sg_list[i]) = period_len;
902 dma_addr += period_len;
906 sg_chain(imxdmac->sg_list, periods + 1, imxdmac->sg_list);
908 desc->type = IMXDMA_DESC_CYCLIC;
909 desc->sg = imxdmac->sg_list;
910 desc->sgcount = periods;
911 desc->len = IMX_DMA_LENGTH_LOOP;
912 desc->direction = direction;
913 if (direction == DMA_DEV_TO_MEM) {
914 desc->src = imxdmac->per_address;
916 desc->dest = imxdmac->per_address;
918 desc->desc.callback = NULL;
919 desc->desc.callback_param = NULL;
921 imxdma_config_write(chan, &imxdmac->config, direction);
926 static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
927 struct dma_chan *chan, dma_addr_t dest,
928 dma_addr_t src, size_t len, unsigned long flags)
930 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
931 struct imxdma_engine *imxdma = imxdmac->imxdma;
932 struct imxdma_desc *desc;
934 dev_dbg(imxdma->dev, "%s channel: %d src=0x%llx dst=0x%llx len=%zu\n",
935 __func__, imxdmac->channel, (unsigned long long)src,
936 (unsigned long long)dest, len);
938 if (list_empty(&imxdmac->ld_free) ||
939 imxdma_chan_is_doing_cyclic(imxdmac))
942 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
944 desc->type = IMXDMA_DESC_MEMCPY;
948 desc->direction = DMA_MEM_TO_MEM;
949 desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
950 desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
951 desc->desc.callback = NULL;
952 desc->desc.callback_param = NULL;
957 static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
958 struct dma_chan *chan, struct dma_interleaved_template *xt,
961 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
962 struct imxdma_engine *imxdma = imxdmac->imxdma;
963 struct imxdma_desc *desc;
965 dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%llx dst_start=0x%llx\n"
966 " src_sgl=%s dst_sgl=%s numf=%zu frame_size=%zu\n", __func__,
967 imxdmac->channel, (unsigned long long)xt->src_start,
968 (unsigned long long) xt->dst_start,
969 xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
970 xt->numf, xt->frame_size);
972 if (list_empty(&imxdmac->ld_free) ||
973 imxdma_chan_is_doing_cyclic(imxdmac))
976 if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
979 desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
981 desc->type = IMXDMA_DESC_INTERLEAVED;
982 desc->src = xt->src_start;
983 desc->dest = xt->dst_start;
984 desc->x = xt->sgl[0].size;
986 desc->w = xt->sgl[0].icg + desc->x;
987 desc->len = desc->x * desc->y;
988 desc->direction = DMA_MEM_TO_MEM;
989 desc->config_port = IMX_DMA_MEMSIZE_32;
990 desc->config_mem = IMX_DMA_MEMSIZE_32;
992 desc->config_mem |= IMX_DMA_TYPE_2D;
994 desc->config_port |= IMX_DMA_TYPE_2D;
995 desc->desc.callback = NULL;
996 desc->desc.callback_param = NULL;
1001 static void imxdma_issue_pending(struct dma_chan *chan)
1003 struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
1004 struct imxdma_engine *imxdma = imxdmac->imxdma;
1005 struct imxdma_desc *desc;
1006 unsigned long flags;
1008 spin_lock_irqsave(&imxdma->lock, flags);
1009 if (list_empty(&imxdmac->ld_active) &&
1010 !list_empty(&imxdmac->ld_queue)) {
1011 desc = list_first_entry(&imxdmac->ld_queue,
1012 struct imxdma_desc, node);
1014 if (imxdma_xfer_desc(desc) < 0) {
1015 dev_warn(imxdma->dev,
1016 "%s: channel: %d couldn't issue DMA xfer\n",
1017 __func__, imxdmac->channel);
1019 list_move_tail(imxdmac->ld_queue.next,
1020 &imxdmac->ld_active);
1023 spin_unlock_irqrestore(&imxdma->lock, flags);
1026 static bool imxdma_filter_fn(struct dma_chan *chan, void *param)
1028 struct imxdma_filter_data *fdata = param;
1029 struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan);
1031 if (chan->device->dev != fdata->imxdma->dev)
1034 imxdma_chan->dma_request = fdata->request;
1035 chan->private = NULL;
1040 static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec,
1041 struct of_dma *ofdma)
1043 int count = dma_spec->args_count;
1044 struct imxdma_engine *imxdma = ofdma->of_dma_data;
1045 struct imxdma_filter_data fdata = {
1052 fdata.request = dma_spec->args[0];
1054 return dma_request_channel(imxdma->dma_device.cap_mask,
1055 imxdma_filter_fn, &fdata);
1058 static int __init imxdma_probe(struct platform_device *pdev)
1060 struct imxdma_engine *imxdma;
1061 struct resource *res;
1062 const struct of_device_id *of_id;
1066 of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev);
1068 pdev->id_entry = of_id->data;
1070 imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
1074 imxdma->dev = &pdev->dev;
1075 imxdma->devtype = pdev->id_entry->driver_data;
1077 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1078 imxdma->base = devm_ioremap_resource(&pdev->dev, res);
1079 if (IS_ERR(imxdma->base))
1080 return PTR_ERR(imxdma->base);
1082 irq = platform_get_irq(pdev, 0);
1086 imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
1087 if (IS_ERR(imxdma->dma_ipg))
1088 return PTR_ERR(imxdma->dma_ipg);
1090 imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
1091 if (IS_ERR(imxdma->dma_ahb))
1092 return PTR_ERR(imxdma->dma_ahb);
1094 ret = clk_prepare_enable(imxdma->dma_ipg);
1097 ret = clk_prepare_enable(imxdma->dma_ahb);
1099 goto disable_dma_ipg_clk;
1101 /* reset DMA module */
1102 imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
1104 if (is_imx1_dma(imxdma)) {
1105 ret = devm_request_irq(&pdev->dev, irq,
1106 dma_irq_handler, 0, "DMA", imxdma);
1108 dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
1109 goto disable_dma_ahb_clk;
1113 irq_err = platform_get_irq(pdev, 1);
1116 goto disable_dma_ahb_clk;
1119 ret = devm_request_irq(&pdev->dev, irq_err,
1120 imxdma_err_handler, 0, "DMA", imxdma);
1122 dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
1123 goto disable_dma_ahb_clk;
1125 imxdma->irq_err = irq_err;
1128 /* enable DMA module */
1129 imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
1131 /* clear all interrupts */
1132 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
1134 /* disable interrupts */
1135 imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
1137 INIT_LIST_HEAD(&imxdma->dma_device.channels);
1139 dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
1140 dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
1141 dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
1142 dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
1144 /* Initialize 2D global parameters */
1145 for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
1146 imxdma->slots_2d[i].count = 0;
1148 spin_lock_init(&imxdma->lock);
1150 /* Initialize channel parameters */
1151 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1152 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1154 if (!is_imx1_dma(imxdma)) {
1155 ret = devm_request_irq(&pdev->dev, irq + i,
1156 dma_irq_handler, 0, "DMA", imxdma);
1158 dev_warn(imxdma->dev, "Can't register IRQ %d "
1159 "for DMA channel %d\n",
1161 goto disable_dma_ahb_clk;
1164 imxdmac->irq = irq + i;
1165 timer_setup(&imxdmac->watchdog, imxdma_watchdog, 0);
1168 imxdmac->imxdma = imxdma;
1170 INIT_LIST_HEAD(&imxdmac->ld_queue);
1171 INIT_LIST_HEAD(&imxdmac->ld_free);
1172 INIT_LIST_HEAD(&imxdmac->ld_active);
1174 tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
1175 (unsigned long)imxdmac);
1176 imxdmac->chan.device = &imxdma->dma_device;
1177 dma_cookie_init(&imxdmac->chan);
1178 imxdmac->channel = i;
1180 /* Add the channel to the DMAC list */
1181 list_add_tail(&imxdmac->chan.device_node,
1182 &imxdma->dma_device.channels);
1185 imxdma->dma_device.dev = &pdev->dev;
1187 imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
1188 imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
1189 imxdma->dma_device.device_tx_status = imxdma_tx_status;
1190 imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
1191 imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
1192 imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
1193 imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
1194 imxdma->dma_device.device_config = imxdma_config;
1195 imxdma->dma_device.device_terminate_all = imxdma_terminate_all;
1196 imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
1198 platform_set_drvdata(pdev, imxdma);
1200 imxdma->dma_device.copy_align = DMAENGINE_ALIGN_4_BYTES;
1201 imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
1202 dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
1204 ret = dma_async_device_register(&imxdma->dma_device);
1206 dev_err(&pdev->dev, "unable to register\n");
1207 goto disable_dma_ahb_clk;
1210 if (pdev->dev.of_node) {
1211 ret = of_dma_controller_register(pdev->dev.of_node,
1212 imxdma_xlate, imxdma);
1214 dev_err(&pdev->dev, "unable to register of_dma_controller\n");
1215 goto err_of_dma_controller;
1221 err_of_dma_controller:
1222 dma_async_device_unregister(&imxdma->dma_device);
1223 disable_dma_ahb_clk:
1224 clk_disable_unprepare(imxdma->dma_ahb);
1225 disable_dma_ipg_clk:
1226 clk_disable_unprepare(imxdma->dma_ipg);
1230 static void imxdma_free_irq(struct platform_device *pdev, struct imxdma_engine *imxdma)
1234 if (is_imx1_dma(imxdma)) {
1235 disable_irq(imxdma->irq);
1236 disable_irq(imxdma->irq_err);
1239 for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1240 struct imxdma_channel *imxdmac = &imxdma->channel[i];
1242 if (!is_imx1_dma(imxdma))
1243 disable_irq(imxdmac->irq);
1245 tasklet_kill(&imxdmac->dma_tasklet);
1249 static int imxdma_remove(struct platform_device *pdev)
1251 struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
1253 imxdma_free_irq(pdev, imxdma);
1255 dma_async_device_unregister(&imxdma->dma_device);
1257 if (pdev->dev.of_node)
1258 of_dma_controller_free(pdev->dev.of_node);
1260 clk_disable_unprepare(imxdma->dma_ipg);
1261 clk_disable_unprepare(imxdma->dma_ahb);
1266 static struct platform_driver imxdma_driver = {
1269 .of_match_table = imx_dma_of_dev_id,
1271 .id_table = imx_dma_devtype,
1272 .remove = imxdma_remove,
1275 static int __init imxdma_module_init(void)
1277 return platform_driver_probe(&imxdma_driver, imxdma_probe);
1279 subsys_initcall(imxdma_module_init);
1281 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1282 MODULE_DESCRIPTION("i.MX dma driver");
1283 MODULE_LICENSE("GPL");