2 * Driver for the Cirrus Logic EP93xx DMA Controller
4 * Copyright (C) 2011 Mika Westerberg
6 * DMA M2P implementation is based on the original
7 * arch/arm/mach-ep93xx/dma-m2p.c which has following copyrights:
9 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
10 * Copyright (C) 2006 Applied Data Systems
11 * Copyright (C) 2009 Ryan Mallon <rmallon@gmail.com>
13 * This driver is based on dw_dmac and amba-pl08x drivers.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
21 #include <linux/clk.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/dmaengine.h>
25 #include <linux/module.h>
26 #include <linux/mod_devicetable.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
30 #include <linux/platform_data/dma-ep93xx.h>
32 #include "dmaengine.h"
35 #define M2P_CONTROL 0x0000
36 #define M2P_CONTROL_STALLINT BIT(0)
37 #define M2P_CONTROL_NFBINT BIT(1)
38 #define M2P_CONTROL_CH_ERROR_INT BIT(3)
39 #define M2P_CONTROL_ENABLE BIT(4)
40 #define M2P_CONTROL_ICE BIT(6)
42 #define M2P_INTERRUPT 0x0004
43 #define M2P_INTERRUPT_STALL BIT(0)
44 #define M2P_INTERRUPT_NFB BIT(1)
45 #define M2P_INTERRUPT_ERROR BIT(3)
47 #define M2P_PPALLOC 0x0008
48 #define M2P_STATUS 0x000c
50 #define M2P_MAXCNT0 0x0020
51 #define M2P_BASE0 0x0024
52 #define M2P_MAXCNT1 0x0030
53 #define M2P_BASE1 0x0034
55 #define M2P_STATE_IDLE 0
56 #define M2P_STATE_STALL 1
57 #define M2P_STATE_ON 2
58 #define M2P_STATE_NEXT 3
61 #define M2M_CONTROL 0x0000
62 #define M2M_CONTROL_DONEINT BIT(2)
63 #define M2M_CONTROL_ENABLE BIT(3)
64 #define M2M_CONTROL_START BIT(4)
65 #define M2M_CONTROL_DAH BIT(11)
66 #define M2M_CONTROL_SAH BIT(12)
67 #define M2M_CONTROL_PW_SHIFT 9
68 #define M2M_CONTROL_PW_8 (0 << M2M_CONTROL_PW_SHIFT)
69 #define M2M_CONTROL_PW_16 (1 << M2M_CONTROL_PW_SHIFT)
70 #define M2M_CONTROL_PW_32 (2 << M2M_CONTROL_PW_SHIFT)
71 #define M2M_CONTROL_PW_MASK (3 << M2M_CONTROL_PW_SHIFT)
72 #define M2M_CONTROL_TM_SHIFT 13
73 #define M2M_CONTROL_TM_TX (1 << M2M_CONTROL_TM_SHIFT)
74 #define M2M_CONTROL_TM_RX (2 << M2M_CONTROL_TM_SHIFT)
75 #define M2M_CONTROL_NFBINT BIT(21)
76 #define M2M_CONTROL_RSS_SHIFT 22
77 #define M2M_CONTROL_RSS_SSPRX (1 << M2M_CONTROL_RSS_SHIFT)
78 #define M2M_CONTROL_RSS_SSPTX (2 << M2M_CONTROL_RSS_SHIFT)
79 #define M2M_CONTROL_RSS_IDE (3 << M2M_CONTROL_RSS_SHIFT)
80 #define M2M_CONTROL_NO_HDSK BIT(24)
81 #define M2M_CONTROL_PWSC_SHIFT 25
83 #define M2M_INTERRUPT 0x0004
84 #define M2M_INTERRUPT_MASK 6
86 #define M2M_STATUS 0x000c
87 #define M2M_STATUS_CTL_SHIFT 1
88 #define M2M_STATUS_CTL_IDLE (0 << M2M_STATUS_CTL_SHIFT)
89 #define M2M_STATUS_CTL_STALL (1 << M2M_STATUS_CTL_SHIFT)
90 #define M2M_STATUS_CTL_MEMRD (2 << M2M_STATUS_CTL_SHIFT)
91 #define M2M_STATUS_CTL_MEMWR (3 << M2M_STATUS_CTL_SHIFT)
92 #define M2M_STATUS_CTL_BWCWAIT (4 << M2M_STATUS_CTL_SHIFT)
93 #define M2M_STATUS_CTL_MASK (7 << M2M_STATUS_CTL_SHIFT)
94 #define M2M_STATUS_BUF_SHIFT 4
95 #define M2M_STATUS_BUF_NO (0 << M2M_STATUS_BUF_SHIFT)
96 #define M2M_STATUS_BUF_ON (1 << M2M_STATUS_BUF_SHIFT)
97 #define M2M_STATUS_BUF_NEXT (2 << M2M_STATUS_BUF_SHIFT)
98 #define M2M_STATUS_BUF_MASK (3 << M2M_STATUS_BUF_SHIFT)
99 #define M2M_STATUS_DONE BIT(6)
101 #define M2M_BCR0 0x0010
102 #define M2M_BCR1 0x0014
103 #define M2M_SAR_BASE0 0x0018
104 #define M2M_SAR_BASE1 0x001c
105 #define M2M_DAR_BASE0 0x002c
106 #define M2M_DAR_BASE1 0x0030
108 #define DMA_MAX_CHAN_BYTES 0xffff
109 #define DMA_MAX_CHAN_DESCRIPTORS 32
111 struct ep93xx_dma_engine;
114 * struct ep93xx_dma_desc - EP93xx specific transaction descriptor
115 * @src_addr: source address of the transaction
116 * @dst_addr: destination address of the transaction
117 * @size: size of the transaction (in bytes)
118 * @complete: this descriptor is completed
119 * @txd: dmaengine API descriptor
120 * @tx_list: list of linked descriptors
121 * @node: link used for putting this into a channel queue
123 struct ep93xx_dma_desc {
128 struct dma_async_tx_descriptor txd;
129 struct list_head tx_list;
130 struct list_head node;
134 * struct ep93xx_dma_chan - an EP93xx DMA M2P/M2M channel
135 * @chan: dmaengine API channel
136 * @edma: pointer to to the engine device
137 * @regs: memory mapped registers
138 * @irq: interrupt number of the channel
139 * @clk: clock used by this channel
140 * @tasklet: channel specific tasklet used for callbacks
141 * @lock: lock protecting the fields following
142 * @flags: flags for the channel
143 * @buffer: which buffer to use next (0/1)
144 * @active: flattened chain of descriptors currently being processed
145 * @queue: pending descriptors which are handled next
146 * @free_list: list of free descriptors which can be used
147 * @runtime_addr: physical address currently used as dest/src (M2M only). This
148 * is set via .device_config before slave operation is
150 * @runtime_ctrl: M2M runtime values for the control register.
152 * As EP93xx DMA controller doesn't support real chained DMA descriptors we
153 * will have slightly different scheme here: @active points to a head of
154 * flattened DMA descriptor chain.
156 * @queue holds pending transactions. These are linked through the first
157 * descriptor in the chain. When a descriptor is moved to the @active queue,
158 * the first and chained descriptors are flattened into a single list.
160 * @chan.private holds pointer to &struct ep93xx_dma_data which contains
161 * necessary channel configuration information. For memcpy channels this must
164 struct ep93xx_dma_chan {
165 struct dma_chan chan;
166 const struct ep93xx_dma_engine *edma;
170 struct tasklet_struct tasklet;
171 /* protects the fields following */
174 /* Channel is configured for cyclic transfers */
175 #define EP93XX_DMA_IS_CYCLIC 0
178 struct list_head active;
179 struct list_head queue;
180 struct list_head free_list;
186 * struct ep93xx_dma_engine - the EP93xx DMA engine instance
187 * @dma_dev: holds the dmaengine device
188 * @m2m: is this an M2M or M2P device
189 * @hw_setup: method which sets the channel up for operation
190 * @hw_shutdown: shuts the channel down and flushes whatever is left
191 * @hw_submit: pushes active descriptor(s) to the hardware
192 * @hw_interrupt: handle the interrupt
193 * @num_channels: number of channels for this instance
194 * @channels: array of channels
196 * There is one instance of this struct for the M2P channels and one for the
197 * M2M channels. hw_xxx() methods are used to perform operations which are
198 * different on M2M and M2P channels. These methods are called with channel
199 * lock held and interrupts disabled so they cannot sleep.
201 struct ep93xx_dma_engine {
202 struct dma_device dma_dev;
204 int (*hw_setup)(struct ep93xx_dma_chan *);
205 void (*hw_synchronize)(struct ep93xx_dma_chan *);
206 void (*hw_shutdown)(struct ep93xx_dma_chan *);
207 void (*hw_submit)(struct ep93xx_dma_chan *);
208 int (*hw_interrupt)(struct ep93xx_dma_chan *);
209 #define INTERRUPT_UNKNOWN 0
210 #define INTERRUPT_DONE 1
211 #define INTERRUPT_NEXT_BUFFER 2
214 struct ep93xx_dma_chan channels[];
217 static inline struct device *chan2dev(struct ep93xx_dma_chan *edmac)
219 return &edmac->chan.dev->device;
222 static struct ep93xx_dma_chan *to_ep93xx_dma_chan(struct dma_chan *chan)
224 return container_of(chan, struct ep93xx_dma_chan, chan);
228 * ep93xx_dma_set_active - set new active descriptor chain
230 * @desc: head of the new active descriptor chain
232 * Sets @desc to be the head of the new active descriptor chain. This is the
233 * chain which is processed next. The active list must be empty before calling
236 * Called with @edmac->lock held and interrupts disabled.
238 static void ep93xx_dma_set_active(struct ep93xx_dma_chan *edmac,
239 struct ep93xx_dma_desc *desc)
241 BUG_ON(!list_empty(&edmac->active));
243 list_add_tail(&desc->node, &edmac->active);
245 /* Flatten the @desc->tx_list chain into @edmac->active list */
246 while (!list_empty(&desc->tx_list)) {
247 struct ep93xx_dma_desc *d = list_first_entry(&desc->tx_list,
248 struct ep93xx_dma_desc, node);
251 * We copy the callback parameters from the first descriptor
252 * to all the chained descriptors. This way we can call the
253 * callback without having to find out the first descriptor in
254 * the chain. Useful for cyclic transfers.
256 d->txd.callback = desc->txd.callback;
257 d->txd.callback_param = desc->txd.callback_param;
259 list_move_tail(&d->node, &edmac->active);
263 /* Called with @edmac->lock held and interrupts disabled */
264 static struct ep93xx_dma_desc *
265 ep93xx_dma_get_active(struct ep93xx_dma_chan *edmac)
267 return list_first_entry_or_null(&edmac->active,
268 struct ep93xx_dma_desc, node);
272 * ep93xx_dma_advance_active - advances to the next active descriptor
275 * Function advances active descriptor to the next in the @edmac->active and
276 * returns %true if we still have descriptors in the chain to process.
277 * Otherwise returns %false.
279 * When the channel is in cyclic mode always returns %true.
281 * Called with @edmac->lock held and interrupts disabled.
283 static bool ep93xx_dma_advance_active(struct ep93xx_dma_chan *edmac)
285 struct ep93xx_dma_desc *desc;
287 list_rotate_left(&edmac->active);
289 if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))
292 desc = ep93xx_dma_get_active(edmac);
297 * If txd.cookie is set it means that we are back in the first
298 * descriptor in the chain and hence done with it.
300 return !desc->txd.cookie;
304 * M2P DMA implementation
307 static void m2p_set_control(struct ep93xx_dma_chan *edmac, u32 control)
309 writel(control, edmac->regs + M2P_CONTROL);
311 * EP93xx User's Guide states that we must perform a dummy read after
312 * write to the control register.
314 readl(edmac->regs + M2P_CONTROL);
317 static int m2p_hw_setup(struct ep93xx_dma_chan *edmac)
319 struct ep93xx_dma_data *data = edmac->chan.private;
322 writel(data->port & 0xf, edmac->regs + M2P_PPALLOC);
324 control = M2P_CONTROL_CH_ERROR_INT | M2P_CONTROL_ICE
325 | M2P_CONTROL_ENABLE;
326 m2p_set_control(edmac, control);
333 static inline u32 m2p_channel_state(struct ep93xx_dma_chan *edmac)
335 return (readl(edmac->regs + M2P_STATUS) >> 4) & 0x3;
338 static void m2p_hw_synchronize(struct ep93xx_dma_chan *edmac)
343 spin_lock_irqsave(&edmac->lock, flags);
344 control = readl(edmac->regs + M2P_CONTROL);
345 control &= ~(M2P_CONTROL_STALLINT | M2P_CONTROL_NFBINT);
346 m2p_set_control(edmac, control);
347 spin_unlock_irqrestore(&edmac->lock, flags);
349 while (m2p_channel_state(edmac) >= M2P_STATE_ON)
353 static void m2p_hw_shutdown(struct ep93xx_dma_chan *edmac)
355 m2p_set_control(edmac, 0);
357 while (m2p_channel_state(edmac) != M2P_STATE_IDLE)
358 dev_warn(chan2dev(edmac), "M2P: Not yet IDLE\n");
361 static void m2p_fill_desc(struct ep93xx_dma_chan *edmac)
363 struct ep93xx_dma_desc *desc;
366 desc = ep93xx_dma_get_active(edmac);
368 dev_warn(chan2dev(edmac), "M2P: empty descriptor list\n");
372 if (ep93xx_dma_chan_direction(&edmac->chan) == DMA_MEM_TO_DEV)
373 bus_addr = desc->src_addr;
375 bus_addr = desc->dst_addr;
377 if (edmac->buffer == 0) {
378 writel(desc->size, edmac->regs + M2P_MAXCNT0);
379 writel(bus_addr, edmac->regs + M2P_BASE0);
381 writel(desc->size, edmac->regs + M2P_MAXCNT1);
382 writel(bus_addr, edmac->regs + M2P_BASE1);
388 static void m2p_hw_submit(struct ep93xx_dma_chan *edmac)
390 u32 control = readl(edmac->regs + M2P_CONTROL);
392 m2p_fill_desc(edmac);
393 control |= M2P_CONTROL_STALLINT;
395 if (ep93xx_dma_advance_active(edmac)) {
396 m2p_fill_desc(edmac);
397 control |= M2P_CONTROL_NFBINT;
400 m2p_set_control(edmac, control);
403 static int m2p_hw_interrupt(struct ep93xx_dma_chan *edmac)
405 u32 irq_status = readl(edmac->regs + M2P_INTERRUPT);
408 if (irq_status & M2P_INTERRUPT_ERROR) {
409 struct ep93xx_dma_desc *desc = ep93xx_dma_get_active(edmac);
411 /* Clear the error interrupt */
412 writel(1, edmac->regs + M2P_INTERRUPT);
415 * It seems that there is no easy way of reporting errors back
416 * to client so we just report the error here and continue as
419 * Revisit this when there is a mechanism to report back the
422 dev_err(chan2dev(edmac),
423 "DMA transfer failed! Details:\n"
425 "\tsrc_addr : 0x%08x\n"
426 "\tdst_addr : 0x%08x\n"
428 desc->txd.cookie, desc->src_addr, desc->dst_addr,
433 * Even latest E2 silicon revision sometimes assert STALL interrupt
434 * instead of NFB. Therefore we treat them equally, basing on the
435 * amount of data we still have to transfer.
437 if (!(irq_status & (M2P_INTERRUPT_STALL | M2P_INTERRUPT_NFB)))
438 return INTERRUPT_UNKNOWN;
440 if (ep93xx_dma_advance_active(edmac)) {
441 m2p_fill_desc(edmac);
442 return INTERRUPT_NEXT_BUFFER;
445 /* Disable interrupts */
446 control = readl(edmac->regs + M2P_CONTROL);
447 control &= ~(M2P_CONTROL_STALLINT | M2P_CONTROL_NFBINT);
448 m2p_set_control(edmac, control);
450 return INTERRUPT_DONE;
454 * M2M DMA implementation
457 static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)
459 const struct ep93xx_dma_data *data = edmac->chan.private;
463 /* This is memcpy channel, nothing to configure */
464 writel(control, edmac->regs + M2M_CONTROL);
468 switch (data->port) {
471 * This was found via experimenting - anything less than 5
472 * causes the channel to perform only a partial transfer which
473 * leads to problems since we don't get DONE interrupt then.
475 control = (5 << M2M_CONTROL_PWSC_SHIFT);
476 control |= M2M_CONTROL_NO_HDSK;
478 if (data->direction == DMA_MEM_TO_DEV) {
479 control |= M2M_CONTROL_DAH;
480 control |= M2M_CONTROL_TM_TX;
481 control |= M2M_CONTROL_RSS_SSPTX;
483 control |= M2M_CONTROL_SAH;
484 control |= M2M_CONTROL_TM_RX;
485 control |= M2M_CONTROL_RSS_SSPRX;
491 * This IDE part is totally untested. Values below are taken
492 * from the EP93xx Users's Guide and might not be correct.
494 if (data->direction == DMA_MEM_TO_DEV) {
495 /* Worst case from the UG */
496 control = (3 << M2M_CONTROL_PWSC_SHIFT);
497 control |= M2M_CONTROL_DAH;
498 control |= M2M_CONTROL_TM_TX;
500 control = (2 << M2M_CONTROL_PWSC_SHIFT);
501 control |= M2M_CONTROL_SAH;
502 control |= M2M_CONTROL_TM_RX;
505 control |= M2M_CONTROL_NO_HDSK;
506 control |= M2M_CONTROL_RSS_IDE;
507 control |= M2M_CONTROL_PW_16;
514 writel(control, edmac->regs + M2M_CONTROL);
518 static void m2m_hw_shutdown(struct ep93xx_dma_chan *edmac)
520 /* Just disable the channel */
521 writel(0, edmac->regs + M2M_CONTROL);
524 static void m2m_fill_desc(struct ep93xx_dma_chan *edmac)
526 struct ep93xx_dma_desc *desc;
528 desc = ep93xx_dma_get_active(edmac);
530 dev_warn(chan2dev(edmac), "M2M: empty descriptor list\n");
534 if (edmac->buffer == 0) {
535 writel(desc->src_addr, edmac->regs + M2M_SAR_BASE0);
536 writel(desc->dst_addr, edmac->regs + M2M_DAR_BASE0);
537 writel(desc->size, edmac->regs + M2M_BCR0);
539 writel(desc->src_addr, edmac->regs + M2M_SAR_BASE1);
540 writel(desc->dst_addr, edmac->regs + M2M_DAR_BASE1);
541 writel(desc->size, edmac->regs + M2M_BCR1);
547 static void m2m_hw_submit(struct ep93xx_dma_chan *edmac)
549 struct ep93xx_dma_data *data = edmac->chan.private;
550 u32 control = readl(edmac->regs + M2M_CONTROL);
553 * Since we allow clients to configure PW (peripheral width) we always
554 * clear PW bits here and then set them according what is given in
555 * the runtime configuration.
557 control &= ~M2M_CONTROL_PW_MASK;
558 control |= edmac->runtime_ctrl;
560 m2m_fill_desc(edmac);
561 control |= M2M_CONTROL_DONEINT;
563 if (ep93xx_dma_advance_active(edmac)) {
564 m2m_fill_desc(edmac);
565 control |= M2M_CONTROL_NFBINT;
569 * Now we can finally enable the channel. For M2M channel this must be
570 * done _after_ the BCRx registers are programmed.
572 control |= M2M_CONTROL_ENABLE;
573 writel(control, edmac->regs + M2M_CONTROL);
577 * For memcpy channels the software trigger must be asserted
578 * in order to start the memcpy operation.
580 control |= M2M_CONTROL_START;
581 writel(control, edmac->regs + M2M_CONTROL);
586 * According to EP93xx User's Guide, we should receive DONE interrupt when all
587 * M2M DMA controller transactions complete normally. This is not always the
588 * case - sometimes EP93xx M2M DMA asserts DONE interrupt when the DMA channel
589 * is still running (channel Buffer FSM in DMA_BUF_ON state, and channel
590 * Control FSM in DMA_MEM_RD state, observed at least in IDE-DMA operation).
591 * In effect, disabling the channel when only DONE bit is set could stop
592 * currently running DMA transfer. To avoid this, we use Buffer FSM and
593 * Control FSM to check current state of DMA channel.
595 static int m2m_hw_interrupt(struct ep93xx_dma_chan *edmac)
597 u32 status = readl(edmac->regs + M2M_STATUS);
598 u32 ctl_fsm = status & M2M_STATUS_CTL_MASK;
599 u32 buf_fsm = status & M2M_STATUS_BUF_MASK;
600 bool done = status & M2M_STATUS_DONE;
603 struct ep93xx_dma_desc *desc;
605 /* Accept only DONE and NFB interrupts */
606 if (!(readl(edmac->regs + M2M_INTERRUPT) & M2M_INTERRUPT_MASK))
607 return INTERRUPT_UNKNOWN;
610 /* Clear the DONE bit */
611 writel(0, edmac->regs + M2M_INTERRUPT);
615 * Check whether we are done with descriptors or not. This, together
616 * with DMA channel state, determines action to take in interrupt.
618 desc = ep93xx_dma_get_active(edmac);
619 last_done = !desc || desc->txd.cookie;
622 * Use M2M DMA Buffer FSM and Control FSM to check current state of
623 * DMA channel. Using DONE and NFB bits from channel status register
624 * or bits from channel interrupt register is not reliable.
627 (buf_fsm == M2M_STATUS_BUF_NO ||
628 buf_fsm == M2M_STATUS_BUF_ON)) {
630 * Two buffers are ready for update when Buffer FSM is in
631 * DMA_NO_BUF state. Only one buffer can be prepared without
632 * disabling the channel or polling the DONE bit.
633 * To simplify things, always prepare only one buffer.
635 if (ep93xx_dma_advance_active(edmac)) {
636 m2m_fill_desc(edmac);
637 if (done && !edmac->chan.private) {
638 /* Software trigger for memcpy channel */
639 control = readl(edmac->regs + M2M_CONTROL);
640 control |= M2M_CONTROL_START;
641 writel(control, edmac->regs + M2M_CONTROL);
643 return INTERRUPT_NEXT_BUFFER;
650 * Disable the channel only when Buffer FSM is in DMA_NO_BUF state
651 * and Control FSM is in DMA_STALL state.
654 buf_fsm == M2M_STATUS_BUF_NO &&
655 ctl_fsm == M2M_STATUS_CTL_STALL) {
656 /* Disable interrupts and the channel */
657 control = readl(edmac->regs + M2M_CONTROL);
658 control &= ~(M2M_CONTROL_DONEINT | M2M_CONTROL_NFBINT
659 | M2M_CONTROL_ENABLE);
660 writel(control, edmac->regs + M2M_CONTROL);
661 return INTERRUPT_DONE;
665 * Nothing to do this time.
667 return INTERRUPT_NEXT_BUFFER;
671 * DMA engine API implementation
674 static struct ep93xx_dma_desc *
675 ep93xx_dma_desc_get(struct ep93xx_dma_chan *edmac)
677 struct ep93xx_dma_desc *desc, *_desc;
678 struct ep93xx_dma_desc *ret = NULL;
681 spin_lock_irqsave(&edmac->lock, flags);
682 list_for_each_entry_safe(desc, _desc, &edmac->free_list, node) {
683 if (async_tx_test_ack(&desc->txd)) {
684 list_del_init(&desc->node);
686 /* Re-initialize the descriptor */
690 desc->complete = false;
691 desc->txd.cookie = 0;
692 desc->txd.callback = NULL;
693 desc->txd.callback_param = NULL;
699 spin_unlock_irqrestore(&edmac->lock, flags);
703 static void ep93xx_dma_desc_put(struct ep93xx_dma_chan *edmac,
704 struct ep93xx_dma_desc *desc)
709 spin_lock_irqsave(&edmac->lock, flags);
710 list_splice_init(&desc->tx_list, &edmac->free_list);
711 list_add(&desc->node, &edmac->free_list);
712 spin_unlock_irqrestore(&edmac->lock, flags);
717 * ep93xx_dma_advance_work - start processing the next pending transaction
720 * If we have pending transactions queued and we are currently idling, this
721 * function takes the next queued transaction from the @edmac->queue and
722 * pushes it to the hardware for execution.
724 static void ep93xx_dma_advance_work(struct ep93xx_dma_chan *edmac)
726 struct ep93xx_dma_desc *new;
729 spin_lock_irqsave(&edmac->lock, flags);
730 if (!list_empty(&edmac->active) || list_empty(&edmac->queue)) {
731 spin_unlock_irqrestore(&edmac->lock, flags);
735 /* Take the next descriptor from the pending queue */
736 new = list_first_entry(&edmac->queue, struct ep93xx_dma_desc, node);
737 list_del_init(&new->node);
739 ep93xx_dma_set_active(edmac, new);
741 /* Push it to the hardware */
742 edmac->edma->hw_submit(edmac);
743 spin_unlock_irqrestore(&edmac->lock, flags);
746 static void ep93xx_dma_tasklet(unsigned long data)
748 struct ep93xx_dma_chan *edmac = (struct ep93xx_dma_chan *)data;
749 struct ep93xx_dma_desc *desc, *d;
750 struct dmaengine_desc_callback cb;
753 memset(&cb, 0, sizeof(cb));
754 spin_lock_irq(&edmac->lock);
756 * If dma_terminate_all() was called before we get to run, the active
757 * list has become empty. If that happens we aren't supposed to do
758 * anything more than call ep93xx_dma_advance_work().
760 desc = ep93xx_dma_get_active(edmac);
762 if (desc->complete) {
763 /* mark descriptor complete for non cyclic case only */
764 if (!test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))
765 dma_cookie_complete(&desc->txd);
766 list_splice_init(&edmac->active, &list);
768 dmaengine_desc_get_callback(&desc->txd, &cb);
770 spin_unlock_irq(&edmac->lock);
772 /* Pick up the next descriptor from the queue */
773 ep93xx_dma_advance_work(edmac);
775 /* Now we can release all the chained descriptors */
776 list_for_each_entry_safe(desc, d, &list, node) {
777 dma_descriptor_unmap(&desc->txd);
778 ep93xx_dma_desc_put(edmac, desc);
781 dmaengine_desc_callback_invoke(&cb, NULL);
784 static irqreturn_t ep93xx_dma_interrupt(int irq, void *dev_id)
786 struct ep93xx_dma_chan *edmac = dev_id;
787 struct ep93xx_dma_desc *desc;
788 irqreturn_t ret = IRQ_HANDLED;
790 spin_lock(&edmac->lock);
792 desc = ep93xx_dma_get_active(edmac);
794 dev_warn(chan2dev(edmac),
795 "got interrupt while active list is empty\n");
796 spin_unlock(&edmac->lock);
800 switch (edmac->edma->hw_interrupt(edmac)) {
802 desc->complete = true;
803 tasklet_schedule(&edmac->tasklet);
806 case INTERRUPT_NEXT_BUFFER:
807 if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))
808 tasklet_schedule(&edmac->tasklet);
812 dev_warn(chan2dev(edmac), "unknown interrupt!\n");
817 spin_unlock(&edmac->lock);
822 * ep93xx_dma_tx_submit - set the prepared descriptor(s) to be executed
823 * @tx: descriptor to be executed
825 * Function will execute given descriptor on the hardware or if the hardware
826 * is busy, queue the descriptor to be executed later on. Returns cookie which
827 * can be used to poll the status of the descriptor.
829 static dma_cookie_t ep93xx_dma_tx_submit(struct dma_async_tx_descriptor *tx)
831 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(tx->chan);
832 struct ep93xx_dma_desc *desc;
836 spin_lock_irqsave(&edmac->lock, flags);
837 cookie = dma_cookie_assign(tx);
839 desc = container_of(tx, struct ep93xx_dma_desc, txd);
842 * If nothing is currently prosessed, we push this descriptor
843 * directly to the hardware. Otherwise we put the descriptor
844 * to the pending queue.
846 if (list_empty(&edmac->active)) {
847 ep93xx_dma_set_active(edmac, desc);
848 edmac->edma->hw_submit(edmac);
850 list_add_tail(&desc->node, &edmac->queue);
853 spin_unlock_irqrestore(&edmac->lock, flags);
858 * ep93xx_dma_alloc_chan_resources - allocate resources for the channel
859 * @chan: channel to allocate resources
861 * Function allocates necessary resources for the given DMA channel and
862 * returns number of allocated descriptors for the channel. Negative errno
863 * is returned in case of failure.
865 static int ep93xx_dma_alloc_chan_resources(struct dma_chan *chan)
867 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
868 struct ep93xx_dma_data *data = chan->private;
869 const char *name = dma_chan_name(chan);
872 /* Sanity check the channel parameters */
873 if (!edmac->edma->m2m) {
876 if (data->port < EP93XX_DMA_I2S1 ||
877 data->port > EP93XX_DMA_IRDA)
879 if (data->direction != ep93xx_dma_chan_direction(chan))
883 switch (data->port) {
886 if (!is_slave_direction(data->direction))
895 if (data && data->name)
898 ret = clk_enable(edmac->clk);
902 ret = request_irq(edmac->irq, ep93xx_dma_interrupt, 0, name, edmac);
904 goto fail_clk_disable;
906 spin_lock_irq(&edmac->lock);
907 dma_cookie_init(&edmac->chan);
908 ret = edmac->edma->hw_setup(edmac);
909 spin_unlock_irq(&edmac->lock);
914 for (i = 0; i < DMA_MAX_CHAN_DESCRIPTORS; i++) {
915 struct ep93xx_dma_desc *desc;
917 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
919 dev_warn(chan2dev(edmac), "not enough descriptors\n");
923 INIT_LIST_HEAD(&desc->tx_list);
925 dma_async_tx_descriptor_init(&desc->txd, chan);
926 desc->txd.flags = DMA_CTRL_ACK;
927 desc->txd.tx_submit = ep93xx_dma_tx_submit;
929 ep93xx_dma_desc_put(edmac, desc);
935 free_irq(edmac->irq, edmac);
937 clk_disable(edmac->clk);
943 * ep93xx_dma_free_chan_resources - release resources for the channel
946 * Function releases all the resources allocated for the given channel.
947 * The channel must be idle when this is called.
949 static void ep93xx_dma_free_chan_resources(struct dma_chan *chan)
951 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
952 struct ep93xx_dma_desc *desc, *d;
956 BUG_ON(!list_empty(&edmac->active));
957 BUG_ON(!list_empty(&edmac->queue));
959 spin_lock_irqsave(&edmac->lock, flags);
960 edmac->edma->hw_shutdown(edmac);
961 edmac->runtime_addr = 0;
962 edmac->runtime_ctrl = 0;
964 list_splice_init(&edmac->free_list, &list);
965 spin_unlock_irqrestore(&edmac->lock, flags);
967 list_for_each_entry_safe(desc, d, &list, node)
970 clk_disable(edmac->clk);
971 free_irq(edmac->irq, edmac);
975 * ep93xx_dma_prep_dma_memcpy - prepare a memcpy DMA operation
977 * @dest: destination bus address
978 * @src: source bus address
979 * @len: size of the transaction
980 * @flags: flags for the descriptor
982 * Returns a valid DMA descriptor or %NULL in case of failure.
984 static struct dma_async_tx_descriptor *
985 ep93xx_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest,
986 dma_addr_t src, size_t len, unsigned long flags)
988 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
989 struct ep93xx_dma_desc *desc, *first;
990 size_t bytes, offset;
993 for (offset = 0; offset < len; offset += bytes) {
994 desc = ep93xx_dma_desc_get(edmac);
996 dev_warn(chan2dev(edmac), "couln't get descriptor\n");
1000 bytes = min_t(size_t, len - offset, DMA_MAX_CHAN_BYTES);
1002 desc->src_addr = src + offset;
1003 desc->dst_addr = dest + offset;
1009 list_add_tail(&desc->node, &first->tx_list);
1012 first->txd.cookie = -EBUSY;
1013 first->txd.flags = flags;
1017 ep93xx_dma_desc_put(edmac, first);
1022 * ep93xx_dma_prep_slave_sg - prepare a slave DMA operation
1024 * @sgl: list of buffers to transfer
1025 * @sg_len: number of entries in @sgl
1026 * @dir: direction of tha DMA transfer
1027 * @flags: flags for the descriptor
1028 * @context: operation context (ignored)
1030 * Returns a valid DMA descriptor or %NULL in case of failure.
1032 static struct dma_async_tx_descriptor *
1033 ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1034 unsigned int sg_len, enum dma_transfer_direction dir,
1035 unsigned long flags, void *context)
1037 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1038 struct ep93xx_dma_desc *desc, *first;
1039 struct scatterlist *sg;
1042 if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) {
1043 dev_warn(chan2dev(edmac),
1044 "channel was configured with different direction\n");
1048 if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags)) {
1049 dev_warn(chan2dev(edmac),
1050 "channel is already used for cyclic transfers\n");
1055 for_each_sg(sgl, sg, sg_len, i) {
1056 size_t len = sg_dma_len(sg);
1058 if (len > DMA_MAX_CHAN_BYTES) {
1059 dev_warn(chan2dev(edmac), "too big transfer size %zu\n",
1064 desc = ep93xx_dma_desc_get(edmac);
1066 dev_warn(chan2dev(edmac), "couln't get descriptor\n");
1070 if (dir == DMA_MEM_TO_DEV) {
1071 desc->src_addr = sg_dma_address(sg);
1072 desc->dst_addr = edmac->runtime_addr;
1074 desc->src_addr = edmac->runtime_addr;
1075 desc->dst_addr = sg_dma_address(sg);
1082 list_add_tail(&desc->node, &first->tx_list);
1085 first->txd.cookie = -EBUSY;
1086 first->txd.flags = flags;
1091 ep93xx_dma_desc_put(edmac, first);
1096 * ep93xx_dma_prep_dma_cyclic - prepare a cyclic DMA operation
1098 * @dma_addr: DMA mapped address of the buffer
1099 * @buf_len: length of the buffer (in bytes)
1100 * @period_len: length of a single period
1101 * @dir: direction of the operation
1102 * @flags: tx descriptor status flags
1104 * Prepares a descriptor for cyclic DMA operation. This means that once the
1105 * descriptor is submitted, we will be submitting in a @period_len sized
1106 * buffers and calling callback once the period has been elapsed. Transfer
1107 * terminates only when client calls dmaengine_terminate_all() for this
1110 * Returns a valid DMA descriptor or %NULL in case of failure.
1112 static struct dma_async_tx_descriptor *
1113 ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
1114 size_t buf_len, size_t period_len,
1115 enum dma_transfer_direction dir, unsigned long flags)
1117 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1118 struct ep93xx_dma_desc *desc, *first;
1121 if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) {
1122 dev_warn(chan2dev(edmac),
1123 "channel was configured with different direction\n");
1127 if (test_and_set_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags)) {
1128 dev_warn(chan2dev(edmac),
1129 "channel is already used for cyclic transfers\n");
1133 if (period_len > DMA_MAX_CHAN_BYTES) {
1134 dev_warn(chan2dev(edmac), "too big period length %zu\n",
1139 /* Split the buffer into period size chunks */
1141 for (offset = 0; offset < buf_len; offset += period_len) {
1142 desc = ep93xx_dma_desc_get(edmac);
1144 dev_warn(chan2dev(edmac), "couln't get descriptor\n");
1148 if (dir == DMA_MEM_TO_DEV) {
1149 desc->src_addr = dma_addr + offset;
1150 desc->dst_addr = edmac->runtime_addr;
1152 desc->src_addr = edmac->runtime_addr;
1153 desc->dst_addr = dma_addr + offset;
1156 desc->size = period_len;
1161 list_add_tail(&desc->node, &first->tx_list);
1164 first->txd.cookie = -EBUSY;
1169 ep93xx_dma_desc_put(edmac, first);
1174 * ep93xx_dma_synchronize - Synchronizes the termination of transfers to the
1178 * Synchronizes the DMA channel termination to the current context. When this
1179 * function returns it is guaranteed that all transfers for previously issued
1180 * descriptors have stopped and and it is safe to free the memory associated
1181 * with them. Furthermore it is guaranteed that all complete callback functions
1182 * for a previously submitted descriptor have finished running and it is safe to
1183 * free resources accessed from within the complete callbacks.
1185 static void ep93xx_dma_synchronize(struct dma_chan *chan)
1187 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1189 if (edmac->edma->hw_synchronize)
1190 edmac->edma->hw_synchronize(edmac);
1194 * ep93xx_dma_terminate_all - terminate all transactions
1197 * Stops all DMA transactions. All descriptors are put back to the
1198 * @edmac->free_list and callbacks are _not_ called.
1200 static int ep93xx_dma_terminate_all(struct dma_chan *chan)
1202 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1203 struct ep93xx_dma_desc *desc, *_d;
1204 unsigned long flags;
1207 spin_lock_irqsave(&edmac->lock, flags);
1208 /* First we disable and flush the DMA channel */
1209 edmac->edma->hw_shutdown(edmac);
1210 clear_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags);
1211 list_splice_init(&edmac->active, &list);
1212 list_splice_init(&edmac->queue, &list);
1214 * We then re-enable the channel. This way we can continue submitting
1215 * the descriptors by just calling ->hw_submit() again.
1217 edmac->edma->hw_setup(edmac);
1218 spin_unlock_irqrestore(&edmac->lock, flags);
1220 list_for_each_entry_safe(desc, _d, &list, node)
1221 ep93xx_dma_desc_put(edmac, desc);
1226 static int ep93xx_dma_slave_config(struct dma_chan *chan,
1227 struct dma_slave_config *config)
1229 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1230 enum dma_slave_buswidth width;
1231 unsigned long flags;
1234 if (!edmac->edma->m2m)
1237 switch (config->direction) {
1238 case DMA_DEV_TO_MEM:
1239 width = config->src_addr_width;
1240 addr = config->src_addr;
1243 case DMA_MEM_TO_DEV:
1244 width = config->dst_addr_width;
1245 addr = config->dst_addr;
1253 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1256 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1257 ctrl = M2M_CONTROL_PW_16;
1259 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1260 ctrl = M2M_CONTROL_PW_32;
1266 spin_lock_irqsave(&edmac->lock, flags);
1267 edmac->runtime_addr = addr;
1268 edmac->runtime_ctrl = ctrl;
1269 spin_unlock_irqrestore(&edmac->lock, flags);
1275 * ep93xx_dma_tx_status - check if a transaction is completed
1277 * @cookie: transaction specific cookie
1278 * @state: state of the transaction is stored here if given
1280 * This function can be used to query state of a given transaction.
1282 static enum dma_status ep93xx_dma_tx_status(struct dma_chan *chan,
1283 dma_cookie_t cookie,
1284 struct dma_tx_state *state)
1286 return dma_cookie_status(chan, cookie, state);
1290 * ep93xx_dma_issue_pending - push pending transactions to the hardware
1293 * When this function is called, all pending transactions are pushed to the
1294 * hardware and executed.
1296 static void ep93xx_dma_issue_pending(struct dma_chan *chan)
1298 ep93xx_dma_advance_work(to_ep93xx_dma_chan(chan));
1301 static int __init ep93xx_dma_probe(struct platform_device *pdev)
1303 struct ep93xx_dma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1304 struct ep93xx_dma_engine *edma;
1305 struct dma_device *dma_dev;
1309 edma_size = pdata->num_channels * sizeof(struct ep93xx_dma_chan);
1310 edma = kzalloc(sizeof(*edma) + edma_size, GFP_KERNEL);
1314 dma_dev = &edma->dma_dev;
1315 edma->m2m = platform_get_device_id(pdev)->driver_data;
1316 edma->num_channels = pdata->num_channels;
1318 INIT_LIST_HEAD(&dma_dev->channels);
1319 for (i = 0; i < pdata->num_channels; i++) {
1320 const struct ep93xx_dma_chan_data *cdata = &pdata->channels[i];
1321 struct ep93xx_dma_chan *edmac = &edma->channels[i];
1323 edmac->chan.device = dma_dev;
1324 edmac->regs = cdata->base;
1325 edmac->irq = cdata->irq;
1328 edmac->clk = clk_get(NULL, cdata->name);
1329 if (IS_ERR(edmac->clk)) {
1330 dev_warn(&pdev->dev, "failed to get clock for %s\n",
1335 spin_lock_init(&edmac->lock);
1336 INIT_LIST_HEAD(&edmac->active);
1337 INIT_LIST_HEAD(&edmac->queue);
1338 INIT_LIST_HEAD(&edmac->free_list);
1339 tasklet_init(&edmac->tasklet, ep93xx_dma_tasklet,
1340 (unsigned long)edmac);
1342 list_add_tail(&edmac->chan.device_node,
1343 &dma_dev->channels);
1346 dma_cap_zero(dma_dev->cap_mask);
1347 dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
1348 dma_cap_set(DMA_CYCLIC, dma_dev->cap_mask);
1350 dma_dev->dev = &pdev->dev;
1351 dma_dev->device_alloc_chan_resources = ep93xx_dma_alloc_chan_resources;
1352 dma_dev->device_free_chan_resources = ep93xx_dma_free_chan_resources;
1353 dma_dev->device_prep_slave_sg = ep93xx_dma_prep_slave_sg;
1354 dma_dev->device_prep_dma_cyclic = ep93xx_dma_prep_dma_cyclic;
1355 dma_dev->device_config = ep93xx_dma_slave_config;
1356 dma_dev->device_synchronize = ep93xx_dma_synchronize;
1357 dma_dev->device_terminate_all = ep93xx_dma_terminate_all;
1358 dma_dev->device_issue_pending = ep93xx_dma_issue_pending;
1359 dma_dev->device_tx_status = ep93xx_dma_tx_status;
1361 dma_set_max_seg_size(dma_dev->dev, DMA_MAX_CHAN_BYTES);
1364 dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
1365 dma_dev->device_prep_dma_memcpy = ep93xx_dma_prep_dma_memcpy;
1367 edma->hw_setup = m2m_hw_setup;
1368 edma->hw_shutdown = m2m_hw_shutdown;
1369 edma->hw_submit = m2m_hw_submit;
1370 edma->hw_interrupt = m2m_hw_interrupt;
1372 dma_cap_set(DMA_PRIVATE, dma_dev->cap_mask);
1374 edma->hw_synchronize = m2p_hw_synchronize;
1375 edma->hw_setup = m2p_hw_setup;
1376 edma->hw_shutdown = m2p_hw_shutdown;
1377 edma->hw_submit = m2p_hw_submit;
1378 edma->hw_interrupt = m2p_hw_interrupt;
1381 ret = dma_async_device_register(dma_dev);
1382 if (unlikely(ret)) {
1383 for (i = 0; i < edma->num_channels; i++) {
1384 struct ep93xx_dma_chan *edmac = &edma->channels[i];
1385 if (!IS_ERR_OR_NULL(edmac->clk))
1386 clk_put(edmac->clk);
1390 dev_info(dma_dev->dev, "EP93xx M2%s DMA ready\n",
1391 edma->m2m ? "M" : "P");
1397 static const struct platform_device_id ep93xx_dma_driver_ids[] = {
1398 { "ep93xx-dma-m2p", 0 },
1399 { "ep93xx-dma-m2m", 1 },
1403 static struct platform_driver ep93xx_dma_driver = {
1405 .name = "ep93xx-dma",
1407 .id_table = ep93xx_dma_driver_ids,
1410 static int __init ep93xx_dma_module_init(void)
1412 return platform_driver_probe(&ep93xx_dma_driver, ep93xx_dma_probe);
1414 subsys_initcall(ep93xx_dma_module_init);
1416 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
1417 MODULE_DESCRIPTION("EP93xx DMA driver");
1418 MODULE_LICENSE("GPL");