drivers/dma/edma.c

   1 /*
   2  * TI EDMA DMA engine driver
   3  *
   4  * Copyright 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/dmaengine.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/edma.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/list.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/of.h>
  28 #include <linux/of_dma.h>
  29 #include <linux/of_irq.h>
  30 #include <linux/of_address.h>
  31 #include <linux/of_device.h>
  32 #include <linux/pm_runtime.h>
  33
  34 #include <linux/platform_data/edma.h>
  35
  36 #include "dmaengine.h"
  37 #include "virt-dma.h"
  38
  39 /* Offsets matching "struct edmacc_param" */
  40 #define PARM_OPT                0x00
  41 #define PARM_SRC                0x04
  42 #define PARM_A_B_CNT            0x08
  43 #define PARM_DST                0x0c
  44 #define PARM_SRC_DST_BIDX       0x10
  45 #define PARM_LINK_BCNTRLD       0x14
  46 #define PARM_SRC_DST_CIDX       0x18
  47 #define PARM_CCNT               0x1c
  48
  49 #define PARM_SIZE               0x20
  50
  51 /* Offsets for EDMA CC global channel registers and their shadows */
  52 #define SH_ER                   0x00    /* 64 bits */
  53 #define SH_ECR                  0x08    /* 64 bits */
  54 #define SH_ESR                  0x10    /* 64 bits */
  55 #define SH_CER                  0x18    /* 64 bits */
  56 #define SH_EER                  0x20    /* 64 bits */
  57 #define SH_EECR                 0x28    /* 64 bits */
  58 #define SH_EESR                 0x30    /* 64 bits */
  59 #define SH_SER                  0x38    /* 64 bits */
  60 #define SH_SECR                 0x40    /* 64 bits */
  61 #define SH_IER                  0x50    /* 64 bits */
  62 #define SH_IECR                 0x58    /* 64 bits */
  63 #define SH_IESR                 0x60    /* 64 bits */
  64 #define SH_IPR                  0x68    /* 64 bits */
  65 #define SH_ICR                  0x70    /* 64 bits */
  66 #define SH_IEVAL                0x78
  67 #define SH_QER                  0x80
  68 #define SH_QEER                 0x84
  69 #define SH_QEECR                0x88
  70 #define SH_QEESR                0x8c
  71 #define SH_QSER                 0x90
  72 #define SH_QSECR                0x94
  73 #define SH_SIZE                 0x200
  74
  75 /* Offsets for EDMA CC global registers */
  76 #define EDMA_REV                0x0000
  77 #define EDMA_CCCFG              0x0004
  78 #define EDMA_QCHMAP             0x0200  /* 8 registers */
  79 #define EDMA_DMAQNUM            0x0240  /* 8 registers (4 on OMAP-L1xx) */
  80 #define EDMA_QDMAQNUM           0x0260
  81 #define EDMA_QUETCMAP           0x0280
  82 #define EDMA_QUEPRI             0x0284
  83 #define EDMA_EMR                0x0300  /* 64 bits */
  84 #define EDMA_EMCR               0x0308  /* 64 bits */
  85 #define EDMA_QEMR               0x0310
  86 #define EDMA_QEMCR              0x0314
  87 #define EDMA_CCERR              0x0318
  88 #define EDMA_CCERRCLR           0x031c
  89 #define EDMA_EEVAL              0x0320
  90 #define EDMA_DRAE               0x0340  /* 4 x 64 bits*/
  91 #define EDMA_QRAE               0x0380  /* 4 registers */
  92 #define EDMA_QUEEVTENTRY        0x0400  /* 2 x 16 registers */
  93 #define EDMA_QSTAT              0x0600  /* 2 registers */
  94 #define EDMA_QWMTHRA            0x0620
  95 #define EDMA_QWMTHRB            0x0624
  96 #define EDMA_CCSTAT             0x0640
  97
  98 #define EDMA_M                  0x1000  /* global channel registers */
  99 #define EDMA_ECR                0x1008
 100 #define EDMA_ECRH               0x100C
 101 #define EDMA_SHADOW0            0x2000  /* 4 shadow regions */
 102 #define EDMA_PARM               0x4000  /* PaRAM entries */
 103
 104 #define PARM_OFFSET(param_no)   (EDMA_PARM + ((param_no) << 5))
 105
 106 #define EDMA_DCHMAP             0x0100  /* 64 registers */
 107
 108 /* CCCFG register */
 109 #define GET_NUM_DMACH(x)        (x & 0x7) /* bits 0-2 */
 110 #define GET_NUM_QDMACH(x)       ((x & 0x70) >> 4) /* bits 4-6 */
 111 #define GET_NUM_PAENTRY(x)      ((x & 0x7000) >> 12) /* bits 12-14 */
 112 #define GET_NUM_EVQUE(x)        ((x & 0x70000) >> 16) /* bits 16-18 */
 113 #define GET_NUM_REGN(x)         ((x & 0x300000) >> 20) /* bits 20-21 */
 114 #define CHMAP_EXIST             BIT(24)
 115
 116 /*
 117  * Max of 20 segments per channel to conserve PaRAM slots
 118  * Also note that MAX_NR_SG should be atleast the no.of periods
 119  * that are required for ASoC, otherwise DMA prep calls will
 120  * fail. Today davinci-pcm is the only user of this driver and
 121  * requires atleast 17 slots, so we setup the default to 20.
 122  */
 123 #define MAX_NR_SG               20
 124 #define EDMA_MAX_SLOTS          MAX_NR_SG
 125 #define EDMA_DESCRIPTORS        16
 126
 127 #define EDMA_CHANNEL_ANY                -1      /* for edma_alloc_channel() */
 128 #define EDMA_SLOT_ANY                   -1      /* for edma_alloc_slot() */
 129 #define EDMA_CONT_PARAMS_ANY             1001
 130 #define EDMA_CONT_PARAMS_FIXED_EXACT     1002
 131 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
 132
 133 /* PaRAM slots are laid out like this */
 134 struct edmacc_param {
 135         u32 opt;
 136         u32 src;
 137         u32 a_b_cnt;
 138         u32 dst;
 139         u32 src_dst_bidx;
 140         u32 link_bcntrld;
 141         u32 src_dst_cidx;
 142         u32 ccnt;
 143 } __packed;
 144
 145 /* fields in edmacc_param.opt */
 146 #define SAM             BIT(0)
 147 #define DAM             BIT(1)
 148 #define SYNCDIM         BIT(2)
 149 #define STATIC          BIT(3)
 150 #define EDMA_FWID       (0x07 << 8)
 151 #define TCCMODE         BIT(11)
 152 #define EDMA_TCC(t)     ((t) << 12)
 153 #define TCINTEN         BIT(20)
 154 #define ITCINTEN        BIT(21)
 155 #define TCCHEN          BIT(22)
 156 #define ITCCHEN         BIT(23)
 157
 158 struct edma_pset {
 159         u32                             len;
 160         dma_addr_t                      addr;
 161         struct edmacc_param             param;
 162 };
 163
 164 struct edma_desc {
 165         struct virt_dma_desc            vdesc;
 166         struct list_head                node;
 167         enum dma_transfer_direction     direction;
 168         int                             cyclic;
 169         int                             absync;
 170         int                             pset_nr;
 171         struct edma_chan                *echan;
 172         int                             processed;
 173
 174         /*
 175          * The following 4 elements are used for residue accounting.
 176          *
 177          * - processed_stat: the number of SG elements we have traversed
 178          * so far to cover accounting. This is updated directly to processed
 179          * during edma_callback and is always <= processed, because processed
 180          * refers to the number of pending transfer (programmed to EDMA
 181          * controller), where as processed_stat tracks number of transfers
 182          * accounted for so far.
 183          *
 184          * - residue: The amount of bytes we have left to transfer for this desc
 185          *
 186          * - residue_stat: The residue in bytes of data we have covered
 187          * so far for accounting. This is updated directly to residue
 188          * during callbacks to keep it current.
 189          *
 190          * - sg_len: Tracks the length of the current intermediate transfer,
 191          * this is required to update the residue during intermediate transfer
 192          * completion callback.
 193          */
 194         int                             processed_stat;
 195         u32                             sg_len;
 196         u32                             residue;
 197         u32                             residue_stat;
 198
 199         struct edma_pset                pset[0];
 200 };
 201
 202 struct edma_cc;
 203
 204 struct edma_tc {
 205         struct device_node              *node;
 206         u16                             id;
 207 };
 208
 209 struct edma_chan {
 210         struct virt_dma_chan            vchan;
 211         struct list_head                node;
 212         struct edma_desc                *edesc;
 213         struct edma_cc                  *ecc;
 214         struct edma_tc                  *tc;
 215         int                             ch_num;
 216         bool                            alloced;
 217         bool                            hw_triggered;
 218         int                             slot[EDMA_MAX_SLOTS];
 219         int                             missed;
 220         struct dma_slave_config         cfg;
 221 };
 222
 223 struct edma_cc {
 224         struct device                   *dev;
 225         struct edma_soc_info            *info;
 226         void __iomem                    *base;
 227         int                             id;
 228         bool                            legacy_mode;
 229
 230         /* eDMA3 resource information */
 231         unsigned                        num_channels;
 232         unsigned                        num_qchannels;
 233         unsigned                        num_region;
 234         unsigned                        num_slots;
 235         unsigned                        num_tc;
 236         bool                            chmap_exist;
 237         enum dma_event_q                default_queue;
 238
 239         /*
 240          * The slot_inuse bit for each PaRAM slot is clear unless the slot is
 241          * in use by Linux or if it is allocated to be used by DSP.
 242          */
 243         unsigned long *slot_inuse;
 244
 245         struct dma_device               dma_slave;
 246         struct dma_device               *dma_memcpy;
 247         struct edma_chan                *slave_chans;
 248         struct edma_tc                  *tc_list;
 249         int                             dummy_slot;
 250 };
 251
 252 /* dummy param set used to (re)initialize parameter RAM slots */
 253 static const struct edmacc_param dummy_paramset = {
 254         .link_bcntrld = 0xffff,
 255         .ccnt = 1,
 256 };
 257
 258 #define EDMA_BINDING_LEGACY     0
 259 #define EDMA_BINDING_TPCC       1
 260 static const struct of_device_id edma_of_ids[] = {
 261         {
 262                 .compatible = "ti,edma3",
 263                 .data = (void *)EDMA_BINDING_LEGACY,
 264         },
 265         {
 266                 .compatible = "ti,edma3-tpcc",
 267                 .data = (void *)EDMA_BINDING_TPCC,
 268         },
 269         {}
 270 };
 271
 272 static const struct of_device_id edma_tptc_of_ids[] = {
 273         { .compatible = "ti,edma3-tptc", },
 274         {}
 275 };
 276
 277 static inline unsigned int edma_read(struct edma_cc *ecc, int offset)
 278 {
 279         return (unsigned int)__raw_readl(ecc->base + offset);
 280 }
 281
 282 static inline void edma_write(struct edma_cc *ecc, int offset, int val)
 283 {
 284         __raw_writel(val, ecc->base + offset);
 285 }
 286
 287 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and,
 288                                unsigned or)
 289 {
 290         unsigned val = edma_read(ecc, offset);
 291
 292         val &= and;
 293         val |= or;
 294         edma_write(ecc, offset, val);
 295 }
 296
 297 static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and)
 298 {
 299         unsigned val = edma_read(ecc, offset);
 300
 301         val &= and;
 302         edma_write(ecc, offset, val);
 303 }
 304
 305 static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or)
 306 {
 307         unsigned val = edma_read(ecc, offset);
 308
 309         val |= or;
 310         edma_write(ecc, offset, val);
 311 }
 312
 313 static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset,
 314                                            int i)
 315 {
 316         return edma_read(ecc, offset + (i << 2));
 317 }
 318
 319 static inline void edma_write_array(struct edma_cc *ecc, int offset, int i,
 320                                     unsigned val)
 321 {
 322         edma_write(ecc, offset + (i << 2), val);
 323 }
 324
 325 static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i,
 326                                      unsigned and, unsigned or)
 327 {
 328         edma_modify(ecc, offset + (i << 2), and, or);
 329 }
 330
 331 static inline void edma_or_array(struct edma_cc *ecc, int offset, int i,
 332                                  unsigned or)
 333 {
 334         edma_or(ecc, offset + (i << 2), or);
 335 }
 336
 337 static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j,
 338                                   unsigned or)
 339 {
 340         edma_or(ecc, offset + ((i * 2 + j) << 2), or);
 341 }
 342
 343 static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i,
 344                                      int j, unsigned val)
 345 {
 346         edma_write(ecc, offset + ((i * 2 + j) << 2), val);
 347 }
 348
 349 static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset)
 350 {
 351         return edma_read(ecc, EDMA_SHADOW0 + offset);
 352 }
 353
 354 static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc,
 355                                                    int offset, int i)
 356 {
 357         return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2));
 358 }
 359
 360 static inline void edma_shadow0_write(struct edma_cc *ecc, int offset,
 361                                       unsigned val)
 362 {
 363         edma_write(ecc, EDMA_SHADOW0 + offset, val);
 364 }
 365
 366 static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset,
 367                                             int i, unsigned val)
 368 {
 369         edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val);
 370 }
 371
 372 static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset,
 373                                            int param_no)
 374 {
 375         return edma_read(ecc, EDMA_PARM + offset + (param_no << 5));
 376 }
 377
 378 static inline void edma_param_write(struct edma_cc *ecc, int offset,
 379                                     int param_no, unsigned val)
 380 {
 381         edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val);
 382 }
 383
 384 static inline void edma_param_modify(struct edma_cc *ecc, int offset,
 385                                      int param_no, unsigned and, unsigned or)
 386 {
 387         edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or);
 388 }
 389
 390 static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no,
 391                                   unsigned and)
 392 {
 393         edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and);
 394 }
 395
 396 static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no,
 397                                  unsigned or)
 398 {
 399         edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or);
 400 }
 401
 402 static inline void set_bits(int offset, int len, unsigned long *p)
 403 {
 404         for (; len > 0; len--)
 405                 set_bit(offset + (len - 1), p);
 406 }
 407
 408 static inline void clear_bits(int offset, int len, unsigned long *p)
 409 {
 410         for (; len > 0; len--)
 411                 clear_bit(offset + (len - 1), p);
 412 }
 413
 414 static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
 415                                           int priority)
 416 {
 417         int bit = queue_no * 4;
 418
 419         edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
 420 }
 421
 422 static void edma_set_chmap(struct edma_chan *echan, int slot)
 423 {
 424         struct edma_cc *ecc = echan->ecc;
 425         int channel = EDMA_CHAN_SLOT(echan->ch_num);
 426
 427         if (ecc->chmap_exist) {
 428                 slot = EDMA_CHAN_SLOT(slot);
 429                 edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5));
 430         }
 431 }
 432
 433 static void edma_setup_interrupt(struct edma_chan *echan, bool enable)
 434 {
 435         struct edma_cc *ecc = echan->ecc;
 436         int channel = EDMA_CHAN_SLOT(echan->ch_num);
 437
 438         if (enable) {
 439                 edma_shadow0_write_array(ecc, SH_ICR, channel >> 5,
 440                                          BIT(channel & 0x1f));
 441                 edma_shadow0_write_array(ecc, SH_IESR, channel >> 5,
 442                                          BIT(channel & 0x1f));
 443         } else {
 444                 edma_shadow0_write_array(ecc, SH_IECR, channel >> 5,
 445                                          BIT(channel & 0x1f));
 446         }
 447 }
 448
 449 /*
 450  * paRAM slot management functions
 451  */
 452 static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
 453                             const struct edmacc_param *param)
 454 {
 455         slot = EDMA_CHAN_SLOT(slot);
 456         if (slot >= ecc->num_slots)
 457                 return;
 458         memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE);
 459 }
 460
 461 static void edma_read_slot(struct edma_cc *ecc, unsigned slot,
 462                            struct edmacc_param *param)
 463 {
 464         slot = EDMA_CHAN_SLOT(slot);
 465         if (slot >= ecc->num_slots)
 466                 return;
 467         memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE);
 468 }
 469
 470 /**
 471  * edma_alloc_slot - allocate DMA parameter RAM
 472  * @ecc: pointer to edma_cc struct
 473  * @slot: specific slot to allocate; negative for "any unused slot"
 474  *
 475  * This allocates a parameter RAM slot, initializing it to hold a
 476  * dummy transfer.  Slots allocated using this routine have not been
 477  * mapped to a hardware DMA channel, and will normally be used by
 478  * linking to them from a slot associated with a DMA channel.
 479  *
 480  * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
 481  * slots may be allocated on behalf of DSP firmware.
 482  *
 483  * Returns the number of the slot, else negative errno.
 484  */
 485 static int edma_alloc_slot(struct edma_cc *ecc, int slot)
 486 {
 487         if (slot > 0) {
 488                 slot = EDMA_CHAN_SLOT(slot);
 489                 /* Requesting entry paRAM slot for a HW triggered channel. */
 490                 if (ecc->chmap_exist && slot < ecc->num_channels)
 491                         slot = EDMA_SLOT_ANY;
 492         }
 493
 494         if (slot < 0) {
 495                 if (ecc->chmap_exist)
 496                         slot = 0;
 497                 else
 498                         slot = ecc->num_channels;
 499                 for (;;) {
 500                         slot = find_next_zero_bit(ecc->slot_inuse,
 501                                                   ecc->num_slots,
 502                                                   slot);
 503                         if (slot == ecc->num_slots)
 504                                 return -ENOMEM;
 505                         if (!test_and_set_bit(slot, ecc->slot_inuse))
 506                                 break;
 507                 }
 508         } else if (slot >= ecc->num_slots) {
 509                 return -EINVAL;
 510         } else if (test_and_set_bit(slot, ecc->slot_inuse)) {
 511                 return -EBUSY;
 512         }
 513
 514         edma_write_slot(ecc, slot, &dummy_paramset);
 515
 516         return EDMA_CTLR_CHAN(ecc->id, slot);
 517 }
 518
 519 static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
 520 {
 521         slot = EDMA_CHAN_SLOT(slot);
 522         if (slot >= ecc->num_slots)
 523                 return;
 524
 525         edma_write_slot(ecc, slot, &dummy_paramset);
 526         clear_bit(slot, ecc->slot_inuse);
 527 }
 528
 529 /**
 530  * edma_link - link one parameter RAM slot to another
 531  * @ecc: pointer to edma_cc struct
 532  * @from: parameter RAM slot originating the link
 533  * @to: parameter RAM slot which is the link target
 534  *
 535  * The originating slot should not be part of any active DMA transfer.
 536  */
 537 static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to)
 538 {
 539         if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to)))
 540                 dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n");
 541
 542         from = EDMA_CHAN_SLOT(from);
 543         to = EDMA_CHAN_SLOT(to);
 544         if (from >= ecc->num_slots || to >= ecc->num_slots)
 545                 return;
 546
 547         edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000,
 548                           PARM_OFFSET(to));
 549 }
 550
 551 /**
 552  * edma_get_position - returns the current transfer point
 553  * @ecc: pointer to edma_cc struct
 554  * @slot: parameter RAM slot being examined
 555  * @dst:  true selects the dest position, false the source
 556  *
 557  * Returns the position of the current active slot
 558  */
 559 static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot,
 560                                     bool dst)
 561 {
 562         u32 offs;
 563
 564         slot = EDMA_CHAN_SLOT(slot);
 565         offs = PARM_OFFSET(slot);
 566         offs += dst ? PARM_DST : PARM_SRC;
 567
 568         return edma_read(ecc, offs);
 569 }
 570
 571 /*
 572  * Channels with event associations will be triggered by their hardware
 573  * events, and channels without such associations will be triggered by
 574  * software.  (At this writing there is no interface for using software
 575  * triggers except with channels that don't support hardware triggers.)
 576  */
 577 static void edma_start(struct edma_chan *echan)
 578 {
 579         struct edma_cc *ecc = echan->ecc;
 580         int channel = EDMA_CHAN_SLOT(echan->ch_num);
 581         int j = (channel >> 5);
 582         unsigned int mask = BIT(channel & 0x1f);
 583
 584         if (!echan->hw_triggered) {
 585                 /* EDMA channels without event association */
 586                 dev_dbg(ecc->dev, "ESR%d %08x\n", j,
 587                         edma_shadow0_read_array(ecc, SH_ESR, j));
 588                 edma_shadow0_write_array(ecc, SH_ESR, j, mask);
 589         } else {
 590                 /* EDMA channel with event association */
 591                 dev_dbg(ecc->dev, "ER%d %08x\n", j,
 592                         edma_shadow0_read_array(ecc, SH_ER, j));
 593                 /* Clear any pending event or error */
 594                 edma_write_array(ecc, EDMA_ECR, j, mask);
 595                 edma_write_array(ecc, EDMA_EMCR, j, mask);
 596                 /* Clear any SER */
 597                 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
 598                 edma_shadow0_write_array(ecc, SH_EESR, j, mask);
 599                 dev_dbg(ecc->dev, "EER%d %08x\n", j,
 600                         edma_shadow0_read_array(ecc, SH_EER, j));
 601         }
 602 }
 603
 604 static void edma_stop(struct edma_chan *echan)
 605 {
 606         struct edma_cc *ecc = echan->ecc;
 607         int channel = EDMA_CHAN_SLOT(echan->ch_num);
 608         int j = (channel >> 5);
 609         unsigned int mask = BIT(channel & 0x1f);
 610
 611         edma_shadow0_write_array(ecc, SH_EECR, j, mask);
 612         edma_shadow0_write_array(ecc, SH_ECR, j, mask);
 613         edma_shadow0_write_array(ecc, SH_SECR, j, mask);
 614         edma_write_array(ecc, EDMA_EMCR, j, mask);
 615
 616         /* clear possibly pending completion interrupt */
 617         edma_shadow0_write_array(ecc, SH_ICR, j, mask);
 618
 619         dev_dbg(ecc->dev, "EER%d %08x\n", j,
 620                 edma_shadow0_read_array(ecc, SH_EER, j));
 621
 622         /* REVISIT:  consider guarding against inappropriate event
 623          * chaining by overwriting with dummy_paramset.
 624          */
 625 }
 626
 627 /*
 628  * Temporarily disable EDMA hardware events on the specified channel,
 629  * preventing them from triggering new transfers
 630  */
 631 static void edma_pause(struct edma_chan *echan)
 632 {
 633         int channel = EDMA_CHAN_SLOT(echan->ch_num);
 634         unsigned int mask = BIT(channel & 0x1f);
 635
 636         edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask);
 637 }
 638
 639 /* Re-enable EDMA hardware events on the specified channel.  */
 640 static void edma_resume(struct edma_chan *echan)
 641 {
 642         int channel = EDMA_CHAN_SLOT(echan->ch_num);
 643         unsigned int mask = BIT(channel & 0x1f);
 644
 645         edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask);
 646 }
 647
 648 static void edma_trigger_channel(struct edma_chan *echan)
 649 {
 650         struct edma_cc *ecc = echan->ecc;
 651         int channel = EDMA_CHAN_SLOT(echan->ch_num);
 652         unsigned int mask = BIT(channel & 0x1f);
 653
 654         edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);
 655
 656         dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5),
 657                 edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
 658 }
 659
 660 static void edma_clean_channel(struct edma_chan *echan)
 661 {
 662         struct edma_cc *ecc = echan->ecc;
 663         int channel = EDMA_CHAN_SLOT(echan->ch_num);
 664         int j = (channel >> 5);
 665         unsigned int mask = BIT(channel & 0x1f);
 666
 667         dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j));
 668         edma_shadow0_write_array(ecc, SH_ECR, j, mask);
 669         /* Clear the corresponding EMR bits */
 670         edma_write_array(ecc, EDMA_EMCR, j, mask);
 671         /* Clear any SER */
 672         edma_shadow0_write_array(ecc, SH_SECR, j, mask);
 673         edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
 674 }
 675
 676 /* Move channel to a specific event queue */
 677 static void edma_assign_channel_eventq(struct edma_chan *echan,
 678                                        enum dma_event_q eventq_no)
 679 {
 680         struct edma_cc *ecc = echan->ecc;
 681         int channel = EDMA_CHAN_SLOT(echan->ch_num);
 682         int bit = (channel & 0x7) * 4;
 683
 684         /* default to low priority queue */
 685         if (eventq_no == EVENTQ_DEFAULT)
 686                 eventq_no = ecc->default_queue;
 687         if (eventq_no >= ecc->num_tc)
 688                 return;
 689
 690         eventq_no &= 7;
 691         edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit),
 692                           eventq_no << bit);
 693 }
 694
 695 static int edma_alloc_channel(struct edma_chan *echan,
 696                               enum dma_event_q eventq_no)
 697 {
 698         struct edma_cc *ecc = echan->ecc;
 699         int channel = EDMA_CHAN_SLOT(echan->ch_num);
 700
 701         /* ensure access through shadow region 0 */
 702         edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
 703
 704         /* ensure no events are pending */
 705         edma_stop(echan);
 706
 707         edma_setup_interrupt(echan, true);
 708
 709         edma_assign_channel_eventq(echan, eventq_no);
 710
 711         return 0;
 712 }
 713
 714 static void edma_free_channel(struct edma_chan *echan)
 715 {
 716         /* ensure no events are pending */
 717         edma_stop(echan);
 718         /* REVISIT should probably take out of shadow region 0 */
 719         edma_setup_interrupt(echan, false);
 720 }
 721
 722 static inline struct edma_cc *to_edma_cc(struct dma_device *d)
 723 {
 724         return container_of(d, struct edma_cc, dma_slave);
 725 }
 726
 727 static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
 728 {
 729         return container_of(c, struct edma_chan, vchan.chan);
 730 }
 731
 732 static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx)
 733 {
 734         return container_of(tx, struct edma_desc, vdesc.tx);
 735 }
 736
 737 static void edma_desc_free(struct virt_dma_desc *vdesc)
 738 {
 739         kfree(container_of(vdesc, struct edma_desc, vdesc));
 740 }
 741
 742 /* Dispatch a queued descriptor to the controller (caller holds lock) */
 743 static void edma_execute(struct edma_chan *echan)
 744 {
 745         struct edma_cc *ecc = echan->ecc;
 746         struct virt_dma_desc *vdesc;
 747         struct edma_desc *edesc;
 748         struct device *dev = echan->vchan.chan.device->dev;
 749         int i, j, left, nslots;
 750
 751         if (!echan->edesc) {
 752                 /* Setup is needed for the first transfer */
 753                 vdesc = vchan_next_desc(&echan->vchan);
 754                 if (!vdesc)
 755                         return;
 756                 list_del(&vdesc->node);
 757                 echan->edesc = to_edma_desc(&vdesc->tx);
 758         }
 759
 760         edesc = echan->edesc;
 761
 762         /* Find out how many left */
 763         left = edesc->pset_nr - edesc->processed;
 764         nslots = min(MAX_NR_SG, left);
 765         edesc->sg_len = 0;
 766
 767         /* Write descriptor PaRAM set(s) */
 768         for (i = 0; i < nslots; i++) {
 769                 j = i + edesc->processed;
 770                 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
 771                 edesc->sg_len += edesc->pset[j].len;
 772                 dev_vdbg(dev,
 773                          "\n pset[%d]:\n"
 774                          "  chnum\t%d\n"
 775                          "  slot\t%d\n"
 776                          "  opt\t%08x\n"
 777                          "  src\t%08x\n"
 778                          "  dst\t%08x\n"
 779                          "  abcnt\t%08x\n"
 780                          "  ccnt\t%08x\n"
 781                          "  bidx\t%08x\n"
 782                          "  cidx\t%08x\n"
 783                          "  lkrld\t%08x\n",
 784                          j, echan->ch_num, echan->slot[i],
 785                          edesc->pset[j].param.opt,
 786                          edesc->pset[j].param.src,
 787                          edesc->pset[j].param.dst,
 788                          edesc->pset[j].param.a_b_cnt,
 789                          edesc->pset[j].param.ccnt,
 790                          edesc->pset[j].param.src_dst_bidx,
 791                          edesc->pset[j].param.src_dst_cidx,
 792                          edesc->pset[j].param.link_bcntrld);
 793                 /* Link to the previous slot if not the last set */
 794                 if (i != (nslots - 1))
 795                         edma_link(ecc, echan->slot[i], echan->slot[i + 1]);
 796         }
 797
 798         edesc->processed += nslots;
 799
 800         /*
 801          * If this is either the last set in a set of SG-list transactions
 802          * then setup a link to the dummy slot, this results in all future
 803          * events being absorbed and that's OK because we're done
 804          */
 805         if (edesc->processed == edesc->pset_nr) {
 806                 if (edesc->cyclic)
 807                         edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]);
 808                 else
 809                         edma_link(ecc, echan->slot[nslots - 1],
 810                                   echan->ecc->dummy_slot);
 811         }
 812
 813         if (echan->missed) {
 814                 /*
 815                  * This happens due to setup times between intermediate
 816                  * transfers in long SG lists which have to be broken up into
 817                  * transfers of MAX_NR_SG
 818                  */
 819                 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
 820                 edma_clean_channel(echan);
 821                 edma_stop(echan);
 822                 edma_start(echan);
 823                 edma_trigger_channel(echan);
 824                 echan->missed = 0;
 825         } else if (edesc->processed <= MAX_NR_SG) {
 826                 dev_dbg(dev, "first transfer starting on channel %d\n",
 827                         echan->ch_num);
 828                 edma_start(echan);
 829         } else {
 830                 dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
 831                         echan->ch_num, edesc->processed);
 832                 edma_resume(echan);
 833         }
 834 }
 835
 836 static int edma_terminate_all(struct dma_chan *chan)
 837 {
 838         struct edma_chan *echan = to_edma_chan(chan);
 839         unsigned long flags;
 840         LIST_HEAD(head);
 841
 842         spin_lock_irqsave(&echan->vchan.lock, flags);
 843
 844         /*
 845          * Stop DMA activity: we assume the callback will not be called
 846          * after edma_dma() returns (even if it does, it will see
 847          * echan->edesc is NULL and exit.)
 848          */
 849         if (echan->edesc) {
 850                 edma_stop(echan);
 851                 /* Move the cyclic channel back to default queue */
 852                 if (!echan->tc && echan->edesc->cyclic)
 853                         edma_assign_channel_eventq(echan, EVENTQ_DEFAULT);
 854                 /*
 855                  * free the running request descriptor
 856                  * since it is not in any of the vdesc lists
 857                  */
 858                 edma_desc_free(&echan->edesc->vdesc);
 859                 echan->edesc = NULL;
 860         }
 861
 862         vchan_get_all_descriptors(&echan->vchan, &head);
 863         spin_unlock_irqrestore(&echan->vchan.lock, flags);
 864         vchan_dma_desc_free_list(&echan->vchan, &head);
 865
 866         return 0;
 867 }
 868
 869 static int edma_slave_config(struct dma_chan *chan,
 870         struct dma_slave_config *cfg)
 871 {
 872         struct edma_chan *echan = to_edma_chan(chan);
 873
 874         if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
 875             cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
 876                 return -EINVAL;
 877
 878         memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
 879
 880         return 0;
 881 }
 882
 883 static int edma_dma_pause(struct dma_chan *chan)
 884 {
 885         struct edma_chan *echan = to_edma_chan(chan);
 886
 887         if (!echan->edesc)
 888                 return -EINVAL;
 889
 890         edma_pause(echan);
 891         return 0;
 892 }
 893
 894 static int edma_dma_resume(struct dma_chan *chan)
 895 {
 896         struct edma_chan *echan = to_edma_chan(chan);
 897
 898         edma_resume(echan);
 899         return 0;
 900 }
 901
 902 /*
 903  * A PaRAM set configuration abstraction used by other modes
 904  * @chan: Channel who's PaRAM set we're configuring
 905  * @pset: PaRAM set to initialize and setup.
 906  * @src_addr: Source address of the DMA
 907  * @dst_addr: Destination address of the DMA
 908  * @burst: In units of dev_width, how much to send
 909  * @dev_width: How much is the dev_width
 910  * @dma_length: Total length of the DMA transfer
 911  * @direction: Direction of the transfer
 912  */
 913 static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
 914                             dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
 915                             unsigned int acnt, unsigned int dma_length,
 916                             enum dma_transfer_direction direction)
 917 {
 918         struct edma_chan *echan = to_edma_chan(chan);
 919         struct device *dev = chan->device->dev;
 920         struct edmacc_param *param = &epset->param;
 921         int bcnt, ccnt, cidx;
 922         int src_bidx, dst_bidx, src_cidx, dst_cidx;
 923         int absync;
 924
 925         /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
 926         if (!burst)
 927                 burst = 1;
 928         /*
 929          * If the maxburst is equal to the fifo width, use
 930          * A-synced transfers. This allows for large contiguous
 931          * buffer transfers using only one PaRAM set.
 932          */
 933         if (burst == 1) {
 934                 /*
 935                  * For the A-sync case, bcnt and ccnt are the remainder
 936                  * and quotient respectively of the division of:
 937                  * (dma_length / acnt) by (SZ_64K -1). This is so
 938                  * that in case bcnt over flows, we have ccnt to use.
 939                  * Note: In A-sync tranfer only, bcntrld is used, but it
 940                  * only applies for sg_dma_len(sg) >= SZ_64K.
 941                  * In this case, the best way adopted is- bccnt for the
 942                  * first frame will be the remainder below. Then for
 943                  * every successive frame, bcnt will be SZ_64K-1. This
 944                  * is assured as bcntrld = 0xffff in end of function.
 945                  */
 946                 absync = false;
 947                 ccnt = dma_length / acnt / (SZ_64K - 1);
 948                 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
 949                 /*
 950                  * If bcnt is non-zero, we have a remainder and hence an
 951                  * extra frame to transfer, so increment ccnt.
 952                  */
 953                 if (bcnt)
 954                         ccnt++;
 955                 else
 956                         bcnt = SZ_64K - 1;
 957                 cidx = acnt;
 958         } else {
 959                 /*
 960                  * If maxburst is greater than the fifo address_width,
 961                  * use AB-synced transfers where A count is the fifo
 962                  * address_width and B count is the maxburst. In this
 963                  * case, we are limited to transfers of C count frames
 964                  * of (address_width * maxburst) where C count is limited
 965                  * to SZ_64K-1. This places an upper bound on the length
 966                  * of an SG segment that can be handled.
 967                  */
 968                 absync = true;
 969                 bcnt = burst;
 970                 ccnt = dma_length / (acnt * bcnt);
 971                 if (ccnt > (SZ_64K - 1)) {
 972                         dev_err(dev, "Exceeded max SG segment size\n");
 973                         return -EINVAL;
 974                 }
 975                 cidx = acnt * bcnt;
 976         }
 977
 978         epset->len = dma_length;
 979
 980         if (direction == DMA_MEM_TO_DEV) {
 981                 src_bidx = acnt;
 982                 src_cidx = cidx;
 983                 dst_bidx = 0;
 984                 dst_cidx = 0;
 985                 epset->addr = src_addr;
 986         } else if (direction == DMA_DEV_TO_MEM)  {
 987                 src_bidx = 0;
 988                 src_cidx = 0;
 989                 dst_bidx = acnt;
 990                 dst_cidx = cidx;
 991                 epset->addr = dst_addr;
 992         } else if (direction == DMA_MEM_TO_MEM)  {
 993                 src_bidx = acnt;
 994                 src_cidx = cidx;
 995                 dst_bidx = acnt;
 996                 dst_cidx = cidx;
 997         } else {
 998                 dev_err(dev, "%s: direction not implemented yet\n", __func__);
 999                 return -EINVAL;
1000         }
1001
1002         param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
1003         /* Configure A or AB synchronized transfers */
1004         if (absync)
1005                 param->opt |= SYNCDIM;
1006
1007         param->src = src_addr;
1008         param->dst = dst_addr;
1009
1010         param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
1011         param->src_dst_cidx = (dst_cidx << 16) | src_cidx;
1012
1013         param->a_b_cnt = bcnt << 16 | acnt;
1014         param->ccnt = ccnt;
1015         /*
1016          * Only time when (bcntrld) auto reload is required is for
1017          * A-sync case, and in this case, a requirement of reload value
1018          * of SZ_64K-1 only is assured. 'link' is initially set to NULL
1019          * and then later will be populated by edma_execute.
1020          */
1021         param->link_bcntrld = 0xffffffff;
1022         return absync;
1023 }
1024
1025 static struct dma_async_tx_descriptor *edma_prep_slave_sg(
1026         struct dma_chan *chan, struct scatterlist *sgl,
1027         unsigned int sg_len, enum dma_transfer_direction direction,
1028         unsigned long tx_flags, void *context)
1029 {
1030         struct edma_chan *echan = to_edma_chan(chan);
1031         struct device *dev = chan->device->dev;
1032         struct edma_desc *edesc;
1033         dma_addr_t src_addr = 0, dst_addr = 0;
1034         enum dma_slave_buswidth dev_width;
1035         u32 burst;
1036         struct scatterlist *sg;
1037         int i, nslots, ret;
1038
1039         if (unlikely(!echan || !sgl || !sg_len))
1040                 return NULL;
1041
1042         if (direction == DMA_DEV_TO_MEM) {
1043                 src_addr = echan->cfg.src_addr;
1044                 dev_width = echan->cfg.src_addr_width;
1045                 burst = echan->cfg.src_maxburst;
1046         } else if (direction == DMA_MEM_TO_DEV) {
1047                 dst_addr = echan->cfg.dst_addr;
1048                 dev_width = echan->cfg.dst_addr_width;
1049                 burst = echan->cfg.dst_maxburst;
1050         } else {
1051                 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1052                 return NULL;
1053         }
1054
1055         if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1056                 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1057                 return NULL;
1058         }
1059
1060         edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]),
1061                         GFP_ATOMIC);
1062         if (!edesc) {
1063                 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
1064                 return NULL;
1065         }
1066
1067         edesc->pset_nr = sg_len;
1068         edesc->residue = 0;
1069         edesc->direction = direction;
1070         edesc->echan = echan;
1071
1072         /* Allocate a PaRAM slot, if needed */
1073         nslots = min_t(unsigned, MAX_NR_SG, sg_len);
1074
1075         for (i = 0; i < nslots; i++) {
1076                 if (echan->slot[i] < 0) {
1077                         echan->slot[i] =
1078                                 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1079                         if (echan->slot[i] < 0) {
1080                                 kfree(edesc);
1081                                 dev_err(dev, "%s: Failed to allocate slot\n",
1082                                         __func__);
1083                                 return NULL;
1084                         }
1085                 }
1086         }
1087
1088         /* Configure PaRAM sets for each SG */
1089         for_each_sg(sgl, sg, sg_len, i) {
1090                 /* Get address for each SG */
1091                 if (direction == DMA_DEV_TO_MEM)
1092                         dst_addr = sg_dma_address(sg);
1093                 else
1094                         src_addr = sg_dma_address(sg);
1095
1096                 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1097                                        dst_addr, burst, dev_width,
1098                                        sg_dma_len(sg), direction);
1099                 if (ret < 0) {
1100                         kfree(edesc);
1101                         return NULL;
1102                 }
1103
1104                 edesc->absync = ret;
1105                 edesc->residue += sg_dma_len(sg);
1106
1107                 /* If this is the last in a current SG set of transactions,
1108                    enable interrupts so that next set is processed */
1109                 if (!((i+1) % MAX_NR_SG))
1110                         edesc->pset[i].param.opt |= TCINTEN;
1111
1112                 /* If this is the last set, enable completion interrupt flag */
1113                 if (i == sg_len - 1)
1114                         edesc->pset[i].param.opt |= TCINTEN;
1115         }
1116         edesc->residue_stat = edesc->residue;
1117
1118         return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1119 }
1120
1121 static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
1122         struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1123         size_t len, unsigned long tx_flags)
1124 {
1125         int ret, nslots;
1126         struct edma_desc *edesc;
1127         struct device *dev = chan->device->dev;
1128         struct edma_chan *echan = to_edma_chan(chan);
1129         unsigned int width, pset_len, array_size;
1130
1131         if (unlikely(!echan || !len))
1132                 return NULL;
1133
1134         /* Align the array size (acnt block) with the transfer properties */
1135         switch (__ffs((src | dest | len))) {
1136         case 0:
1137                 array_size = SZ_32K - 1;
1138                 break;
1139         case 1:
1140                 array_size = SZ_32K - 2;
1141                 break;
1142         default:
1143                 array_size = SZ_32K - 4;
1144                 break;
1145         }
1146
1147         if (len < SZ_64K) {
1148                 /*
1149                  * Transfer size less than 64K can be handled with one paRAM
1150                  * slot and with one burst.
1151                  * ACNT = length
1152                  */
1153                 width = len;
1154                 pset_len = len;
1155                 nslots = 1;
1156         } else {
1157                 /*
1158                  * Transfer size bigger than 64K will be handled with maximum of
1159                  * two paRAM slots.
1160                  * slot1: (full_length / 32767) times 32767 bytes bursts.
1161                  *        ACNT = 32767, length1: (full_length / 32767) * 32767
1162                  * slot2: the remaining amount of data after slot1.
1163                  *        ACNT = full_length - length1, length2 = ACNT
1164                  *
1165                  * When the full_length is multibple of 32767 one slot can be
1166                  * used to complete the transfer.
1167                  */
1168                 width = array_size;
1169                 pset_len = rounddown(len, width);
1170                 /* One slot is enough for lengths multiple of (SZ_32K -1) */
1171                 if (unlikely(pset_len == len))
1172                         nslots = 1;
1173                 else
1174                         nslots = 2;
1175         }
1176
1177         edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
1178                         GFP_ATOMIC);
1179         if (!edesc) {
1180                 dev_dbg(dev, "Failed to allocate a descriptor\n");
1181                 return NULL;
1182         }
1183
1184         edesc->pset_nr = nslots;
1185         edesc->residue = edesc->residue_stat = len;
1186         edesc->direction = DMA_MEM_TO_MEM;
1187         edesc->echan = echan;
1188
1189         ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1,
1190                                width, pset_len, DMA_MEM_TO_MEM);
1191         if (ret < 0) {
1192                 kfree(edesc);
1193                 return NULL;
1194         }
1195
1196         edesc->absync = ret;
1197
1198         edesc->pset[0].param.opt |= ITCCHEN;
1199         if (nslots == 1) {
1200                 /* Enable transfer complete interrupt */
1201                 edesc->pset[0].param.opt |= TCINTEN;
1202         } else {
1203                 /* Enable transfer complete chaining for the first slot */
1204                 edesc->pset[0].param.opt |= TCCHEN;
1205
1206                 if (echan->slot[1] < 0) {
1207                         echan->slot[1] = edma_alloc_slot(echan->ecc,
1208                                                          EDMA_SLOT_ANY);
1209                         if (echan->slot[1] < 0) {
1210                                 kfree(edesc);
1211                                 dev_err(dev, "%s: Failed to allocate slot\n",
1212                                         __func__);
1213                                 return NULL;
1214                         }
1215                 }
1216                 dest += pset_len;
1217                 src += pset_len;
1218                 pset_len = width = len % array_size;
1219
1220                 ret = edma_config_pset(chan, &edesc->pset[1], src, dest, 1,
1221                                        width, pset_len, DMA_MEM_TO_MEM);
1222                 if (ret < 0) {
1223                         kfree(edesc);
1224                         return NULL;
1225                 }
1226
1227                 edesc->pset[1].param.opt |= ITCCHEN;
1228                 edesc->pset[1].param.opt |= TCINTEN;
1229         }
1230
1231         return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1232 }
1233
1234 static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
1235         struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
1236         size_t period_len, enum dma_transfer_direction direction,
1237         unsigned long tx_flags)
1238 {
1239         struct edma_chan *echan = to_edma_chan(chan);
1240         struct device *dev = chan->device->dev;
1241         struct edma_desc *edesc;
1242         dma_addr_t src_addr, dst_addr;
1243         enum dma_slave_buswidth dev_width;
1244         u32 burst;
1245         int i, ret, nslots;
1246
1247         if (unlikely(!echan || !buf_len || !period_len))
1248                 return NULL;
1249
1250         if (direction == DMA_DEV_TO_MEM) {
1251                 src_addr = echan->cfg.src_addr;
1252                 dst_addr = buf_addr;
1253                 dev_width = echan->cfg.src_addr_width;
1254                 burst = echan->cfg.src_maxburst;
1255         } else if (direction == DMA_MEM_TO_DEV) {
1256                 src_addr = buf_addr;
1257                 dst_addr = echan->cfg.dst_addr;
1258                 dev_width = echan->cfg.dst_addr_width;
1259                 burst = echan->cfg.dst_maxburst;
1260         } else {
1261                 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1262                 return NULL;
1263         }
1264
1265         if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1266                 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1267                 return NULL;
1268         }
1269
1270         if (unlikely(buf_len % period_len)) {
1271                 dev_err(dev, "Period should be multiple of Buffer length\n");
1272                 return NULL;
1273         }
1274
1275         nslots = (buf_len / period_len) + 1;
1276
1277         /*
1278          * Cyclic DMA users such as audio cannot tolerate delays introduced
1279          * by cases where the number of periods is more than the maximum
1280          * number of SGs the EDMA driver can handle at a time. For DMA types
1281          * such as Slave SGs, such delays are tolerable and synchronized,
1282          * but the synchronization is difficult to achieve with Cyclic and
1283          * cannot be guaranteed, so we error out early.
1284          */
1285         if (nslots > MAX_NR_SG)
1286                 return NULL;
1287
1288         edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
1289                         GFP_ATOMIC);
1290         if (!edesc) {
1291                 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
1292                 return NULL;
1293         }
1294
1295         edesc->cyclic = 1;
1296         edesc->pset_nr = nslots;
1297         edesc->residue = edesc->residue_stat = buf_len;
1298         edesc->direction = direction;
1299         edesc->echan = echan;
1300
1301         dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
1302                 __func__, echan->ch_num, nslots, period_len, buf_len);
1303
1304         for (i = 0; i < nslots; i++) {
1305                 /* Allocate a PaRAM slot, if needed */
1306                 if (echan->slot[i] < 0) {
1307                         echan->slot[i] =
1308                                 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1309                         if (echan->slot[i] < 0) {
1310                                 kfree(edesc);
1311                                 dev_err(dev, "%s: Failed to allocate slot\n",
1312                                         __func__);
1313                                 return NULL;
1314                         }
1315                 }
1316
1317                 if (i == nslots - 1) {
1318                         memcpy(&edesc->pset[i], &edesc->pset[0],
1319                                sizeof(edesc->pset[0]));
1320                         break;
1321                 }
1322
1323                 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1324                                        dst_addr, burst, dev_width, period_len,
1325                                        direction);
1326                 if (ret < 0) {
1327                         kfree(edesc);
1328                         return NULL;
1329                 }
1330
1331                 if (direction == DMA_DEV_TO_MEM)
1332                         dst_addr += period_len;
1333                 else
1334                         src_addr += period_len;
1335
1336                 dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
1337                 dev_vdbg(dev,
1338                         "\n pset[%d]:\n"
1339                         "  chnum\t%d\n"
1340                         "  slot\t%d\n"
1341                         "  opt\t%08x\n"
1342                         "  src\t%08x\n"
1343                         "  dst\t%08x\n"
1344                         "  abcnt\t%08x\n"
1345                         "  ccnt\t%08x\n"
1346                         "  bidx\t%08x\n"
1347                         "  cidx\t%08x\n"
1348                         "  lkrld\t%08x\n",
1349                         i, echan->ch_num, echan->slot[i],
1350                         edesc->pset[i].param.opt,
1351                         edesc->pset[i].param.src,
1352                         edesc->pset[i].param.dst,
1353                         edesc->pset[i].param.a_b_cnt,
1354                         edesc->pset[i].param.ccnt,
1355                         edesc->pset[i].param.src_dst_bidx,
1356                         edesc->pset[i].param.src_dst_cidx,
1357                         edesc->pset[i].param.link_bcntrld);
1358
1359                 edesc->absync = ret;
1360
1361                 /*
1362                  * Enable period interrupt only if it is requested
1363                  */
1364                 if (tx_flags & DMA_PREP_INTERRUPT)
1365                         edesc->pset[i].param.opt |= TCINTEN;
1366         }
1367
1368         /* Place the cyclic channel to highest priority queue */
1369         if (!echan->tc)
1370                 edma_assign_channel_eventq(echan, EVENTQ_0);
1371
1372         return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1373 }
1374
1375 static void edma_completion_handler(struct edma_chan *echan)
1376 {
1377         struct device *dev = echan->vchan.chan.device->dev;
1378         struct edma_desc *edesc = echan->edesc;
1379
1380         if (!edesc)
1381                 return;
1382
1383         spin_lock(&echan->vchan.lock);
1384         if (edesc->cyclic) {
1385                 vchan_cyclic_callback(&edesc->vdesc);
1386                 spin_unlock(&echan->vchan.lock);
1387                 return;
1388         } else if (edesc->processed == edesc->pset_nr) {
1389                 edesc->residue = 0;
1390                 edma_stop(echan);
1391                 vchan_cookie_complete(&edesc->vdesc);
1392                 echan->edesc = NULL;
1393
1394                 dev_dbg(dev, "Transfer completed on channel %d\n",
1395                         echan->ch_num);
1396         } else {
1397                 dev_dbg(dev, "Sub transfer completed on channel %d\n",
1398                         echan->ch_num);
1399
1400                 edma_pause(echan);
1401
1402                 /* Update statistics for tx_status */
1403                 edesc->residue -= edesc->sg_len;
1404                 edesc->residue_stat = edesc->residue;
1405                 edesc->processed_stat = edesc->processed;
1406         }
1407         edma_execute(echan);
1408
1409         spin_unlock(&echan->vchan.lock);
1410 }
1411
1412 /* eDMA interrupt handler */
1413 static irqreturn_t dma_irq_handler(int irq, void *data)
1414 {
1415         struct edma_cc *ecc = data;
1416         int ctlr;
1417         u32 sh_ier;
1418         u32 sh_ipr;
1419         u32 bank;
1420
1421         ctlr = ecc->id;
1422         if (ctlr < 0)
1423                 return IRQ_NONE;
1424
1425         dev_vdbg(ecc->dev, "dma_irq_handler\n");
1426
1427         sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
1428         if (!sh_ipr) {
1429                 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
1430                 if (!sh_ipr)
1431                         return IRQ_NONE;
1432                 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
1433                 bank = 1;
1434         } else {
1435                 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
1436                 bank = 0;
1437         }
1438
1439         do {
1440                 u32 slot;
1441                 u32 channel;
1442
1443                 slot = __ffs(sh_ipr);
1444                 sh_ipr &= ~(BIT(slot));
1445
1446                 if (sh_ier & BIT(slot)) {
1447                         channel = (bank << 5) | slot;
1448                         /* Clear the corresponding IPR bits */
1449                         edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
1450                         edma_completion_handler(&ecc->slave_chans[channel]);
1451                 }
1452         } while (sh_ipr);
1453
1454         edma_shadow0_write(ecc, SH_IEVAL, 1);
1455         return IRQ_HANDLED;
1456 }
1457
1458 static void edma_error_handler(struct edma_chan *echan)
1459 {
1460         struct edma_cc *ecc = echan->ecc;
1461         struct device *dev = echan->vchan.chan.device->dev;
1462         struct edmacc_param p;
1463
1464         if (!echan->edesc)
1465                 return;
1466
1467         spin_lock(&echan->vchan.lock);
1468
1469         edma_read_slot(ecc, echan->slot[0], &p);
1470         /*
1471          * Issue later based on missed flag which will be sure
1472          * to happen as:
1473          * (1) we finished transmitting an intermediate slot and
1474          *     edma_execute is coming up.
1475          * (2) or we finished current transfer and issue will
1476          *     call edma_execute.
1477          *
1478          * Important note: issuing can be dangerous here and
1479          * lead to some nasty recursion when we are in a NULL
1480          * slot. So we avoid doing so and set the missed flag.
1481          */
1482         if (p.a_b_cnt == 0 && p.ccnt == 0) {
1483                 dev_dbg(dev, "Error on null slot, setting miss\n");
1484                 echan->missed = 1;
1485         } else {
1486                 /*
1487                  * The slot is already programmed but the event got
1488                  * missed, so its safe to issue it here.
1489                  */
1490                 dev_dbg(dev, "Missed event, TRIGGERING\n");
1491                 edma_clean_channel(echan);
1492                 edma_stop(echan);
1493                 edma_start(echan);
1494                 edma_trigger_channel(echan);
1495         }
1496         spin_unlock(&echan->vchan.lock);
1497 }
1498
1499 static inline bool edma_error_pending(struct edma_cc *ecc)
1500 {
1501         if (edma_read_array(ecc, EDMA_EMR, 0) ||
1502             edma_read_array(ecc, EDMA_EMR, 1) ||
1503             edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR))
1504                 return true;
1505
1506         return false;
1507 }
1508
1509 /* eDMA error interrupt handler */
1510 static irqreturn_t dma_ccerr_handler(int irq, void *data)
1511 {
1512         struct edma_cc *ecc = data;
1513         int i, j;
1514         int ctlr;
1515         unsigned int cnt = 0;
1516         unsigned int val;
1517
1518         ctlr = ecc->id;
1519         if (ctlr < 0)
1520                 return IRQ_NONE;
1521
1522         dev_vdbg(ecc->dev, "dma_ccerr_handler\n");
1523
1524         if (!edma_error_pending(ecc))
1525                 return IRQ_NONE;
1526
1527         while (1) {
1528                 /* Event missed register(s) */
1529                 for (j = 0; j < 2; j++) {
1530                         unsigned long emr;
1531
1532                         val = edma_read_array(ecc, EDMA_EMR, j);
1533                         if (!val)
1534                                 continue;
1535
1536                         dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val);
1537                         emr = val;
1538                         for (i = find_next_bit(&emr, 32, 0); i < 32;
1539                              i = find_next_bit(&emr, 32, i + 1)) {
1540                                 int k = (j << 5) + i;
1541
1542                                 /* Clear the corresponding EMR bits */
1543                                 edma_write_array(ecc, EDMA_EMCR, j, BIT(i));
1544                                 /* Clear any SER */
1545                                 edma_shadow0_write_array(ecc, SH_SECR, j,
1546                                                          BIT(i));
1547                                 edma_error_handler(&ecc->slave_chans[k]);
1548                         }
1549                 }
1550
1551                 val = edma_read(ecc, EDMA_QEMR);
1552                 if (val) {
1553                         dev_dbg(ecc->dev, "QEMR 0x%02x\n", val);
1554                         /* Not reported, just clear the interrupt reason. */
1555                         edma_write(ecc, EDMA_QEMCR, val);
1556                         edma_shadow0_write(ecc, SH_QSECR, val);
1557                 }
1558
1559                 val = edma_read(ecc, EDMA_CCERR);
1560                 if (val) {
1561                         dev_warn(ecc->dev, "CCERR 0x%08x\n", val);
1562                         /* Not reported, just clear the interrupt reason. */
1563                         edma_write(ecc, EDMA_CCERRCLR, val);
1564                 }
1565
1566                 if (!edma_error_pending(ecc))
1567                         break;
1568                 cnt++;
1569                 if (cnt > 10)
1570                         break;
1571         }
1572         edma_write(ecc, EDMA_EEVAL, 1);
1573         return IRQ_HANDLED;
1574 }
1575
1576 static void edma_tc_set_pm_state(struct edma_tc *tc, bool enable)
1577 {
1578         struct platform_device *tc_pdev;
1579         int ret;
1580
1581         if (!IS_ENABLED(CONFIG_OF) || !tc)
1582                 return;
1583
1584         tc_pdev = of_find_device_by_node(tc->node);
1585         if (!tc_pdev) {
1586                 pr_err("%s: TPTC device is not found\n", __func__);
1587                 return;
1588         }
1589         if (!pm_runtime_enabled(&tc_pdev->dev))
1590                 pm_runtime_enable(&tc_pdev->dev);
1591
1592         if (enable)
1593                 ret = pm_runtime_get_sync(&tc_pdev->dev);
1594         else
1595                 ret = pm_runtime_put_sync(&tc_pdev->dev);
1596
1597         if (ret < 0)
1598                 pr_err("%s: pm_runtime_%s_sync() failed for %s\n", __func__,
1599                        enable ? "get" : "put", dev_name(&tc_pdev->dev));
1600 }
1601
1602 /* Alloc channel resources */
1603 static int edma_alloc_chan_resources(struct dma_chan *chan)
1604 {
1605         struct edma_chan *echan = to_edma_chan(chan);
1606         struct edma_cc *ecc = echan->ecc;
1607         struct device *dev = ecc->dev;
1608         enum dma_event_q eventq_no = EVENTQ_DEFAULT;
1609         int ret;
1610
1611         if (echan->tc) {
1612                 eventq_no = echan->tc->id;
1613         } else if (ecc->tc_list) {
1614                 /* memcpy channel */
1615                 echan->tc = &ecc->tc_list[ecc->info->default_queue];
1616                 eventq_no = echan->tc->id;
1617         }
1618
1619         ret = edma_alloc_channel(echan, eventq_no);
1620         if (ret)
1621                 return ret;
1622
1623         echan->slot[0] = edma_alloc_slot(ecc, echan->ch_num);
1624         if (echan->slot[0] < 0) {
1625                 dev_err(dev, "Entry slot allocation failed for channel %u\n",
1626                         EDMA_CHAN_SLOT(echan->ch_num));
1627                 goto err_slot;
1628         }
1629
1630         /* Set up channel -> slot mapping for the entry slot */
1631         edma_set_chmap(echan, echan->slot[0]);
1632         echan->alloced = true;
1633
1634         dev_dbg(dev, "Got eDMA channel %d for virt channel %d (%s trigger)\n",
1635                 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id,
1636                 echan->hw_triggered ? "HW" : "SW");
1637
1638         edma_tc_set_pm_state(echan->tc, true);
1639
1640         return 0;
1641
1642 err_slot:
1643         edma_free_channel(echan);
1644         return ret;
1645 }
1646
1647 /* Free channel resources */
1648 static void edma_free_chan_resources(struct dma_chan *chan)
1649 {
1650         struct edma_chan *echan = to_edma_chan(chan);
1651         struct device *dev = echan->ecc->dev;
1652         int i;
1653
1654         /* Terminate transfers */
1655         edma_stop(echan);
1656
1657         vchan_free_chan_resources(&echan->vchan);
1658
1659         /* Free EDMA PaRAM slots */
1660         for (i = 0; i < EDMA_MAX_SLOTS; i++) {
1661                 if (echan->slot[i] >= 0) {
1662                         edma_free_slot(echan->ecc, echan->slot[i]);
1663                         echan->slot[i] = -1;
1664                 }
1665         }
1666
1667         /* Set entry slot to the dummy slot */
1668         edma_set_chmap(echan, echan->ecc->dummy_slot);
1669
1670         /* Free EDMA channel */
1671         if (echan->alloced) {
1672                 edma_free_channel(echan);
1673                 echan->alloced = false;
1674         }
1675
1676         edma_tc_set_pm_state(echan->tc, false);
1677         echan->tc = NULL;
1678         echan->hw_triggered = false;
1679
1680         dev_dbg(dev, "Free eDMA channel %d for virt channel %d\n",
1681                 EDMA_CHAN_SLOT(echan->ch_num), chan->chan_id);
1682 }
1683
1684 /* Send pending descriptor to hardware */
1685 static void edma_issue_pending(struct dma_chan *chan)
1686 {
1687         struct edma_chan *echan = to_edma_chan(chan);
1688         unsigned long flags;
1689
1690         spin_lock_irqsave(&echan->vchan.lock, flags);
1691         if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
1692                 edma_execute(echan);
1693         spin_unlock_irqrestore(&echan->vchan.lock, flags);
1694 }
1695
1696 static u32 edma_residue(struct edma_desc *edesc)
1697 {
1698         bool dst = edesc->direction == DMA_DEV_TO_MEM;
1699         struct edma_pset *pset = edesc->pset;
1700         dma_addr_t done, pos;
1701         int i;
1702
1703         /*
1704          * We always read the dst/src position from the first RamPar
1705          * pset. That's the one which is active now.
1706          */
1707         pos = edma_get_position(edesc->echan->ecc, edesc->echan->slot[0], dst);
1708
1709         /*
1710          * Cyclic is simple. Just subtract pset[0].addr from pos.
1711          *
1712          * We never update edesc->residue in the cyclic case, so we
1713          * can tell the remaining room to the end of the circular
1714          * buffer.
1715          */
1716         if (edesc->cyclic) {
1717                 done = pos - pset->addr;
1718                 edesc->residue_stat = edesc->residue - done;
1719                 return edesc->residue_stat;
1720         }
1721
1722         /*
1723          * For SG operation we catch up with the last processed
1724          * status.
1725          */
1726         pset += edesc->processed_stat;
1727
1728         for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) {
1729                 /*
1730                  * If we are inside this pset address range, we know
1731                  * this is the active one. Get the current delta and
1732                  * stop walking the psets.
1733                  */
1734                 if (pos >= pset->addr && pos < pset->addr + pset->len)
1735                         return edesc->residue_stat - (pos - pset->addr);
1736
1737                 /* Otherwise mark it done and update residue_stat. */
1738                 edesc->processed_stat++;
1739                 edesc->residue_stat -= pset->len;
1740         }
1741         return edesc->residue_stat;
1742 }
1743
1744 /* Check request completion status */
1745 static enum dma_status edma_tx_status(struct dma_chan *chan,
1746                                       dma_cookie_t cookie,
1747                                       struct dma_tx_state *txstate)
1748 {
1749         struct edma_chan *echan = to_edma_chan(chan);
1750         struct virt_dma_desc *vdesc;
1751         enum dma_status ret;
1752         unsigned long flags;
1753
1754         ret = dma_cookie_status(chan, cookie, txstate);
1755         if (ret == DMA_COMPLETE || !txstate)
1756                 return ret;
1757
1758         spin_lock_irqsave(&echan->vchan.lock, flags);
1759         if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie)
1760                 txstate->residue = edma_residue(echan->edesc);
1761         else if ((vdesc = vchan_find_desc(&echan->vchan, cookie)))
1762                 txstate->residue = to_edma_desc(&vdesc->tx)->residue;
1763         spin_unlock_irqrestore(&echan->vchan.lock, flags);
1764
1765         return ret;
1766 }
1767
1768 static bool edma_is_memcpy_channel(int ch_num, s32 *memcpy_channels)
1769 {
1770         if (!memcpy_channels)
1771                 return false;
1772         while (*memcpy_channels != -1) {
1773                 if (*memcpy_channels == ch_num)
1774                         return true;
1775                 memcpy_channels++;
1776         }
1777         return false;
1778 }
1779
1780 #define EDMA_DMA_BUSWIDTHS      (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1781                                  BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
1782                                  BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
1783                                  BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1784
1785 static void edma_dma_init(struct edma_cc *ecc, bool legacy_mode)
1786 {
1787         struct dma_device *s_ddev = &ecc->dma_slave;
1788         struct dma_device *m_ddev = NULL;
1789         s32 *memcpy_channels = ecc->info->memcpy_channels;
1790         int i, j;
1791
1792         dma_cap_zero(s_ddev->cap_mask);
1793         dma_cap_set(DMA_SLAVE, s_ddev->cap_mask);
1794         dma_cap_set(DMA_CYCLIC, s_ddev->cap_mask);
1795         if (ecc->legacy_mode && !memcpy_channels) {
1796                 dev_warn(ecc->dev,
1797                          "Legacy memcpy is enabled, things might not work\n");
1798
1799                 dma_cap_set(DMA_MEMCPY, s_ddev->cap_mask);
1800                 s_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1801                 s_ddev->directions = BIT(DMA_MEM_TO_MEM);
1802         }
1803
1804         s_ddev->device_prep_slave_sg = edma_prep_slave_sg;
1805         s_ddev->device_prep_dma_cyclic = edma_prep_dma_cyclic;
1806         s_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
1807         s_ddev->device_free_chan_resources = edma_free_chan_resources;
1808         s_ddev->device_issue_pending = edma_issue_pending;
1809         s_ddev->device_tx_status = edma_tx_status;
1810         s_ddev->device_config = edma_slave_config;
1811         s_ddev->device_pause = edma_dma_pause;
1812         s_ddev->device_resume = edma_dma_resume;
1813         s_ddev->device_terminate_all = edma_terminate_all;
1814
1815         s_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1816         s_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
1817         s_ddev->directions |= (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV));
1818         s_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1819
1820         s_ddev->dev = ecc->dev;
1821         INIT_LIST_HEAD(&s_ddev->channels);
1822
1823         if (memcpy_channels) {
1824                 m_ddev = devm_kzalloc(ecc->dev, sizeof(*m_ddev), GFP_KERNEL);
1825                 ecc->dma_memcpy = m_ddev;
1826
1827                 dma_cap_zero(m_ddev->cap_mask);
1828                 dma_cap_set(DMA_MEMCPY, m_ddev->cap_mask);
1829
1830                 m_ddev->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1831                 m_ddev->device_alloc_chan_resources = edma_alloc_chan_resources;
1832                 m_ddev->device_free_chan_resources = edma_free_chan_resources;
1833                 m_ddev->device_issue_pending = edma_issue_pending;
1834                 m_ddev->device_tx_status = edma_tx_status;
1835                 m_ddev->device_config = edma_slave_config;
1836                 m_ddev->device_pause = edma_dma_pause;
1837                 m_ddev->device_resume = edma_dma_resume;
1838                 m_ddev->device_terminate_all = edma_terminate_all;
1839
1840                 m_ddev->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1841                 m_ddev->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
1842                 m_ddev->directions = BIT(DMA_MEM_TO_MEM);
1843                 m_ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1844
1845                 m_ddev->dev = ecc->dev;
1846                 INIT_LIST_HEAD(&m_ddev->channels);
1847         } else if (!ecc->legacy_mode) {
1848                 dev_info(ecc->dev, "memcpy is disabled\n");
1849         }
1850
1851         for (i = 0; i < ecc->num_channels; i++) {
1852                 struct edma_chan *echan = &ecc->slave_chans[i];
1853                 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
1854                 echan->ecc = ecc;
1855                 echan->vchan.desc_free = edma_desc_free;
1856
1857                 if (m_ddev && edma_is_memcpy_channel(i, memcpy_channels))
1858                         vchan_init(&echan->vchan, m_ddev);
1859                 else
1860                         vchan_init(&echan->vchan, s_ddev);
1861
1862                 INIT_LIST_HEAD(&echan->node);
1863                 for (j = 0; j < EDMA_MAX_SLOTS; j++)
1864                         echan->slot[j] = -1;
1865         }
1866 }
1867
1868 static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
1869                               struct edma_cc *ecc)
1870 {
1871         int i;
1872         u32 value, cccfg;
1873         s8 (*queue_priority_map)[2];
1874
1875         /* Decode the eDMA3 configuration from CCCFG register */
1876         cccfg = edma_read(ecc, EDMA_CCCFG);
1877
1878         value = GET_NUM_REGN(cccfg);
1879         ecc->num_region = BIT(value);
1880
1881         value = GET_NUM_DMACH(cccfg);
1882         ecc->num_channels = BIT(value + 1);
1883
1884         value = GET_NUM_QDMACH(cccfg);
1885         ecc->num_qchannels = value * 2;
1886
1887         value = GET_NUM_PAENTRY(cccfg);
1888         ecc->num_slots = BIT(value + 4);
1889
1890         value = GET_NUM_EVQUE(cccfg);
1891         ecc->num_tc = value + 1;
1892
1893         ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false;
1894
1895         dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
1896         dev_dbg(dev, "num_region: %u\n", ecc->num_region);
1897         dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
1898         dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels);
1899         dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
1900         dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
1901         dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
1902
1903         /* Nothing need to be done if queue priority is provided */
1904         if (pdata->queue_priority_mapping)
1905                 return 0;
1906
1907         /*
1908          * Configure TC/queue priority as follows:
1909          * Q0 - priority 0
1910          * Q1 - priority 1
1911          * Q2 - priority 2
1912          * ...
1913          * The meaning of priority numbers: 0 highest priority, 7 lowest
1914          * priority. So Q0 is the highest priority queue and the last queue has
1915          * the lowest priority.
1916          */
1917         queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8),
1918                                           GFP_KERNEL);
1919         if (!queue_priority_map)
1920                 return -ENOMEM;
1921
1922         for (i = 0; i < ecc->num_tc; i++) {
1923                 queue_priority_map[i][0] = i;
1924                 queue_priority_map[i][1] = i;
1925         }
1926         queue_priority_map[i][0] = -1;
1927         queue_priority_map[i][1] = -1;
1928
1929         pdata->queue_priority_mapping = queue_priority_map;
1930         /* Default queue has the lowest priority */
1931         pdata->default_queue = i - 1;
1932
1933         return 0;
1934 }
1935
1936 #if IS_ENABLED(CONFIG_OF)
1937 static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata,
1938                                size_t sz)
1939 {
1940         const char pname[] = "ti,edma-xbar-event-map";
1941         struct resource res;
1942         void __iomem *xbar;
1943         s16 (*xbar_chans)[2];
1944         size_t nelm = sz / sizeof(s16);
1945         u32 shift, offset, mux;
1946         int ret, i;
1947
1948         xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL);
1949         if (!xbar_chans)
1950                 return -ENOMEM;
1951
1952         ret = of_address_to_resource(dev->of_node, 1, &res);
1953         if (ret)
1954                 return -ENOMEM;
1955
1956         xbar = devm_ioremap(dev, res.start, resource_size(&res));
1957         if (!xbar)
1958                 return -ENOMEM;
1959
1960         ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans,
1961                                          nelm);
1962         if (ret)
1963                 return -EIO;
1964
1965         /* Invalidate last entry for the other user of this mess */
1966         nelm >>= 1;
1967         xbar_chans[nelm][0] = -1;
1968         xbar_chans[nelm][1] = -1;
1969
1970         for (i = 0; i < nelm; i++) {
1971                 shift = (xbar_chans[i][1] & 0x03) << 3;
1972                 offset = xbar_chans[i][1] & 0xfffffffc;
1973                 mux = readl(xbar + offset);
1974                 mux &= ~(0xff << shift);
1975                 mux |= xbar_chans[i][0] << shift;
1976                 writel(mux, (xbar + offset));
1977         }
1978
1979         pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
1980         return 0;
1981 }
1982
1983 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
1984                                                      bool legacy_mode)
1985 {
1986         struct edma_soc_info *info;
1987         struct property *prop;
1988         size_t sz;
1989         int ret;
1990
1991         info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
1992         if (!info)
1993                 return ERR_PTR(-ENOMEM);
1994
1995         if (legacy_mode) {
1996                 prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map",
1997                                         &sz);
1998                 if (prop) {
1999                         ret = edma_xbar_event_map(dev, info, sz);
2000                         if (ret)
2001                                 return ERR_PTR(ret);
2002                 }
2003                 return info;
2004         }
2005
2006         /* Get the list of channels allocated to be used for memcpy */
2007         prop = of_find_property(dev->of_node, "ti,edma-memcpy-channels", &sz);
2008         if (prop) {
2009                 const char pname[] = "ti,edma-memcpy-channels";
2010                 size_t nelm = sz / sizeof(s32);
2011                 s32 *memcpy_ch;
2012
2013                 memcpy_ch = devm_kcalloc(dev, nelm + 1, sizeof(s32),
2014                                          GFP_KERNEL);
2015                 if (!memcpy_ch)
2016                         return ERR_PTR(-ENOMEM);
2017
2018                 ret = of_property_read_u32_array(dev->of_node, pname,
2019                                                  (u32 *)memcpy_ch, nelm);
2020                 if (ret)
2021                         return ERR_PTR(ret);
2022
2023                 memcpy_ch[nelm] = -1;
2024                 info->memcpy_channels = memcpy_ch;
2025         }
2026
2027         prop = of_find_property(dev->of_node, "ti,edma-reserved-slot-ranges",
2028                                 &sz);
2029         if (prop) {
2030                 const char pname[] = "ti,edma-reserved-slot-ranges";
2031                 u32 (*tmp)[2];
2032                 s16 (*rsv_slots)[2];
2033                 size_t nelm = sz / sizeof(*tmp);
2034                 struct edma_rsv_info *rsv_info;
2035                 int i;
2036
2037                 if (!nelm)
2038                         return info;
2039
2040                 tmp = kcalloc(nelm, sizeof(*tmp), GFP_KERNEL);
2041                 if (!tmp)
2042                         return ERR_PTR(-ENOMEM);
2043
2044                 rsv_info = devm_kzalloc(dev, sizeof(*rsv_info), GFP_KERNEL);
2045                 if (!rsv_info) {
2046                         kfree(tmp);
2047                         return ERR_PTR(-ENOMEM);
2048                 }
2049
2050                 rsv_slots = devm_kcalloc(dev, nelm + 1, sizeof(*rsv_slots),
2051                                          GFP_KERNEL);
2052                 if (!rsv_slots) {
2053                         kfree(tmp);
2054                         return ERR_PTR(-ENOMEM);
2055                 }
2056
2057                 ret = of_property_read_u32_array(dev->of_node, pname,
2058                                                  (u32 *)tmp, nelm * 2);
2059                 if (ret) {
2060                         kfree(tmp);
2061                         return ERR_PTR(ret);
2062                 }
2063
2064                 for (i = 0; i < nelm; i++) {
2065                         rsv_slots[i][0] = tmp[i][0];
2066                         rsv_slots[i][1] = tmp[i][1];
2067                 }
2068                 rsv_slots[nelm][0] = -1;
2069                 rsv_slots[nelm][1] = -1;
2070
2071                 info->rsv = rsv_info;
2072                 info->rsv->rsv_slots = (const s16 (*)[2])rsv_slots;
2073
2074                 kfree(tmp);
2075         }
2076
2077         return info;
2078 }
2079
2080 static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2081                                       struct of_dma *ofdma)
2082 {
2083         struct edma_cc *ecc = ofdma->of_dma_data;
2084         struct dma_chan *chan = NULL;
2085         struct edma_chan *echan;
2086         int i;
2087
2088         if (!ecc || dma_spec->args_count < 1)
2089                 return NULL;
2090
2091         for (i = 0; i < ecc->num_channels; i++) {
2092                 echan = &ecc->slave_chans[i];
2093                 if (echan->ch_num == dma_spec->args[0]) {
2094                         chan = &echan->vchan.chan;
2095                         break;
2096                 }
2097         }
2098
2099         if (!chan)
2100                 return NULL;
2101
2102         if (echan->ecc->legacy_mode && dma_spec->args_count == 1)
2103                 goto out;
2104
2105         if (!echan->ecc->legacy_mode && dma_spec->args_count == 2 &&
2106             dma_spec->args[1] < echan->ecc->num_tc) {
2107                 echan->tc = &echan->ecc->tc_list[dma_spec->args[1]];
2108                 goto out;
2109         }
2110
2111         return NULL;
2112 out:
2113         /* The channel is going to be used as HW synchronized */
2114         echan->hw_triggered = true;
2115         return dma_get_slave_channel(chan);
2116 }
2117 #else
2118 static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
2119                                                      bool legacy_mode)
2120 {
2121         return ERR_PTR(-EINVAL);
2122 }
2123
2124 static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
2125                                       struct of_dma *ofdma)
2126 {
2127         return NULL;
2128 }
2129 #endif
2130
2131 static int edma_probe(struct platform_device *pdev)
2132 {
2133         struct edma_soc_info    *info = pdev->dev.platform_data;
2134         s8                      (*queue_priority_mapping)[2];
2135         int                     i, off, ln;
2136         const s16               (*rsv_slots)[2];
2137         const s16               (*xbar_chans)[2];
2138         int                     irq;
2139         char                    *irq_name;
2140         struct resource         *mem;
2141         struct device_node      *node = pdev->dev.of_node;
2142         struct device           *dev = &pdev->dev;
2143         struct edma_cc          *ecc;
2144         bool                    legacy_mode = true;
2145         int ret;
2146
2147         if (node) {
2148                 const struct of_device_id *match;
2149
2150                 match = of_match_node(edma_of_ids, node);
2151                 if (match && (u32)match->data == EDMA_BINDING_TPCC)
2152                         legacy_mode = false;
2153
2154                 info = edma_setup_info_from_dt(dev, legacy_mode);
2155                 if (IS_ERR(info)) {
2156                         dev_err(dev, "failed to get DT data\n");
2157                         return PTR_ERR(info);
2158                 }
2159         }
2160
2161         if (!info)
2162                 return -ENODEV;
2163
2164         pm_runtime_enable(dev);
2165         ret = pm_runtime_get_sync(dev);
2166         if (ret < 0) {
2167                 dev_err(dev, "pm_runtime_get_sync() failed\n");
2168                 return ret;
2169         }
2170
2171         ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2172         if (ret)
2173                 return ret;
2174
2175         ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
2176         if (!ecc) {
2177                 dev_err(dev, "Can't allocate controller\n");
2178                 return -ENOMEM;
2179         }
2180
2181         ecc->dev = dev;
2182         ecc->id = pdev->id;
2183         ecc->legacy_mode = legacy_mode;
2184         /* When booting with DT the pdev->id is -1 */
2185         if (ecc->id < 0)
2186                 ecc->id = 0;
2187
2188         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc");
2189         if (!mem) {
2190                 dev_dbg(dev, "mem resource not found, using index 0\n");
2191                 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2192                 if (!mem) {
2193                         dev_err(dev, "no mem resource?\n");
2194                         return -ENODEV;
2195                 }
2196         }
2197         ecc->base = devm_ioremap_resource(dev, mem);
2198         if (IS_ERR(ecc->base))
2199                 return PTR_ERR(ecc->base);
2200
2201         platform_set_drvdata(pdev, ecc);
2202
2203         /* Get eDMA3 configuration from IP */
2204         ret = edma_setup_from_hw(dev, info, ecc);
2205         if (ret)
2206                 return ret;
2207
2208         /* Allocate memory based on the information we got from the IP */
2209         ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels,
2210                                         sizeof(*ecc->slave_chans), GFP_KERNEL);
2211         if (!ecc->slave_chans)
2212                 return -ENOMEM;
2213
2214         ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
2215                                        sizeof(unsigned long), GFP_KERNEL);
2216         if (!ecc->slot_inuse)
2217                 return -ENOMEM;
2218
2219         ecc->default_queue = info->default_queue;
2220
2221         if (info->rsv) {
2222                 /* Set the reserved slots in inuse list */
2223                 rsv_slots = info->rsv->rsv_slots;
2224                 if (rsv_slots) {
2225                         for (i = 0; rsv_slots[i][0] != -1; i++) {
2226                                 off = rsv_slots[i][0];
2227                                 ln = rsv_slots[i][1];
2228                                 set_bits(off, ln, ecc->slot_inuse);
2229                         }
2230                 }
2231         }
2232
2233         for (i = 0; i < ecc->num_slots; i++) {
2234                 /* Reset only unused - not reserved - paRAM slots */
2235                 if (!test_bit(i, ecc->slot_inuse))
2236                         edma_write_slot(ecc, i, &dummy_paramset);
2237         }
2238
2239         /* Clear the xbar mapped channels in unused list */
2240         xbar_chans = info->xbar_chans;
2241         if (xbar_chans) {
2242                 for (i = 0; xbar_chans[i][1] != -1; i++) {
2243                         off = xbar_chans[i][1];
2244                 }
2245         }
2246
2247         irq = platform_get_irq_byname(pdev, "edma3_ccint");
2248         if (irq < 0 && node)
2249                 irq = irq_of_parse_and_map(node, 0);
2250
2251         if (irq >= 0) {
2252                 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint",
2253                                           dev_name(dev));
2254                 ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
2255                                        ecc);
2256                 if (ret) {
2257                         dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
2258                         return ret;
2259                 }
2260         }
2261
2262         irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
2263         if (irq < 0 && node)
2264                 irq = irq_of_parse_and_map(node, 2);
2265
2266         if (irq >= 0) {
2267                 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint",
2268                                           dev_name(dev));
2269                 ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
2270                                        ecc);
2271                 if (ret) {
2272                         dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
2273                         return ret;
2274                 }
2275         }
2276
2277         ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
2278         if (ecc->dummy_slot < 0) {
2279                 dev_err(dev, "Can't allocate PaRAM dummy slot\n");
2280                 return ecc->dummy_slot;
2281         }
2282
2283         queue_priority_mapping = info->queue_priority_mapping;
2284
2285         if (!ecc->legacy_mode) {
2286                 int lowest_priority = 0;
2287                 struct of_phandle_args tc_args;
2288
2289                 ecc->tc_list = devm_kcalloc(dev, ecc->num_tc,
2290                                             sizeof(*ecc->tc_list), GFP_KERNEL);
2291                 if (!ecc->tc_list) {
2292                         ret = -ENOMEM;
2293                         goto err_reg1;
2294                 }
2295
2296                 for (i = 0;; i++) {
2297                         ret = of_parse_phandle_with_fixed_args(node, "ti,tptcs",
2298                                                                1, i, &tc_args);
2299                         if (ret || i == ecc->num_tc)
2300                                 break;
2301
2302                         ecc->tc_list[i].node = tc_args.np;
2303                         ecc->tc_list[i].id = i;
2304                         queue_priority_mapping[i][1] = tc_args.args[0];
2305                         if (queue_priority_mapping[i][1] > lowest_priority) {
2306                                 lowest_priority = queue_priority_mapping[i][1];
2307                                 info->default_queue = i;
2308                         }
2309                 }
2310         }
2311
2312         /* Event queue priority mapping */
2313         for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2314                 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2315                                               queue_priority_mapping[i][1]);
2316
2317         for (i = 0; i < ecc->num_region; i++) {
2318                 edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0);
2319                 edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0);
2320                 edma_write_array(ecc, EDMA_QRAE, i, 0x0);
2321         }
2322         ecc->info = info;
2323
2324         /* Init the dma device and channels */
2325         edma_dma_init(ecc, legacy_mode);
2326
2327         for (i = 0; i < ecc->num_channels; i++) {
2328                 /* Assign all channels to the default queue */
2329                 edma_assign_channel_eventq(&ecc->slave_chans[i],
2330                                            info->default_queue);
2331                 /* Set entry slot to the dummy slot */
2332                 edma_set_chmap(&ecc->slave_chans[i], ecc->dummy_slot);
2333         }
2334
2335         ret = dma_async_device_register(&ecc->dma_slave);
2336         if (ret) {
2337                 dev_err(dev, "slave ddev registration failed (%d)\n", ret);
2338                 goto err_reg1;
2339         }
2340
2341         if (ecc->dma_memcpy) {
2342                 ret = dma_async_device_register(ecc->dma_memcpy);
2343                 if (ret) {
2344                         dev_err(dev, "memcpy ddev registration failed (%d)\n",
2345                                 ret);
2346                         dma_async_device_unregister(&ecc->dma_slave);
2347                         goto err_reg1;
2348                 }
2349         }
2350
2351         if (node)
2352                 of_dma_controller_register(node, of_edma_xlate, ecc);
2353
2354         dev_info(dev, "TI EDMA DMA engine driver\n");
2355
2356         return 0;
2357
2358 err_reg1:
2359         edma_free_slot(ecc, ecc->dummy_slot);
2360         return ret;
2361 }
2362
2363 static int edma_remove(struct platform_device *pdev)
2364 {
2365         struct device *dev = &pdev->dev;
2366         struct edma_cc *ecc = dev_get_drvdata(dev);
2367
2368         if (dev->of_node)
2369                 of_dma_controller_free(dev->of_node);
2370         dma_async_device_unregister(&ecc->dma_slave);
2371         if (ecc->dma_memcpy)
2372                 dma_async_device_unregister(ecc->dma_memcpy);
2373         edma_free_slot(ecc, ecc->dummy_slot);
2374
2375         return 0;
2376 }
2377
2378 #ifdef CONFIG_PM_SLEEP
2379 static int edma_pm_suspend(struct device *dev)
2380 {
2381         struct edma_cc *ecc = dev_get_drvdata(dev);
2382         struct edma_chan *echan = ecc->slave_chans;
2383         int i;
2384
2385         for (i = 0; i < ecc->num_channels; i++) {
2386                 if (echan[i].alloced) {
2387                         edma_setup_interrupt(&echan[i], false);
2388                         edma_tc_set_pm_state(echan[i].tc, false);
2389                 }
2390         }
2391
2392         return 0;
2393 }
2394
2395 static int edma_pm_resume(struct device *dev)
2396 {
2397         struct edma_cc *ecc = dev_get_drvdata(dev);
2398         struct edma_chan *echan = ecc->slave_chans;
2399         int i;
2400         s8 (*queue_priority_mapping)[2];
2401
2402         queue_priority_mapping = ecc->info->queue_priority_mapping;
2403
2404         /* Event queue priority mapping */
2405         for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2406                 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2407                                               queue_priority_mapping[i][1]);
2408
2409         for (i = 0; i < ecc->num_channels; i++) {
2410                 if (echan[i].alloced) {
2411                         /* ensure access through shadow region 0 */
2412                         edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5,
2413                                        BIT(i & 0x1f));
2414
2415                         edma_setup_interrupt(&echan[i], true);
2416
2417                         /* Set up channel -> slot mapping for the entry slot */
2418                         edma_set_chmap(&echan[i], echan[i].slot[0]);
2419
2420                         edma_tc_set_pm_state(echan[i].tc, true);
2421                 }
2422         }
2423
2424         return 0;
2425 }
2426 #endif
2427
2428 static const struct dev_pm_ops edma_pm_ops = {
2429         SET_LATE_SYSTEM_SLEEP_PM_OPS(edma_pm_suspend, edma_pm_resume)
2430 };
2431
2432 static struct platform_driver edma_driver = {
2433         .probe          = edma_probe,
2434         .remove         = edma_remove,
2435         .driver = {
2436                 .name   = "edma",
2437                 .pm     = &edma_pm_ops,
2438                 .of_match_table = edma_of_ids,
2439         },
2440 };
2441
2442 static int edma_tptc_probe(struct platform_device *pdev)
2443 {
2444         return 0;
2445 }
2446
2447 static struct platform_driver edma_tptc_driver = {
2448         .probe          = edma_tptc_probe,
2449         .driver = {
2450                 .name   = "edma3-tptc",
2451                 .of_match_table = edma_tptc_of_ids,
2452         },
2453 };
2454
2455 bool edma_filter_fn(struct dma_chan *chan, void *param)
2456 {
2457         bool match = false;
2458
2459         if (chan->device->dev->driver == &edma_driver.driver) {
2460                 struct edma_chan *echan = to_edma_chan(chan);
2461                 unsigned ch_req = *(unsigned *)param;
2462                 if (ch_req == echan->ch_num) {
2463                         /* The channel is going to be used as HW synchronized */
2464                         echan->hw_triggered = true;
2465                         match = true;
2466                 }
2467         }
2468         return match;
2469 }
2470 EXPORT_SYMBOL(edma_filter_fn);
2471
2472 static int edma_init(void)
2473 {
2474         int ret;
2475
2476         ret = platform_driver_register(&edma_tptc_driver);
2477         if (ret)
2478                 return ret;
2479
2480         return platform_driver_register(&edma_driver);
2481 }
2482 subsys_initcall(edma_init);
2483
2484 static void __exit edma_exit(void)
2485 {
2486         platform_driver_unregister(&edma_driver);
2487         platform_driver_unregister(&edma_tptc_driver);
2488 }
2489 module_exit(edma_exit);
2490
2491 MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
2492 MODULE_DESCRIPTION("TI EDMA DMA engine driver");
2493 MODULE_LICENSE("GPL v2");