1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA core driver
6 * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
9 #include <linux/module.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/dmaengine.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/dma/edma.h>
18 #include <linux/dma-mapping.h>
20 #include "dw-edma-core.h"
21 #include "dw-edma-v0-core.h"
22 #include "../dmaengine.h"
23 #include "../virt-dma.h"
26 struct device *dchan2dev(struct dma_chan *dchan)
28 return &dchan->dev->device;
32 struct device *chan2dev(struct dw_edma_chan *chan)
34 return &chan->vc.chan.dev->device;
38 struct dw_edma_desc *vd2dw_edma_desc(struct virt_dma_desc *vd)
40 return container_of(vd, struct dw_edma_desc, vd);
43 static struct dw_edma_burst *dw_edma_alloc_burst(struct dw_edma_chunk *chunk)
45 struct dw_edma_burst *burst;
47 burst = kzalloc(sizeof(*burst), GFP_NOWAIT);
51 INIT_LIST_HEAD(&burst->list);
53 /* Create and add new element into the linked list */
54 chunk->bursts_alloc++;
55 list_add_tail(&burst->list, &chunk->burst->list);
58 chunk->bursts_alloc = 0;
65 static struct dw_edma_chunk *dw_edma_alloc_chunk(struct dw_edma_desc *desc)
67 struct dw_edma_chan *chan = desc->chan;
68 struct dw_edma *dw = chan->chip->dw;
69 struct dw_edma_chunk *chunk;
71 chunk = kzalloc(sizeof(*chunk), GFP_NOWAIT);
75 INIT_LIST_HEAD(&chunk->list);
77 /* Toggling change bit (CB) in each chunk, this is a mechanism to
78 * inform the eDMA HW block that this is a new linked list ready
80 * - Odd chunks originate CB equal to 0
81 * - Even chunks originate CB equal to 1
83 chunk->cb = !(desc->chunks_alloc % 2);
84 chunk->ll_region.paddr = dw->ll_region.paddr + chan->ll_off;
85 chunk->ll_region.vaddr = dw->ll_region.vaddr + chan->ll_off;
88 /* Create and add new element into the linked list */
89 if (!dw_edma_alloc_burst(chunk)) {
94 list_add_tail(&chunk->list, &desc->chunk->list);
98 desc->chunks_alloc = 0;
105 static struct dw_edma_desc *dw_edma_alloc_desc(struct dw_edma_chan *chan)
107 struct dw_edma_desc *desc;
109 desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
114 if (!dw_edma_alloc_chunk(desc)) {
122 static void dw_edma_free_burst(struct dw_edma_chunk *chunk)
124 struct dw_edma_burst *child, *_next;
126 /* Remove all the list elements */
127 list_for_each_entry_safe(child, _next, &chunk->burst->list, list) {
128 list_del(&child->list);
130 chunk->bursts_alloc--;
133 /* Remove the list head */
138 static void dw_edma_free_chunk(struct dw_edma_desc *desc)
140 struct dw_edma_chunk *child, *_next;
145 /* Remove all the list elements */
146 list_for_each_entry_safe(child, _next, &desc->chunk->list, list) {
147 dw_edma_free_burst(child);
148 list_del(&child->list);
150 desc->chunks_alloc--;
153 /* Remove the list head */
158 static void dw_edma_free_desc(struct dw_edma_desc *desc)
160 dw_edma_free_chunk(desc);
164 static void vchan_free_desc(struct virt_dma_desc *vdesc)
166 dw_edma_free_desc(vd2dw_edma_desc(vdesc));
169 static int dw_edma_start_transfer(struct dw_edma_chan *chan)
171 struct dw_edma_chunk *child;
172 struct dw_edma_desc *desc;
173 struct virt_dma_desc *vd;
175 vd = vchan_next_desc(&chan->vc);
179 desc = vd2dw_edma_desc(vd);
183 child = list_first_entry_or_null(&desc->chunk->list,
184 struct dw_edma_chunk, list);
188 dw_edma_v0_core_start(child, !desc->xfer_sz);
189 desc->xfer_sz += child->ll_region.sz;
190 dw_edma_free_burst(child);
191 list_del(&child->list);
193 desc->chunks_alloc--;
198 static int dw_edma_device_config(struct dma_chan *dchan,
199 struct dma_slave_config *config)
201 struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
203 memcpy(&chan->config, config, sizeof(*config));
204 chan->configured = true;
209 static int dw_edma_device_pause(struct dma_chan *dchan)
211 struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
214 if (!chan->configured)
216 else if (chan->status != EDMA_ST_BUSY)
218 else if (chan->request != EDMA_REQ_NONE)
221 chan->request = EDMA_REQ_PAUSE;
226 static int dw_edma_device_resume(struct dma_chan *dchan)
228 struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
231 if (!chan->configured) {
233 } else if (chan->status != EDMA_ST_PAUSE) {
235 } else if (chan->request != EDMA_REQ_NONE) {
238 chan->status = EDMA_ST_BUSY;
239 dw_edma_start_transfer(chan);
245 static int dw_edma_device_terminate_all(struct dma_chan *dchan)
247 struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
251 if (!chan->configured) {
253 } else if (chan->status == EDMA_ST_PAUSE) {
254 chan->status = EDMA_ST_IDLE;
255 chan->configured = false;
256 } else if (chan->status == EDMA_ST_IDLE) {
257 chan->configured = false;
258 } else if (dw_edma_v0_core_ch_status(chan) == DMA_COMPLETE) {
260 * The channel is in a false BUSY state, probably didn't
261 * receive or lost an interrupt
263 chan->status = EDMA_ST_IDLE;
264 chan->configured = false;
265 } else if (chan->request > EDMA_REQ_PAUSE) {
268 chan->request = EDMA_REQ_STOP;
274 static void dw_edma_device_issue_pending(struct dma_chan *dchan)
276 struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
279 if (!chan->configured)
282 spin_lock_irqsave(&chan->vc.lock, flags);
283 if (vchan_issue_pending(&chan->vc) && chan->request == EDMA_REQ_NONE &&
284 chan->status == EDMA_ST_IDLE) {
285 chan->status = EDMA_ST_BUSY;
286 dw_edma_start_transfer(chan);
288 spin_unlock_irqrestore(&chan->vc.lock, flags);
291 static enum dma_status
292 dw_edma_device_tx_status(struct dma_chan *dchan, dma_cookie_t cookie,
293 struct dma_tx_state *txstate)
295 struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
296 struct dw_edma_desc *desc;
297 struct virt_dma_desc *vd;
302 ret = dma_cookie_status(dchan, cookie, txstate);
303 if (ret == DMA_COMPLETE)
306 if (ret == DMA_IN_PROGRESS && chan->status == EDMA_ST_PAUSE)
312 spin_lock_irqsave(&chan->vc.lock, flags);
313 vd = vchan_find_desc(&chan->vc, cookie);
315 desc = vd2dw_edma_desc(vd);
317 residue = desc->alloc_sz - desc->xfer_sz;
319 spin_unlock_irqrestore(&chan->vc.lock, flags);
322 dma_set_residue(txstate, residue);
327 static struct dma_async_tx_descriptor *
328 dw_edma_device_transfer(struct dw_edma_transfer *xfer)
330 struct dw_edma_chan *chan = dchan2dw_edma_chan(xfer->dchan);
331 enum dma_transfer_direction dir = xfer->direction;
332 phys_addr_t src_addr, dst_addr;
333 struct scatterlist *sg = NULL;
334 struct dw_edma_chunk *chunk;
335 struct dw_edma_burst *burst;
336 struct dw_edma_desc *desc;
340 if (!chan->configured)
343 switch (chan->config.direction) {
344 case DMA_DEV_TO_MEM: /* local dma */
345 if (dir == DMA_DEV_TO_MEM && chan->dir == EDMA_DIR_READ)
348 case DMA_MEM_TO_DEV: /* local dma */
349 if (dir == DMA_MEM_TO_DEV && chan->dir == EDMA_DIR_WRITE)
352 default: /* remote dma */
353 if (dir == DMA_MEM_TO_DEV && chan->dir == EDMA_DIR_READ)
355 if (dir == DMA_DEV_TO_MEM && chan->dir == EDMA_DIR_WRITE)
361 if (!xfer->xfer.cyclic.len || !xfer->xfer.cyclic.cnt)
364 if (xfer->xfer.sg.len < 1)
368 desc = dw_edma_alloc_desc(chan);
372 chunk = dw_edma_alloc_chunk(desc);
373 if (unlikely(!chunk))
376 src_addr = chan->config.src_addr;
377 dst_addr = chan->config.dst_addr;
380 cnt = xfer->xfer.cyclic.cnt;
382 cnt = xfer->xfer.sg.len;
383 sg = xfer->xfer.sg.sgl;
386 for (i = 0; i < cnt; i++) {
387 if (!xfer->cyclic && !sg)
390 if (chunk->bursts_alloc == chan->ll_max) {
391 chunk = dw_edma_alloc_chunk(desc);
392 if (unlikely(!chunk))
396 burst = dw_edma_alloc_burst(chunk);
397 if (unlikely(!burst))
401 burst->sz = xfer->xfer.cyclic.len;
403 burst->sz = sg_dma_len(sg);
405 chunk->ll_region.sz += burst->sz;
406 desc->alloc_sz += burst->sz;
408 if (dir == DMA_DEV_TO_MEM) {
409 burst->sar = src_addr;
411 burst->dar = xfer->xfer.cyclic.paddr;
413 burst->dar = dst_addr;
414 /* Unlike the typical assumption by other
415 * drivers/IPs the peripheral memory isn't
416 * a FIFO memory, in this case, it's a
417 * linear memory and that why the source
418 * and destination addresses are increased
419 * by the same portion (data length)
423 burst->dar = dst_addr;
425 burst->sar = xfer->xfer.cyclic.paddr;
427 burst->sar = src_addr;
428 /* Unlike the typical assumption by other
429 * drivers/IPs the peripheral memory isn't
430 * a FIFO memory, in this case, it's a
431 * linear memory and that why the source
432 * and destination addresses are increased
433 * by the same portion (data length)
439 src_addr += sg_dma_len(sg);
440 dst_addr += sg_dma_len(sg);
445 return vchan_tx_prep(&chan->vc, &desc->vd, xfer->flags);
449 dw_edma_free_desc(desc);
454 static struct dma_async_tx_descriptor *
455 dw_edma_device_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
457 enum dma_transfer_direction direction,
458 unsigned long flags, void *context)
460 struct dw_edma_transfer xfer;
463 xfer.direction = direction;
464 xfer.xfer.sg.sgl = sgl;
465 xfer.xfer.sg.len = len;
469 return dw_edma_device_transfer(&xfer);
472 static struct dma_async_tx_descriptor *
473 dw_edma_device_prep_dma_cyclic(struct dma_chan *dchan, dma_addr_t paddr,
474 size_t len, size_t count,
475 enum dma_transfer_direction direction,
478 struct dw_edma_transfer xfer;
481 xfer.direction = direction;
482 xfer.xfer.cyclic.paddr = paddr;
483 xfer.xfer.cyclic.len = len;
484 xfer.xfer.cyclic.cnt = count;
488 return dw_edma_device_transfer(&xfer);
491 static void dw_edma_done_interrupt(struct dw_edma_chan *chan)
493 struct dw_edma_desc *desc;
494 struct virt_dma_desc *vd;
497 dw_edma_v0_core_clear_done_int(chan);
499 spin_lock_irqsave(&chan->vc.lock, flags);
500 vd = vchan_next_desc(&chan->vc);
502 switch (chan->request) {
504 desc = vd2dw_edma_desc(vd);
505 if (!desc->chunks_alloc) {
507 vchan_cookie_complete(vd);
510 /* Continue transferring if there are remaining chunks or issued requests.
512 chan->status = dw_edma_start_transfer(chan) ? EDMA_ST_BUSY : EDMA_ST_IDLE;
517 vchan_cookie_complete(vd);
518 chan->request = EDMA_REQ_NONE;
519 chan->status = EDMA_ST_IDLE;
523 chan->request = EDMA_REQ_NONE;
524 chan->status = EDMA_ST_PAUSE;
531 spin_unlock_irqrestore(&chan->vc.lock, flags);
534 static void dw_edma_abort_interrupt(struct dw_edma_chan *chan)
536 struct virt_dma_desc *vd;
539 dw_edma_v0_core_clear_abort_int(chan);
541 spin_lock_irqsave(&chan->vc.lock, flags);
542 vd = vchan_next_desc(&chan->vc);
545 vchan_cookie_complete(vd);
547 spin_unlock_irqrestore(&chan->vc.lock, flags);
548 chan->request = EDMA_REQ_NONE;
549 chan->status = EDMA_ST_IDLE;
552 static irqreturn_t dw_edma_interrupt(int irq, void *data, bool write)
554 struct dw_edma_irq *dw_irq = data;
555 struct dw_edma *dw = dw_irq->dw;
556 unsigned long total, pos, val;
561 total = dw->wr_ch_cnt;
563 mask = dw_irq->wr_mask;
565 total = dw->rd_ch_cnt;
567 mask = dw_irq->rd_mask;
570 val = dw_edma_v0_core_status_done_int(dw, write ?
574 for_each_set_bit(pos, &val, total) {
575 struct dw_edma_chan *chan = &dw->chan[pos + off];
577 dw_edma_done_interrupt(chan);
580 val = dw_edma_v0_core_status_abort_int(dw, write ?
584 for_each_set_bit(pos, &val, total) {
585 struct dw_edma_chan *chan = &dw->chan[pos + off];
587 dw_edma_abort_interrupt(chan);
593 static inline irqreturn_t dw_edma_interrupt_write(int irq, void *data)
595 return dw_edma_interrupt(irq, data, true);
598 static inline irqreturn_t dw_edma_interrupt_read(int irq, void *data)
600 return dw_edma_interrupt(irq, data, false);
603 static irqreturn_t dw_edma_interrupt_common(int irq, void *data)
605 dw_edma_interrupt(irq, data, true);
606 dw_edma_interrupt(irq, data, false);
611 static int dw_edma_alloc_chan_resources(struct dma_chan *dchan)
613 struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
615 if (chan->status != EDMA_ST_IDLE)
618 pm_runtime_get(chan->chip->dev);
623 static void dw_edma_free_chan_resources(struct dma_chan *dchan)
625 unsigned long timeout = jiffies + msecs_to_jiffies(5000);
626 struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
629 while (time_before(jiffies, timeout)) {
630 ret = dw_edma_device_terminate_all(dchan);
634 if (time_after_eq(jiffies, timeout))
640 pm_runtime_put(chan->chip->dev);
643 static int dw_edma_channel_setup(struct dw_edma_chip *chip, bool write,
644 u32 wr_alloc, u32 rd_alloc)
646 struct dw_edma_region *dt_region;
647 struct device *dev = chip->dev;
648 struct dw_edma *dw = chip->dw;
649 struct dw_edma_chan *chan;
650 size_t ll_chunk, dt_chunk;
651 struct dw_edma_irq *irq;
652 struct dma_device *dma;
653 u32 i, j, cnt, ch_cnt;
654 u32 alloc, off_alloc;
658 ch_cnt = dw->wr_ch_cnt + dw->rd_ch_cnt;
659 ll_chunk = dw->ll_region.sz;
660 dt_chunk = dw->dt_region.sz;
662 /* Calculate linked list chunk for each channel */
663 ll_chunk /= roundup_pow_of_two(ch_cnt);
665 /* Calculate linked list chunk for each channel */
666 dt_chunk /= roundup_pow_of_two(ch_cnt);
679 off_alloc = wr_alloc;
682 INIT_LIST_HEAD(&dma->channels);
683 for (j = 0; (alloc || dw->nr_irqs == 1) && j < cnt; j++, i++) {
686 dt_region = devm_kzalloc(dev, sizeof(*dt_region), GFP_KERNEL);
690 chan->vc.chan.private = dt_region;
694 chan->dir = write ? EDMA_DIR_WRITE : EDMA_DIR_READ;
695 chan->configured = false;
696 chan->request = EDMA_REQ_NONE;
697 chan->status = EDMA_ST_IDLE;
699 chan->ll_off = (ll_chunk * i);
700 chan->ll_max = (ll_chunk / EDMA_LL_SZ) - 1;
702 chan->dt_off = (dt_chunk * i);
704 dev_vdbg(dev, "L. List:\tChannel %s[%u] off=0x%.8lx, max_cnt=%u\n",
705 write ? "write" : "read", j,
706 chan->ll_off, chan->ll_max);
708 if (dw->nr_irqs == 1)
711 pos = off_alloc + (j % alloc);
716 irq->wr_mask |= BIT(j);
718 irq->rd_mask |= BIT(j);
721 memcpy(&chan->msi, &irq->msi, sizeof(chan->msi));
723 dev_vdbg(dev, "MSI:\t\tChannel %s[%u] addr=0x%.8x%.8x, data=0x%.8x\n",
724 write ? "write" : "read", j,
725 chan->msi.address_hi, chan->msi.address_lo,
728 chan->vc.desc_free = vchan_free_desc;
729 vchan_init(&chan->vc, dma);
731 dt_region->paddr = dw->dt_region.paddr + chan->dt_off;
732 dt_region->vaddr = dw->dt_region.vaddr + chan->dt_off;
733 dt_region->sz = dt_chunk;
735 dev_vdbg(dev, "Data:\tChannel %s[%u] off=0x%.8lx\n",
736 write ? "write" : "read", j, chan->dt_off);
738 dw_edma_v0_core_device_config(chan);
741 /* Set DMA channel capabilities */
742 dma_cap_zero(dma->cap_mask);
743 dma_cap_set(DMA_SLAVE, dma->cap_mask);
744 dma_cap_set(DMA_CYCLIC, dma->cap_mask);
745 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
746 dma->directions = BIT(write ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV);
747 dma->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
748 dma->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
749 dma->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
752 /* Set DMA channel callbacks */
753 dma->dev = chip->dev;
754 dma->device_alloc_chan_resources = dw_edma_alloc_chan_resources;
755 dma->device_free_chan_resources = dw_edma_free_chan_resources;
756 dma->device_config = dw_edma_device_config;
757 dma->device_pause = dw_edma_device_pause;
758 dma->device_resume = dw_edma_device_resume;
759 dma->device_terminate_all = dw_edma_device_terminate_all;
760 dma->device_issue_pending = dw_edma_device_issue_pending;
761 dma->device_tx_status = dw_edma_device_tx_status;
762 dma->device_prep_slave_sg = dw_edma_device_prep_slave_sg;
763 dma->device_prep_dma_cyclic = dw_edma_device_prep_dma_cyclic;
765 dma_set_max_seg_size(dma->dev, U32_MAX);
767 /* Register DMA device */
768 err = dma_async_device_register(dma);
773 static inline void dw_edma_dec_irq_alloc(int *nr_irqs, u32 *alloc, u16 cnt)
775 if (*nr_irqs && *alloc < cnt) {
781 static inline void dw_edma_add_irq_mask(u32 *mask, u32 alloc, u16 cnt)
783 while (*mask * alloc < cnt)
787 static int dw_edma_irq_request(struct dw_edma_chip *chip,
788 u32 *wr_alloc, u32 *rd_alloc)
790 struct device *dev = chip->dev;
791 struct dw_edma *dw = chip->dw;
798 ch_cnt = dw->wr_ch_cnt + dw->rd_ch_cnt;
803 if (dw->nr_irqs == 1) {
804 /* Common IRQ shared among all channels */
805 irq = dw->ops->irq_vector(dev, 0);
806 err = request_irq(irq, dw_edma_interrupt_common,
807 IRQF_SHARED, dw->name, &dw->irq[0]);
813 if (irq_get_msi_desc(irq))
814 get_cached_msi_msg(irq, &dw->irq[0].msi);
816 /* Distribute IRQs equally among all channels */
817 int tmp = dw->nr_irqs;
819 while (tmp && (*wr_alloc + *rd_alloc) < ch_cnt) {
820 dw_edma_dec_irq_alloc(&tmp, wr_alloc, dw->wr_ch_cnt);
821 dw_edma_dec_irq_alloc(&tmp, rd_alloc, dw->rd_ch_cnt);
824 dw_edma_add_irq_mask(&wr_mask, *wr_alloc, dw->wr_ch_cnt);
825 dw_edma_add_irq_mask(&rd_mask, *rd_alloc, dw->rd_ch_cnt);
827 for (i = 0; i < (*wr_alloc + *rd_alloc); i++) {
828 irq = dw->ops->irq_vector(dev, i);
829 err = request_irq(irq,
831 dw_edma_interrupt_write :
832 dw_edma_interrupt_read,
833 IRQF_SHARED, dw->name,
840 if (irq_get_msi_desc(irq))
841 get_cached_msi_msg(irq, &dw->irq[i].msi);
850 int dw_edma_probe(struct dw_edma_chip *chip)
866 if (!dw || !dw->irq || !dw->ops || !dw->ops->irq_vector)
869 raw_spin_lock_init(&dw->lock);
871 /* Find out how many write channels are supported by hardware */
872 dw->wr_ch_cnt = dw_edma_v0_core_ch_count(dw, EDMA_DIR_WRITE);
876 /* Find out how many read channels are supported by hardware */
877 dw->rd_ch_cnt = dw_edma_v0_core_ch_count(dw, EDMA_DIR_READ);
881 dev_vdbg(dev, "Channels:\twrite=%d, read=%d\n",
882 dw->wr_ch_cnt, dw->rd_ch_cnt);
884 /* Allocate channels */
885 dw->chan = devm_kcalloc(dev, dw->wr_ch_cnt + dw->rd_ch_cnt,
886 sizeof(*dw->chan), GFP_KERNEL);
890 snprintf(dw->name, sizeof(dw->name), "dw-edma-core:%d", chip->id);
892 /* Disable eDMA, only to establish the ideal initial conditions */
893 dw_edma_v0_core_off(dw);
896 err = dw_edma_irq_request(chip, &wr_alloc, &rd_alloc);
900 /* Setup write channels */
901 err = dw_edma_channel_setup(chip, true, wr_alloc, rd_alloc);
905 /* Setup read channels */
906 err = dw_edma_channel_setup(chip, false, wr_alloc, rd_alloc);
910 /* Power management */
911 pm_runtime_enable(dev);
913 /* Turn debugfs on */
914 dw_edma_v0_core_debugfs_on(chip);
919 for (i = (dw->nr_irqs - 1); i >= 0; i--)
920 free_irq(dw->ops->irq_vector(dev, i), &dw->irq[i]);
926 EXPORT_SYMBOL_GPL(dw_edma_probe);
928 int dw_edma_remove(struct dw_edma_chip *chip)
930 struct dw_edma_chan *chan, *_chan;
931 struct device *dev = chip->dev;
932 struct dw_edma *dw = chip->dw;
936 dw_edma_v0_core_off(dw);
939 for (i = (dw->nr_irqs - 1); i >= 0; i--)
940 free_irq(dw->ops->irq_vector(dev, i), &dw->irq[i]);
942 /* Power management */
943 pm_runtime_disable(dev);
945 /* Deregister eDMA device */
946 dma_async_device_unregister(&dw->wr_edma);
947 list_for_each_entry_safe(chan, _chan, &dw->wr_edma.channels,
948 vc.chan.device_node) {
949 tasklet_kill(&chan->vc.task);
950 list_del(&chan->vc.chan.device_node);
953 dma_async_device_unregister(&dw->rd_edma);
954 list_for_each_entry_safe(chan, _chan, &dw->rd_edma.channels,
955 vc.chan.device_node) {
956 tasklet_kill(&chan->vc.task);
957 list_del(&chan->vc.chan.device_node);
960 /* Turn debugfs off */
961 dw_edma_v0_core_debugfs_off();
965 EXPORT_SYMBOL_GPL(dw_edma_remove);
967 MODULE_LICENSE("GPL v2");
968 MODULE_DESCRIPTION("Synopsys DesignWare eDMA controller core driver");
969 MODULE_AUTHOR("Gustavo Pimentel <gustavo.pimentel@synopsys.com>");