1 #include <linux/delay.h>
2 #include <linux/dmaengine.h>
3 #include <linux/dma-mapping.h>
4 #include <linux/platform_device.h>
5 #include <linux/module.h>
7 #include <linux/slab.h>
8 #include <linux/of_dma.h>
9 #include <linux/of_irq.h>
10 #include <linux/dmapool.h>
11 #include <linux/interrupt.h>
12 #include <linux/of_address.h>
13 #include <linux/pm_runtime.h>
14 #include "dmaengine.h"
17 #define DESC_TYPE_HOST 0x10
18 #define DESC_TYPE_TEARD 0x13
20 #define TD_DESC_IS_RX (1 << 16)
21 #define TD_DESC_DMA_NUM 10
23 #define DESC_LENGTH_BITS_NUM 21
25 #define DESC_TYPE_USB (5 << 26)
26 #define DESC_PD_COMPLETE (1 << 31)
30 #define DMA_TXGCR(x) (0x800 + (x) * 0x20)
31 #define DMA_RXGCR(x) (0x808 + (x) * 0x20)
34 #define GCR_CHAN_ENABLE (1 << 31)
35 #define GCR_TEARDOWN (1 << 30)
36 #define GCR_STARV_RETRY (1 << 24)
37 #define GCR_DESC_TYPE_HOST (1 << 14)
40 #define DMA_SCHED_CTRL 0
41 #define DMA_SCHED_CTRL_EN (1 << 31)
42 #define DMA_SCHED_WORD(x) ((x) * 4 + 0x800)
44 #define SCHED_ENTRY0_CHAN(x) ((x) << 0)
45 #define SCHED_ENTRY0_IS_RX (1 << 7)
47 #define SCHED_ENTRY1_CHAN(x) ((x) << 8)
48 #define SCHED_ENTRY1_IS_RX (1 << 15)
50 #define SCHED_ENTRY2_CHAN(x) ((x) << 16)
51 #define SCHED_ENTRY2_IS_RX (1 << 23)
53 #define SCHED_ENTRY3_CHAN(x) ((x) << 24)
54 #define SCHED_ENTRY3_IS_RX (1 << 31)
57 /* 4 KiB of memory for descriptors, 2 for each endpoint */
58 #define ALLOC_DECS_NUM 128
60 #define TOTAL_DESCS_NUM (ALLOC_DECS_NUM * DESCS_AREAS)
61 #define QMGR_SCRATCH_SIZE (TOTAL_DESCS_NUM * 4)
63 #define QMGR_LRAM0_BASE 0x80
64 #define QMGR_LRAM_SIZE 0x84
65 #define QMGR_LRAM1_BASE 0x88
66 #define QMGR_MEMBASE(x) (0x1000 + (x) * 0x10)
67 #define QMGR_MEMCTRL(x) (0x1004 + (x) * 0x10)
68 #define QMGR_MEMCTRL_IDX_SH 16
69 #define QMGR_MEMCTRL_DESC_SH 8
71 #define QMGR_NUM_PEND 5
72 #define QMGR_PEND(x) (0x90 + (x) * 4)
74 #define QMGR_PENDING_SLOT_Q(x) (x / 32)
75 #define QMGR_PENDING_BIT_Q(x) (x % 32)
77 #define QMGR_QUEUE_A(n) (0x2000 + (n) * 0x10)
78 #define QMGR_QUEUE_B(n) (0x2004 + (n) * 0x10)
79 #define QMGR_QUEUE_C(n) (0x2008 + (n) * 0x10)
80 #define QMGR_QUEUE_D(n) (0x200c + (n) * 0x10)
82 /* Glue layer specific */
83 /* USBSS / USB AM335x */
84 #define USBSS_IRQ_STATUS 0x28
85 #define USBSS_IRQ_ENABLER 0x2c
86 #define USBSS_IRQ_CLEARR 0x30
88 #define USBSS_IRQ_PD_COMP (1 << 2)
90 /* Packet Descriptor */
91 #define PD2_ZERO_LENGTH (1 << 19)
93 struct cppi41_channel {
95 struct dma_async_tx_descriptor txd;
96 struct cppi41_dd *cdd;
97 struct cppi41_desc *desc;
99 void __iomem *gcr_reg;
104 unsigned int q_comp_num;
105 unsigned int port_num;
108 unsigned td_queued:1;
110 unsigned td_desc_seen:1;
112 struct list_head node; /* Node for pending list */
132 struct dma_device ddev;
135 dma_addr_t scratch_phys;
137 struct cppi41_desc *cd;
138 dma_addr_t descs_phys;
140 struct cppi41_channel *chan_busy[ALLOC_DECS_NUM];
142 void __iomem *usbss_mem;
143 void __iomem *ctrl_mem;
144 void __iomem *sched_mem;
145 void __iomem *qmgr_mem;
147 const struct chan_queues *queues_rx;
148 const struct chan_queues *queues_tx;
149 struct chan_queues td_queue;
151 struct list_head pending; /* Pending queued transfers */
152 spinlock_t lock; /* Lock for pending list */
154 /* context for suspend/resume */
155 unsigned int dma_tdfdq;
160 #define FIST_COMPLETION_QUEUE 93
161 static struct chan_queues usb_queues_tx[] = {
163 [ 0] = { .submit = 32, .complete = 93},
164 [ 1] = { .submit = 34, .complete = 94},
165 [ 2] = { .submit = 36, .complete = 95},
166 [ 3] = { .submit = 38, .complete = 96},
167 [ 4] = { .submit = 40, .complete = 97},
168 [ 5] = { .submit = 42, .complete = 98},
169 [ 6] = { .submit = 44, .complete = 99},
170 [ 7] = { .submit = 46, .complete = 100},
171 [ 8] = { .submit = 48, .complete = 101},
172 [ 9] = { .submit = 50, .complete = 102},
173 [10] = { .submit = 52, .complete = 103},
174 [11] = { .submit = 54, .complete = 104},
175 [12] = { .submit = 56, .complete = 105},
176 [13] = { .submit = 58, .complete = 106},
177 [14] = { .submit = 60, .complete = 107},
180 [15] = { .submit = 62, .complete = 125},
181 [16] = { .submit = 64, .complete = 126},
182 [17] = { .submit = 66, .complete = 127},
183 [18] = { .submit = 68, .complete = 128},
184 [19] = { .submit = 70, .complete = 129},
185 [20] = { .submit = 72, .complete = 130},
186 [21] = { .submit = 74, .complete = 131},
187 [22] = { .submit = 76, .complete = 132},
188 [23] = { .submit = 78, .complete = 133},
189 [24] = { .submit = 80, .complete = 134},
190 [25] = { .submit = 82, .complete = 135},
191 [26] = { .submit = 84, .complete = 136},
192 [27] = { .submit = 86, .complete = 137},
193 [28] = { .submit = 88, .complete = 138},
194 [29] = { .submit = 90, .complete = 139},
197 static const struct chan_queues usb_queues_rx[] = {
199 [ 0] = { .submit = 1, .complete = 109},
200 [ 1] = { .submit = 2, .complete = 110},
201 [ 2] = { .submit = 3, .complete = 111},
202 [ 3] = { .submit = 4, .complete = 112},
203 [ 4] = { .submit = 5, .complete = 113},
204 [ 5] = { .submit = 6, .complete = 114},
205 [ 6] = { .submit = 7, .complete = 115},
206 [ 7] = { .submit = 8, .complete = 116},
207 [ 8] = { .submit = 9, .complete = 117},
208 [ 9] = { .submit = 10, .complete = 118},
209 [10] = { .submit = 11, .complete = 119},
210 [11] = { .submit = 12, .complete = 120},
211 [12] = { .submit = 13, .complete = 121},
212 [13] = { .submit = 14, .complete = 122},
213 [14] = { .submit = 15, .complete = 123},
216 [15] = { .submit = 16, .complete = 141},
217 [16] = { .submit = 17, .complete = 142},
218 [17] = { .submit = 18, .complete = 143},
219 [18] = { .submit = 19, .complete = 144},
220 [19] = { .submit = 20, .complete = 145},
221 [20] = { .submit = 21, .complete = 146},
222 [21] = { .submit = 22, .complete = 147},
223 [22] = { .submit = 23, .complete = 148},
224 [23] = { .submit = 24, .complete = 149},
225 [24] = { .submit = 25, .complete = 150},
226 [25] = { .submit = 26, .complete = 151},
227 [26] = { .submit = 27, .complete = 152},
228 [27] = { .submit = 28, .complete = 153},
229 [28] = { .submit = 29, .complete = 154},
230 [29] = { .submit = 30, .complete = 155},
233 struct cppi_glue_infos {
234 irqreturn_t (*isr)(int irq, void *data);
235 const struct chan_queues *queues_rx;
236 const struct chan_queues *queues_tx;
237 struct chan_queues td_queue;
240 static struct cppi41_channel *to_cpp41_chan(struct dma_chan *c)
242 return container_of(c, struct cppi41_channel, chan);
245 static struct cppi41_channel *desc_to_chan(struct cppi41_dd *cdd, u32 desc)
247 struct cppi41_channel *c;
251 descs_size = sizeof(struct cppi41_desc) * ALLOC_DECS_NUM;
253 if (!((desc >= cdd->descs_phys) &&
254 (desc < (cdd->descs_phys + descs_size)))) {
258 desc_num = (desc - cdd->descs_phys) / sizeof(struct cppi41_desc);
259 BUG_ON(desc_num >= ALLOC_DECS_NUM);
260 c = cdd->chan_busy[desc_num];
261 cdd->chan_busy[desc_num] = NULL;
263 /* Usecount for chan_busy[], paired with push_desc_queue() */
264 pm_runtime_put(cdd->ddev.dev);
269 static void cppi_writel(u32 val, void *__iomem *mem)
271 __raw_writel(val, mem);
274 static u32 cppi_readl(void *__iomem *mem)
276 return __raw_readl(mem);
279 static u32 pd_trans_len(u32 val)
281 return val & ((1 << (DESC_LENGTH_BITS_NUM + 1)) - 1);
284 static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num)
288 desc = cppi_readl(cdd->qmgr_mem + QMGR_QUEUE_D(queue_num));
293 static irqreturn_t cppi41_irq(int irq, void *data)
295 struct cppi41_dd *cdd = data;
296 struct cppi41_channel *c;
300 status = cppi_readl(cdd->usbss_mem + USBSS_IRQ_STATUS);
301 if (!(status & USBSS_IRQ_PD_COMP))
303 cppi_writel(status, cdd->usbss_mem + USBSS_IRQ_STATUS);
305 for (i = QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE); i < QMGR_NUM_PEND;
310 val = cppi_readl(cdd->qmgr_mem + QMGR_PEND(i));
311 if (i == QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE) && val) {
313 /* set corresponding bit for completetion Q 93 */
314 mask = 1 << QMGR_PENDING_BIT_Q(FIST_COMPLETION_QUEUE);
315 /* not set all bits for queues less than Q 93 */
317 /* now invert and keep only Q 93+ set */
328 error = pm_runtime_get(cdd->ddev.dev);
330 dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n",
334 val &= ~(1 << q_num);
336 desc = cppi41_pop_desc(cdd, q_num);
337 c = desc_to_chan(cdd, desc);
339 pr_err("%s() q %d desc %08x\n", __func__,
344 if (c->desc->pd2 & PD2_ZERO_LENGTH)
347 len = pd_trans_len(c->desc->pd0);
349 c->residue = pd_trans_len(c->desc->pd6) - len;
350 dma_cookie_complete(&c->txd);
351 dmaengine_desc_get_callback_invoke(&c->txd, NULL);
353 pm_runtime_mark_last_busy(cdd->ddev.dev);
354 pm_runtime_put_autosuspend(cdd->ddev.dev);
360 static dma_cookie_t cppi41_tx_submit(struct dma_async_tx_descriptor *tx)
364 cookie = dma_cookie_assign(tx);
369 static int cppi41_dma_alloc_chan_resources(struct dma_chan *chan)
371 struct cppi41_channel *c = to_cpp41_chan(chan);
372 struct cppi41_dd *cdd = c->cdd;
375 error = pm_runtime_get_sync(cdd->ddev.dev);
377 dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n",
379 pm_runtime_put_noidle(cdd->ddev.dev);
384 dma_cookie_init(chan);
385 dma_async_tx_descriptor_init(&c->txd, chan);
386 c->txd.tx_submit = cppi41_tx_submit;
389 cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0);
391 pm_runtime_mark_last_busy(cdd->ddev.dev);
392 pm_runtime_put_autosuspend(cdd->ddev.dev);
397 static void cppi41_dma_free_chan_resources(struct dma_chan *chan)
399 struct cppi41_channel *c = to_cpp41_chan(chan);
400 struct cppi41_dd *cdd = c->cdd;
403 error = pm_runtime_get_sync(cdd->ddev.dev);
405 pm_runtime_put_noidle(cdd->ddev.dev);
410 WARN_ON(!list_empty(&cdd->pending));
412 pm_runtime_mark_last_busy(cdd->ddev.dev);
413 pm_runtime_put_autosuspend(cdd->ddev.dev);
416 static enum dma_status cppi41_dma_tx_status(struct dma_chan *chan,
417 dma_cookie_t cookie, struct dma_tx_state *txstate)
419 struct cppi41_channel *c = to_cpp41_chan(chan);
423 ret = dma_cookie_status(chan, cookie, txstate);
424 if (txstate && ret == DMA_COMPLETE)
425 txstate->residue = c->residue;
431 static void push_desc_queue(struct cppi41_channel *c)
433 struct cppi41_dd *cdd = c->cdd;
440 reg = GCR_CHAN_ENABLE;
442 reg |= GCR_STARV_RETRY;
443 reg |= GCR_DESC_TYPE_HOST;
444 reg |= c->q_comp_num;
447 cppi_writel(reg, c->gcr_reg);
450 * We don't use writel() but __raw_writel() so we have to make sure
451 * that the DMA descriptor in coherent memory made to the main memory
452 * before starting the dma engine.
457 * DMA transfers can take at least 200ms to complete with USB mass
458 * storage connected. To prevent autosuspend timeouts, we must use
459 * pm_runtime_get/put() when chan_busy[] is modified. This will get
460 * cleared in desc_to_chan() or cppi41_stop_chan() depending on the
461 * outcome of the transfer.
463 pm_runtime_get(cdd->ddev.dev);
465 desc_phys = lower_32_bits(c->desc_phys);
466 desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
467 WARN_ON(cdd->chan_busy[desc_num]);
468 cdd->chan_busy[desc_num] = c;
470 reg = (sizeof(struct cppi41_desc) - 24) / 4;
472 cppi_writel(reg, cdd->qmgr_mem + QMGR_QUEUE_D(c->q_num));
476 * Caller must hold cdd->lock to prevent push_desc_queue()
477 * getting called out of order. We have both cppi41_dma_issue_pending()
478 * and cppi41_runtime_resume() call this function.
480 static void cppi41_run_queue(struct cppi41_dd *cdd)
482 struct cppi41_channel *c, *_c;
484 list_for_each_entry_safe(c, _c, &cdd->pending, node) {
490 static void cppi41_dma_issue_pending(struct dma_chan *chan)
492 struct cppi41_channel *c = to_cpp41_chan(chan);
493 struct cppi41_dd *cdd = c->cdd;
497 error = pm_runtime_get(cdd->ddev.dev);
498 if ((error != -EINPROGRESS) && error < 0) {
499 pm_runtime_put_noidle(cdd->ddev.dev);
500 dev_err(cdd->ddev.dev, "Failed to pm_runtime_get: %i\n",
506 spin_lock_irqsave(&cdd->lock, flags);
507 list_add_tail(&c->node, &cdd->pending);
508 if (!cdd->is_suspended)
509 cppi41_run_queue(cdd);
510 spin_unlock_irqrestore(&cdd->lock, flags);
512 pm_runtime_mark_last_busy(cdd->ddev.dev);
513 pm_runtime_put_autosuspend(cdd->ddev.dev);
516 static u32 get_host_pd0(u32 length)
520 reg = DESC_TYPE_HOST << DESC_TYPE;
526 static u32 get_host_pd1(struct cppi41_channel *c)
535 static u32 get_host_pd2(struct cppi41_channel *c)
540 reg |= c->q_comp_num;
545 static u32 get_host_pd3(u32 length)
549 /* PD3 = packet size */
555 static u32 get_host_pd6(u32 length)
559 /* PD6 buffer size */
560 reg = DESC_PD_COMPLETE;
566 static u32 get_host_pd4_or_7(u32 addr)
575 static u32 get_host_pd5(void)
584 static struct dma_async_tx_descriptor *cppi41_dma_prep_slave_sg(
585 struct dma_chan *chan, struct scatterlist *sgl, unsigned sg_len,
586 enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
588 struct cppi41_channel *c = to_cpp41_chan(chan);
589 struct dma_async_tx_descriptor *txd = NULL;
590 struct cppi41_dd *cdd = c->cdd;
591 struct cppi41_desc *d;
592 struct scatterlist *sg;
596 error = pm_runtime_get(cdd->ddev.dev);
598 pm_runtime_put_noidle(cdd->ddev.dev);
603 if (cdd->is_suspended)
604 goto err_out_not_ready;
607 for_each_sg(sgl, sg, sg_len, i) {
611 /* We need to use more than one desc once musb supports sg */
612 addr = lower_32_bits(sg_dma_address(sg));
613 len = sg_dma_len(sg);
615 d->pd0 = get_host_pd0(len);
616 d->pd1 = get_host_pd1(c);
617 d->pd2 = get_host_pd2(c);
618 d->pd3 = get_host_pd3(len);
619 d->pd4 = get_host_pd4_or_7(addr);
620 d->pd5 = get_host_pd5();
621 d->pd6 = get_host_pd6(len);
622 d->pd7 = get_host_pd4_or_7(addr);
630 pm_runtime_mark_last_busy(cdd->ddev.dev);
631 pm_runtime_put_autosuspend(cdd->ddev.dev);
636 static void cppi41_compute_td_desc(struct cppi41_desc *d)
638 d->pd0 = DESC_TYPE_TEARD << DESC_TYPE;
641 static int cppi41_tear_down_chan(struct cppi41_channel *c)
643 struct cppi41_dd *cdd = c->cdd;
644 struct cppi41_desc *td;
650 td += cdd->first_td_desc;
652 td_desc_phys = cdd->descs_phys;
653 td_desc_phys += cdd->first_td_desc * sizeof(struct cppi41_desc);
656 cppi41_compute_td_desc(td);
659 reg = (sizeof(struct cppi41_desc) - 24) / 4;
661 cppi_writel(reg, cdd->qmgr_mem +
662 QMGR_QUEUE_D(cdd->td_queue.submit));
664 reg = GCR_CHAN_ENABLE;
666 reg |= GCR_STARV_RETRY;
667 reg |= GCR_DESC_TYPE_HOST;
668 reg |= c->q_comp_num;
671 cppi_writel(reg, c->gcr_reg);
676 if (!c->td_seen || !c->td_desc_seen) {
678 desc_phys = cppi41_pop_desc(cdd, cdd->td_queue.complete);
680 desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
682 if (desc_phys == c->desc_phys) {
685 } else if (desc_phys == td_desc_phys) {
690 WARN_ON((pd0 >> DESC_TYPE) != DESC_TYPE_TEARD);
691 WARN_ON(!c->is_tx && !(pd0 & TD_DESC_IS_RX));
692 WARN_ON((pd0 & 0x1f) != c->port_num);
694 } else if (desc_phys) {
700 * If the TX descriptor / channel is in use, the caller needs to poke
701 * his TD bit multiple times. After that he hardware releases the
702 * transfer descriptor followed by TD descriptor. Waiting seems not to
703 * cause any difference.
704 * RX seems to be thrown out right away. However once the TearDown
705 * descriptor gets through we are done. If we have seens the transfer
706 * descriptor before the TD we fetch it from enqueue, it has to be
707 * there waiting for us.
709 if (!c->td_seen && c->td_retry) {
713 WARN_ON(!c->td_retry);
715 if (!c->td_desc_seen) {
716 desc_phys = cppi41_pop_desc(cdd, c->q_num);
718 desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
725 cppi_writel(0, c->gcr_reg);
729 static int cppi41_stop_chan(struct dma_chan *chan)
731 struct cppi41_channel *c = to_cpp41_chan(chan);
732 struct cppi41_dd *cdd = c->cdd;
737 desc_phys = lower_32_bits(c->desc_phys);
738 desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
739 if (!cdd->chan_busy[desc_num]) {
740 struct cppi41_channel *cc, *_ct;
743 * channels might still be in the pendling list if
744 * cppi41_dma_issue_pending() is called after
745 * cppi41_runtime_suspend() is called
747 list_for_each_entry_safe(cc, _ct, &cdd->pending, node) {
756 ret = cppi41_tear_down_chan(c);
760 WARN_ON(!cdd->chan_busy[desc_num]);
761 cdd->chan_busy[desc_num] = NULL;
763 /* Usecount for chan_busy[], paired with push_desc_queue() */
764 pm_runtime_put(cdd->ddev.dev);
769 static void cleanup_chans(struct cppi41_dd *cdd)
771 while (!list_empty(&cdd->ddev.channels)) {
772 struct cppi41_channel *cchan;
774 cchan = list_first_entry(&cdd->ddev.channels,
775 struct cppi41_channel, chan.device_node);
776 list_del(&cchan->chan.device_node);
781 static int cppi41_add_chans(struct device *dev, struct cppi41_dd *cdd)
783 struct cppi41_channel *cchan;
788 ret = of_property_read_u32(dev->of_node, "#dma-channels",
793 * The channels can only be used as TX or as RX. So we add twice
794 * that much dma channels because USB can only do RX or TX.
798 for (i = 0; i < n_chans; i++) {
799 cchan = kzalloc(sizeof(*cchan), GFP_KERNEL);
805 cchan->gcr_reg = cdd->ctrl_mem + DMA_TXGCR(i >> 1);
808 cchan->gcr_reg = cdd->ctrl_mem + DMA_RXGCR(i >> 1);
811 cchan->port_num = i >> 1;
812 cchan->desc = &cdd->cd[i];
813 cchan->desc_phys = cdd->descs_phys;
814 cchan->desc_phys += i * sizeof(struct cppi41_desc);
815 cchan->chan.device = &cdd->ddev;
816 list_add_tail(&cchan->chan.device_node, &cdd->ddev.channels);
818 cdd->first_td_desc = n_chans;
826 static void purge_descs(struct device *dev, struct cppi41_dd *cdd)
828 unsigned int mem_decs;
831 mem_decs = ALLOC_DECS_NUM * sizeof(struct cppi41_desc);
833 for (i = 0; i < DESCS_AREAS; i++) {
835 cppi_writel(0, cdd->qmgr_mem + QMGR_MEMBASE(i));
836 cppi_writel(0, cdd->qmgr_mem + QMGR_MEMCTRL(i));
838 dma_free_coherent(dev, mem_decs, cdd->cd,
843 static void disable_sched(struct cppi41_dd *cdd)
845 cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
848 static void deinit_cppi41(struct device *dev, struct cppi41_dd *cdd)
852 purge_descs(dev, cdd);
854 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
855 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
856 dma_free_coherent(dev, QMGR_SCRATCH_SIZE, cdd->qmgr_scratch,
860 static int init_descs(struct device *dev, struct cppi41_dd *cdd)
862 unsigned int desc_size;
863 unsigned int mem_decs;
868 BUILD_BUG_ON(sizeof(struct cppi41_desc) &
869 (sizeof(struct cppi41_desc) - 1));
870 BUILD_BUG_ON(sizeof(struct cppi41_desc) < 32);
871 BUILD_BUG_ON(ALLOC_DECS_NUM < 32);
873 desc_size = sizeof(struct cppi41_desc);
874 mem_decs = ALLOC_DECS_NUM * desc_size;
877 for (i = 0; i < DESCS_AREAS; i++) {
879 reg = idx << QMGR_MEMCTRL_IDX_SH;
880 reg |= (ilog2(desc_size) - 5) << QMGR_MEMCTRL_DESC_SH;
881 reg |= ilog2(ALLOC_DECS_NUM) - 5;
883 BUILD_BUG_ON(DESCS_AREAS != 1);
884 cdd->cd = dma_alloc_coherent(dev, mem_decs,
885 &cdd->descs_phys, GFP_KERNEL);
889 cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
890 cppi_writel(reg, cdd->qmgr_mem + QMGR_MEMCTRL(i));
892 idx += ALLOC_DECS_NUM;
897 static void init_sched(struct cppi41_dd *cdd)
904 cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
905 for (ch = 0; ch < 15 * 2; ch += 2) {
907 reg = SCHED_ENTRY0_CHAN(ch);
908 reg |= SCHED_ENTRY1_CHAN(ch) | SCHED_ENTRY1_IS_RX;
910 reg |= SCHED_ENTRY2_CHAN(ch + 1);
911 reg |= SCHED_ENTRY3_CHAN(ch + 1) | SCHED_ENTRY3_IS_RX;
912 cppi_writel(reg, cdd->sched_mem + DMA_SCHED_WORD(word));
915 reg = 15 * 2 * 2 - 1;
916 reg |= DMA_SCHED_CTRL_EN;
917 cppi_writel(reg, cdd->sched_mem + DMA_SCHED_CTRL);
920 static int init_cppi41(struct device *dev, struct cppi41_dd *cdd)
924 BUILD_BUG_ON(QMGR_SCRATCH_SIZE > ((1 << 14) - 1));
925 cdd->qmgr_scratch = dma_alloc_coherent(dev, QMGR_SCRATCH_SIZE,
926 &cdd->scratch_phys, GFP_KERNEL);
927 if (!cdd->qmgr_scratch)
930 cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
931 cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
932 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
934 ret = init_descs(dev, cdd);
938 cppi_writel(cdd->td_queue.submit, cdd->ctrl_mem + DMA_TDFDQ);
942 deinit_cppi41(dev, cdd);
946 static struct platform_driver cpp41_dma_driver;
948 * The param format is:
956 static bool cpp41_dma_filter_fn(struct dma_chan *chan, void *param)
958 struct cppi41_channel *cchan;
959 struct cppi41_dd *cdd;
960 const struct chan_queues *queues;
963 if (chan->device->dev->driver != &cpp41_dma_driver.driver)
966 cchan = to_cpp41_chan(chan);
968 if (cchan->port_num != num[INFO_PORT])
971 if (cchan->is_tx && !num[INFO_IS_TX])
975 queues = cdd->queues_tx;
977 queues = cdd->queues_rx;
979 BUILD_BUG_ON(ARRAY_SIZE(usb_queues_rx) != ARRAY_SIZE(usb_queues_tx));
980 if (WARN_ON(cchan->port_num > ARRAY_SIZE(usb_queues_rx)))
983 cchan->q_num = queues[cchan->port_num].submit;
984 cchan->q_comp_num = queues[cchan->port_num].complete;
988 static struct of_dma_filter_info cpp41_dma_info = {
989 .filter_fn = cpp41_dma_filter_fn,
992 static struct dma_chan *cppi41_dma_xlate(struct of_phandle_args *dma_spec,
993 struct of_dma *ofdma)
995 int count = dma_spec->args_count;
996 struct of_dma_filter_info *info = ofdma->of_dma_data;
998 if (!info || !info->filter_fn)
1004 return dma_request_channel(info->dma_cap, info->filter_fn,
1005 &dma_spec->args[0]);
1008 static const struct cppi_glue_infos usb_infos = {
1010 .queues_rx = usb_queues_rx,
1011 .queues_tx = usb_queues_tx,
1012 .td_queue = { .submit = 31, .complete = 0 },
1015 static const struct of_device_id cppi41_dma_ids[] = {
1016 { .compatible = "ti,am3359-cppi41", .data = &usb_infos},
1019 MODULE_DEVICE_TABLE(of, cppi41_dma_ids);
1021 static const struct cppi_glue_infos *get_glue_info(struct device *dev)
1023 const struct of_device_id *of_id;
1025 of_id = of_match_node(cppi41_dma_ids, dev->of_node);
1031 #define CPPI41_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1032 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
1033 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
1034 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1036 static int cppi41_dma_probe(struct platform_device *pdev)
1038 struct cppi41_dd *cdd;
1039 struct device *dev = &pdev->dev;
1040 const struct cppi_glue_infos *glue_info;
1044 glue_info = get_glue_info(dev);
1048 cdd = devm_kzalloc(&pdev->dev, sizeof(*cdd), GFP_KERNEL);
1052 dma_cap_set(DMA_SLAVE, cdd->ddev.cap_mask);
1053 cdd->ddev.device_alloc_chan_resources = cppi41_dma_alloc_chan_resources;
1054 cdd->ddev.device_free_chan_resources = cppi41_dma_free_chan_resources;
1055 cdd->ddev.device_tx_status = cppi41_dma_tx_status;
1056 cdd->ddev.device_issue_pending = cppi41_dma_issue_pending;
1057 cdd->ddev.device_prep_slave_sg = cppi41_dma_prep_slave_sg;
1058 cdd->ddev.device_terminate_all = cppi41_stop_chan;
1059 cdd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1060 cdd->ddev.src_addr_widths = CPPI41_DMA_BUSWIDTHS;
1061 cdd->ddev.dst_addr_widths = CPPI41_DMA_BUSWIDTHS;
1062 cdd->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1063 cdd->ddev.dev = dev;
1064 INIT_LIST_HEAD(&cdd->ddev.channels);
1065 cpp41_dma_info.dma_cap = cdd->ddev.cap_mask;
1067 cdd->usbss_mem = of_iomap(dev->of_node, 0);
1068 cdd->ctrl_mem = of_iomap(dev->of_node, 1);
1069 cdd->sched_mem = of_iomap(dev->of_node, 2);
1070 cdd->qmgr_mem = of_iomap(dev->of_node, 3);
1071 spin_lock_init(&cdd->lock);
1072 INIT_LIST_HEAD(&cdd->pending);
1074 platform_set_drvdata(pdev, cdd);
1076 if (!cdd->usbss_mem || !cdd->ctrl_mem || !cdd->sched_mem ||
1080 pm_runtime_enable(dev);
1081 pm_runtime_set_autosuspend_delay(dev, 100);
1082 pm_runtime_use_autosuspend(dev);
1083 ret = pm_runtime_get_sync(dev);
1087 cdd->queues_rx = glue_info->queues_rx;
1088 cdd->queues_tx = glue_info->queues_tx;
1089 cdd->td_queue = glue_info->td_queue;
1091 ret = init_cppi41(dev, cdd);
1095 ret = cppi41_add_chans(dev, cdd);
1099 irq = irq_of_parse_and_map(dev->of_node, 0);
1105 cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
1107 ret = devm_request_irq(&pdev->dev, irq, glue_info->isr, IRQF_SHARED,
1108 dev_name(dev), cdd);
1113 ret = dma_async_device_register(&cdd->ddev);
1117 ret = of_dma_controller_register(dev->of_node,
1118 cppi41_dma_xlate, &cpp41_dma_info);
1122 pm_runtime_mark_last_busy(dev);
1123 pm_runtime_put_autosuspend(dev);
1127 dma_async_device_unregister(&cdd->ddev);
1130 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
1133 deinit_cppi41(dev, cdd);
1135 pm_runtime_dont_use_autosuspend(dev);
1137 pm_runtime_put_sync(dev);
1138 pm_runtime_disable(dev);
1139 iounmap(cdd->usbss_mem);
1140 iounmap(cdd->ctrl_mem);
1141 iounmap(cdd->sched_mem);
1142 iounmap(cdd->qmgr_mem);
1146 static int cppi41_dma_remove(struct platform_device *pdev)
1148 struct cppi41_dd *cdd = platform_get_drvdata(pdev);
1151 error = pm_runtime_get_sync(&pdev->dev);
1153 dev_err(&pdev->dev, "%s could not pm_runtime_get: %i\n",
1155 of_dma_controller_free(pdev->dev.of_node);
1156 dma_async_device_unregister(&cdd->ddev);
1158 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
1159 devm_free_irq(&pdev->dev, cdd->irq, cdd);
1161 deinit_cppi41(&pdev->dev, cdd);
1162 iounmap(cdd->usbss_mem);
1163 iounmap(cdd->ctrl_mem);
1164 iounmap(cdd->sched_mem);
1165 iounmap(cdd->qmgr_mem);
1166 pm_runtime_dont_use_autosuspend(&pdev->dev);
1167 pm_runtime_put_sync(&pdev->dev);
1168 pm_runtime_disable(&pdev->dev);
1172 static int __maybe_unused cppi41_suspend(struct device *dev)
1174 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1176 cdd->dma_tdfdq = cppi_readl(cdd->ctrl_mem + DMA_TDFDQ);
1177 cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
1183 static int __maybe_unused cppi41_resume(struct device *dev)
1185 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1186 struct cppi41_channel *c;
1189 for (i = 0; i < DESCS_AREAS; i++)
1190 cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
1192 list_for_each_entry(c, &cdd->ddev.channels, chan.device_node)
1194 cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0);
1198 cppi_writel(cdd->dma_tdfdq, cdd->ctrl_mem + DMA_TDFDQ);
1199 cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
1200 cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
1201 cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
1203 cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
1208 static int __maybe_unused cppi41_runtime_suspend(struct device *dev)
1210 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1211 unsigned long flags;
1213 spin_lock_irqsave(&cdd->lock, flags);
1214 cdd->is_suspended = true;
1215 WARN_ON(!list_empty(&cdd->pending));
1216 spin_unlock_irqrestore(&cdd->lock, flags);
1221 static int __maybe_unused cppi41_runtime_resume(struct device *dev)
1223 struct cppi41_dd *cdd = dev_get_drvdata(dev);
1224 unsigned long flags;
1226 spin_lock_irqsave(&cdd->lock, flags);
1227 cdd->is_suspended = false;
1228 cppi41_run_queue(cdd);
1229 spin_unlock_irqrestore(&cdd->lock, flags);
1234 static const struct dev_pm_ops cppi41_pm_ops = {
1235 SET_LATE_SYSTEM_SLEEP_PM_OPS(cppi41_suspend, cppi41_resume)
1236 SET_RUNTIME_PM_OPS(cppi41_runtime_suspend,
1237 cppi41_runtime_resume,
1241 static struct platform_driver cpp41_dma_driver = {
1242 .probe = cppi41_dma_probe,
1243 .remove = cppi41_dma_remove,
1245 .name = "cppi41-dma-engine",
1246 .pm = &cppi41_pm_ops,
1247 .of_match_table = of_match_ptr(cppi41_dma_ids),
1251 module_platform_driver(cpp41_dma_driver);
1252 MODULE_LICENSE("GPL");
1253 MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");