1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
5 * Copyright (C) 2014 Atmel Corporation
7 * Author: Ludovic Desroches <ludovic.desroches@atmel.com>
10 #include <asm/barrier.h>
11 #include <dt-bindings/dma/at91.h>
12 #include <linux/clk.h>
13 #include <linux/dmaengine.h>
14 #include <linux/dmapool.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/kernel.h>
18 #include <linux/list.h>
19 #include <linux/module.h>
20 #include <linux/of_dma.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
25 #include "dmaengine.h"
27 /* Global registers */
28 #define AT_XDMAC_GTYPE 0x00 /* Global Type Register */
29 #define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */
30 #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */
31 #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */
32 #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */
33 #define AT_XDMAC_WRHP(i) (((i) & 0xF) << 4)
34 #define AT_XDMAC_WRMP(i) (((i) & 0xF) << 8)
35 #define AT_XDMAC_WRLP(i) (((i) & 0xF) << 12)
36 #define AT_XDMAC_RDHP(i) (((i) & 0xF) << 16)
37 #define AT_XDMAC_RDMP(i) (((i) & 0xF) << 20)
38 #define AT_XDMAC_RDLP(i) (((i) & 0xF) << 24)
39 #define AT_XDMAC_RDSG(i) (((i) & 0xF) << 28)
40 #define AT_XDMAC_GCFG_M2M (AT_XDMAC_RDLP(0xF) | AT_XDMAC_WRLP(0xF))
41 #define AT_XDMAC_GCFG_P2M (AT_XDMAC_RDSG(0x1) | AT_XDMAC_RDHP(0x3) | \
43 #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */
44 #define AT_XDMAC_PW0(i) (((i) & 0xF) << 0)
45 #define AT_XDMAC_PW1(i) (((i) & 0xF) << 4)
46 #define AT_XDMAC_PW2(i) (((i) & 0xF) << 8)
47 #define AT_XDMAC_PW3(i) (((i) & 0xF) << 12)
48 #define AT_XDMAC_GWAC_M2M 0
49 #define AT_XDMAC_GWAC_P2M (AT_XDMAC_PW0(0xF) | AT_XDMAC_PW2(0xF))
51 #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */
52 #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */
53 #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
54 #define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */
55 #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
56 #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
57 #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
58 #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */
60 /* Channel relative registers offsets */
61 #define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */
62 #define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */
63 #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */
64 #define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */
65 #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */
66 #define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */
67 #define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */
68 #define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */
69 #define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */
70 #define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */
71 #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */
72 #define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */
73 #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */
74 #define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */
75 #define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */
76 #define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */
77 #define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */
78 #define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */
79 #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */
80 #define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */
81 #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */
82 #define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */
83 #define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */
84 #define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */
85 #define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */
86 #define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */
87 #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */
88 #define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */
89 #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */
90 #define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */
91 #define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */
92 #define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */
93 #define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */
94 #define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */
95 #define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */
96 #define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */
97 #define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */
98 #define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */
99 #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */
100 #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */
101 #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */
102 #define AT_XDMAC_CNDC_NDVIEW_MASK GENMASK(28, 27)
103 #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
104 #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
105 #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
106 #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */
107 #define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */
108 #define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */
109 #define AT_XDMAC_CC 0x28 /* Channel Configuration Register */
110 #define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */
111 #define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */
112 #define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */
113 #define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1)
114 #define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1)
115 #define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1)
116 #define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1)
117 #define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1)
118 #define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */
119 #define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4)
120 #define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4)
121 #define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */
122 #define AT_XDMAC_CC_PROT_SEC (0x0 << 5)
123 #define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5)
124 #define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */
125 #define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6)
126 #define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6)
127 #define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */
128 #define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7)
129 #define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7)
130 #define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */
131 #define AT_XDMAC_CC_DWIDTH_OFFSET 11
132 #define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET)
133 #define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */
134 #define AT_XDMAC_CC_DWIDTH_BYTE 0x0
135 #define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1
136 #define AT_XDMAC_CC_DWIDTH_WORD 0x2
137 #define AT_XDMAC_CC_DWIDTH_DWORD 0x3
138 #define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */
139 #define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */
140 #define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */
141 #define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16)
142 #define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16)
143 #define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16)
144 #define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16)
145 #define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */
146 #define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18)
147 #define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18)
148 #define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18)
149 #define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18)
150 #define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */
151 #define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21)
152 #define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21)
153 #define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */
154 #define AT_XDMAC_CC_RDIP_DONE (0x0 << 22)
155 #define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22)
156 #define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */
157 #define AT_XDMAC_CC_WRIP_DONE (0x0 << 23)
158 #define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23)
159 #define AT_XDMAC_CC_PERID(i) ((0x7f & (i)) << 24) /* Channel Peripheral Identifier */
160 #define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */
161 #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
162 #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
164 /* Microblock control members */
165 #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */
166 #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */
167 #define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */
168 #define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */
169 #define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */
170 #define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */
171 #define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */
172 #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */
174 #define AT_XDMAC_MAX_CHAN 0x20
175 #define AT_XDMAC_MAX_CSIZE 16 /* 16 data */
176 #define AT_XDMAC_MAX_DWIDTH 8 /* 64 bits */
177 #define AT_XDMAC_RESIDUE_MAX_RETRIES 5
179 #define AT_XDMAC_DMA_BUSWIDTHS\
180 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
181 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
182 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
183 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\
184 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
187 AT_XDMAC_CHAN_IS_CYCLIC = 0,
188 AT_XDMAC_CHAN_IS_PAUSED,
191 struct at_xdmac_layout {
192 /* Global Channel Read Suspend Register */
194 /* Global Write Suspend Register */
196 /* Global Channel Read Write Suspend Register */
198 /* Global Channel Read Write Resume Register */
200 /* Global Channel Software Request Register */
202 /* Global channel Software Request Status Register */
204 /* Global Channel Software Flush Request Register */
206 /* Channel reg base */
208 /* Source/Destination Interface must be specified or not */
210 /* AXI queue priority configuration supported */
214 /* ----- Channels ----- */
215 struct at_xdmac_chan {
216 struct dma_chan chan;
217 void __iomem *ch_regs;
218 u32 mask; /* Channel Mask */
219 u32 cfg; /* Channel Configuration Register */
220 u8 perid; /* Peripheral ID */
221 u8 perif; /* Peripheral Interface */
222 u8 memif; /* Memory Interface */
228 unsigned long status;
229 struct tasklet_struct tasklet;
230 struct dma_slave_config sconfig;
234 struct list_head xfers_list;
235 struct list_head free_descs_list;
239 /* ----- Controller ----- */
241 struct dma_device dma;
246 struct dma_pool *at_xdmac_desc_pool;
247 const struct at_xdmac_layout *layout;
248 struct at_xdmac_chan chan[];
252 /* ----- Descriptors ----- */
254 /* Linked List Descriptor */
255 struct at_xdmac_lld {
256 u32 mbr_nda; /* Next Descriptor Member */
257 u32 mbr_ubc; /* Microblock Control Member */
258 u32 mbr_sa; /* Source Address Member */
259 u32 mbr_da; /* Destination Address Member */
260 u32 mbr_cfg; /* Configuration Register */
261 u32 mbr_bc; /* Block Control Register */
262 u32 mbr_ds; /* Data Stride Register */
263 u32 mbr_sus; /* Source Microblock Stride Register */
264 u32 mbr_dus; /* Destination Microblock Stride Register */
267 /* 64-bit alignment needed to update CNDA and CUBC registers in an atomic way. */
268 struct at_xdmac_desc {
269 struct at_xdmac_lld lld;
270 enum dma_transfer_direction direction;
271 struct dma_async_tx_descriptor tx_dma_desc;
272 struct list_head desc_node;
273 /* Following members are only used by the first descriptor */
275 unsigned int xfer_size;
276 struct list_head descs_list;
277 struct list_head xfer_node;
278 } __aligned(sizeof(u64));
280 static const struct at_xdmac_layout at_xdmac_sama5d4_layout = {
288 .chan_cc_reg_base = 0x50,
293 static const struct at_xdmac_layout at_xdmac_sama7g5_layout = {
301 .chan_cc_reg_base = 0x60,
306 static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
308 return atxdmac->regs + (atxdmac->layout->chan_cc_reg_base + chan_nb * 0x40);
311 #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
312 #define at_xdmac_write(atxdmac, reg, value) \
313 writel_relaxed((value), (atxdmac)->regs + (reg))
315 #define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg))
316 #define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg))
318 static inline struct at_xdmac_chan *to_at_xdmac_chan(struct dma_chan *dchan)
320 return container_of(dchan, struct at_xdmac_chan, chan);
323 static struct device *chan2dev(struct dma_chan *chan)
325 return &chan->dev->device;
328 static inline struct at_xdmac *to_at_xdmac(struct dma_device *ddev)
330 return container_of(ddev, struct at_xdmac, dma);
333 static inline struct at_xdmac_desc *txd_to_at_desc(struct dma_async_tx_descriptor *txd)
335 return container_of(txd, struct at_xdmac_desc, tx_dma_desc);
338 static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan *atchan)
340 return test_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
343 static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan *atchan)
345 return test_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
348 static inline bool at_xdmac_chan_is_peripheral_xfer(u32 cfg)
350 return cfg & AT_XDMAC_CC_TYPE_PER_TRAN;
353 static inline u8 at_xdmac_get_dwidth(u32 cfg)
355 return (cfg & AT_XDMAC_CC_DWIDTH_MASK) >> AT_XDMAC_CC_DWIDTH_OFFSET;
358 static unsigned int init_nr_desc_per_channel = 64;
359 module_param(init_nr_desc_per_channel, uint, 0644);
360 MODULE_PARM_DESC(init_nr_desc_per_channel,
361 "initial descriptors per channel (default: 64)");
364 static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan *atchan)
366 return at_xdmac_chan_read(atchan, AT_XDMAC_GS) & atchan->mask;
369 static void at_xdmac_off(struct at_xdmac *atxdmac)
371 at_xdmac_write(atxdmac, AT_XDMAC_GD, -1L);
373 /* Wait that all chans are disabled. */
374 while (at_xdmac_read(atxdmac, AT_XDMAC_GS))
377 at_xdmac_write(atxdmac, AT_XDMAC_GID, -1L);
380 /* Call with lock hold. */
381 static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
382 struct at_xdmac_desc *first)
384 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
387 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, first);
389 /* Set transfer as active to not try to start it again. */
390 first->active_xfer = true;
392 /* Tell xdmac where to get the first descriptor. */
393 reg = AT_XDMAC_CNDA_NDA(first->tx_dma_desc.phys);
394 if (atxdmac->layout->sdif)
395 reg |= AT_XDMAC_CNDA_NDAIF(atchan->memif);
397 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, reg);
400 * When doing non cyclic transfer we need to use the next
401 * descriptor view 2 since some fields of the configuration register
402 * depend on transfer size and src/dest addresses.
404 if (at_xdmac_chan_is_cyclic(atchan))
405 reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
406 else if ((first->lld.mbr_ubc &
407 AT_XDMAC_CNDC_NDVIEW_MASK) == AT_XDMAC_MBR_UBC_NDV3)
408 reg = AT_XDMAC_CNDC_NDVIEW_NDV3;
410 reg = AT_XDMAC_CNDC_NDVIEW_NDV2;
412 * Even if the register will be updated from the configuration in the
413 * descriptor when using view 2 or higher, the PROT bit won't be set
414 * properly. This bit can be modified only by using the channel
415 * configuration register.
417 at_xdmac_chan_write(atchan, AT_XDMAC_CC, first->lld.mbr_cfg);
419 reg |= AT_XDMAC_CNDC_NDDUP
420 | AT_XDMAC_CNDC_NDSUP
422 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, reg);
424 dev_vdbg(chan2dev(&atchan->chan),
425 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
426 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
427 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
428 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
429 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
430 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
431 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
433 at_xdmac_chan_write(atchan, AT_XDMAC_CID, 0xffffffff);
434 reg = AT_XDMAC_CIE_RBEIE | AT_XDMAC_CIE_WBEIE;
436 * Request Overflow Error is only for peripheral synchronized transfers
438 if (at_xdmac_chan_is_peripheral_xfer(first->lld.mbr_cfg))
439 reg |= AT_XDMAC_CIE_ROIE;
442 * There is no end of list when doing cyclic dma, we need to get
443 * an interrupt after each periods.
445 if (at_xdmac_chan_is_cyclic(atchan))
446 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
447 reg | AT_XDMAC_CIE_BIE);
449 at_xdmac_chan_write(atchan, AT_XDMAC_CIE,
450 reg | AT_XDMAC_CIE_LIE);
451 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atchan->mask);
452 dev_vdbg(chan2dev(&atchan->chan),
453 "%s: enable channel (0x%08x)\n", __func__, atchan->mask);
455 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
457 dev_vdbg(chan2dev(&atchan->chan),
458 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
459 __func__, at_xdmac_chan_read(atchan, AT_XDMAC_CC),
460 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
461 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
462 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
463 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
464 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
468 static dma_cookie_t at_xdmac_tx_submit(struct dma_async_tx_descriptor *tx)
470 struct at_xdmac_desc *desc = txd_to_at_desc(tx);
471 struct at_xdmac_chan *atchan = to_at_xdmac_chan(tx->chan);
473 unsigned long irqflags;
475 spin_lock_irqsave(&atchan->lock, irqflags);
476 cookie = dma_cookie_assign(tx);
478 list_add_tail(&desc->xfer_node, &atchan->xfers_list);
479 spin_unlock_irqrestore(&atchan->lock, irqflags);
481 dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n",
482 __func__, atchan, desc);
487 static struct at_xdmac_desc *at_xdmac_alloc_desc(struct dma_chan *chan,
490 struct at_xdmac_desc *desc;
491 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
494 desc = dma_pool_zalloc(atxdmac->at_xdmac_desc_pool, gfp_flags, &phys);
496 INIT_LIST_HEAD(&desc->descs_list);
497 dma_async_tx_descriptor_init(&desc->tx_dma_desc, chan);
498 desc->tx_dma_desc.tx_submit = at_xdmac_tx_submit;
499 desc->tx_dma_desc.phys = phys;
505 static void at_xdmac_init_used_desc(struct at_xdmac_desc *desc)
507 memset(&desc->lld, 0, sizeof(desc->lld));
508 INIT_LIST_HEAD(&desc->descs_list);
509 desc->direction = DMA_TRANS_NONE;
511 desc->active_xfer = false;
514 /* Call must be protected by lock. */
515 static struct at_xdmac_desc *at_xdmac_get_desc(struct at_xdmac_chan *atchan)
517 struct at_xdmac_desc *desc;
519 if (list_empty(&atchan->free_descs_list)) {
520 desc = at_xdmac_alloc_desc(&atchan->chan, GFP_NOWAIT);
522 desc = list_first_entry(&atchan->free_descs_list,
523 struct at_xdmac_desc, desc_node);
524 list_del(&desc->desc_node);
525 at_xdmac_init_used_desc(desc);
531 static void at_xdmac_queue_desc(struct dma_chan *chan,
532 struct at_xdmac_desc *prev,
533 struct at_xdmac_desc *desc)
538 prev->lld.mbr_nda = desc->tx_dma_desc.phys;
539 prev->lld.mbr_ubc |= AT_XDMAC_MBR_UBC_NDE;
541 dev_dbg(chan2dev(chan), "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
542 __func__, prev, &prev->lld.mbr_nda);
545 static inline void at_xdmac_increment_block_count(struct dma_chan *chan,
546 struct at_xdmac_desc *desc)
553 dev_dbg(chan2dev(chan),
554 "%s: incrementing the block count of the desc 0x%p\n",
558 static struct dma_chan *at_xdmac_xlate(struct of_phandle_args *dma_spec,
559 struct of_dma *of_dma)
561 struct at_xdmac *atxdmac = of_dma->of_dma_data;
562 struct at_xdmac_chan *atchan;
563 struct dma_chan *chan;
564 struct device *dev = atxdmac->dma.dev;
566 if (dma_spec->args_count != 1) {
567 dev_err(dev, "dma phandler args: bad number of args\n");
571 chan = dma_get_any_slave_channel(&atxdmac->dma);
573 dev_err(dev, "can't get a dma channel\n");
577 atchan = to_at_xdmac_chan(chan);
578 atchan->memif = AT91_XDMAC_DT_GET_MEM_IF(dma_spec->args[0]);
579 atchan->perif = AT91_XDMAC_DT_GET_PER_IF(dma_spec->args[0]);
580 atchan->perid = AT91_XDMAC_DT_GET_PERID(dma_spec->args[0]);
581 dev_dbg(dev, "chan dt cfg: memif=%u perif=%u perid=%u\n",
582 atchan->memif, atchan->perif, atchan->perid);
587 static int at_xdmac_compute_chan_conf(struct dma_chan *chan,
588 enum dma_transfer_direction direction)
590 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
591 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
594 if (direction == DMA_DEV_TO_MEM) {
596 AT91_XDMAC_DT_PERID(atchan->perid)
597 | AT_XDMAC_CC_DAM_INCREMENTED_AM
598 | AT_XDMAC_CC_SAM_FIXED_AM
599 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
600 | AT_XDMAC_CC_DSYNC_PER2MEM
601 | AT_XDMAC_CC_MBSIZE_SIXTEEN
602 | AT_XDMAC_CC_TYPE_PER_TRAN;
603 if (atxdmac->layout->sdif)
604 atchan->cfg |= AT_XDMAC_CC_DIF(atchan->memif) |
605 AT_XDMAC_CC_SIF(atchan->perif);
607 csize = ffs(atchan->sconfig.src_maxburst) - 1;
609 dev_err(chan2dev(chan), "invalid src maxburst value\n");
612 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
613 dwidth = ffs(atchan->sconfig.src_addr_width) - 1;
615 dev_err(chan2dev(chan), "invalid src addr width value\n");
618 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
619 } else if (direction == DMA_MEM_TO_DEV) {
621 AT91_XDMAC_DT_PERID(atchan->perid)
622 | AT_XDMAC_CC_DAM_FIXED_AM
623 | AT_XDMAC_CC_SAM_INCREMENTED_AM
624 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
625 | AT_XDMAC_CC_DSYNC_MEM2PER
626 | AT_XDMAC_CC_MBSIZE_SIXTEEN
627 | AT_XDMAC_CC_TYPE_PER_TRAN;
628 if (atxdmac->layout->sdif)
629 atchan->cfg |= AT_XDMAC_CC_DIF(atchan->perif) |
630 AT_XDMAC_CC_SIF(atchan->memif);
632 csize = ffs(atchan->sconfig.dst_maxburst) - 1;
634 dev_err(chan2dev(chan), "invalid src maxburst value\n");
637 atchan->cfg |= AT_XDMAC_CC_CSIZE(csize);
638 dwidth = ffs(atchan->sconfig.dst_addr_width) - 1;
640 dev_err(chan2dev(chan), "invalid dst addr width value\n");
643 atchan->cfg |= AT_XDMAC_CC_DWIDTH(dwidth);
646 dev_dbg(chan2dev(chan), "%s: cfg=0x%08x\n", __func__, atchan->cfg);
652 * Only check that maxburst and addr width values are supported by the
653 * the controller but not that the configuration is good to perform the
654 * transfer since we don't know the direction at this stage.
656 static int at_xdmac_check_slave_config(struct dma_slave_config *sconfig)
658 if ((sconfig->src_maxburst > AT_XDMAC_MAX_CSIZE)
659 || (sconfig->dst_maxburst > AT_XDMAC_MAX_CSIZE))
662 if ((sconfig->src_addr_width > AT_XDMAC_MAX_DWIDTH)
663 || (sconfig->dst_addr_width > AT_XDMAC_MAX_DWIDTH))
669 static int at_xdmac_set_slave_config(struct dma_chan *chan,
670 struct dma_slave_config *sconfig)
672 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
674 if (at_xdmac_check_slave_config(sconfig)) {
675 dev_err(chan2dev(chan), "invalid slave configuration\n");
679 memcpy(&atchan->sconfig, sconfig, sizeof(atchan->sconfig));
684 static struct dma_async_tx_descriptor *
685 at_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
686 unsigned int sg_len, enum dma_transfer_direction direction,
687 unsigned long flags, void *context)
689 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
690 struct at_xdmac_desc *first = NULL, *prev = NULL;
691 struct scatterlist *sg;
693 unsigned int xfer_size = 0;
694 unsigned long irqflags;
695 struct dma_async_tx_descriptor *ret = NULL;
700 if (!is_slave_direction(direction)) {
701 dev_err(chan2dev(chan), "invalid DMA direction\n");
705 dev_dbg(chan2dev(chan), "%s: sg_len=%d, dir=%s, flags=0x%lx\n",
707 direction == DMA_MEM_TO_DEV ? "to device" : "from device",
710 /* Protect dma_sconfig field that can be modified by set_slave_conf. */
711 spin_lock_irqsave(&atchan->lock, irqflags);
713 if (at_xdmac_compute_chan_conf(chan, direction))
716 /* Prepare descriptors. */
717 for_each_sg(sgl, sg, sg_len, i) {
718 struct at_xdmac_desc *desc = NULL;
719 u32 len, mem, dwidth, fixed_dwidth;
721 len = sg_dma_len(sg);
722 mem = sg_dma_address(sg);
723 if (unlikely(!len)) {
724 dev_err(chan2dev(chan), "sg data length is zero\n");
727 dev_dbg(chan2dev(chan), "%s: * sg%d len=%u, mem=0x%08x\n",
728 __func__, i, len, mem);
730 desc = at_xdmac_get_desc(atchan);
732 dev_err(chan2dev(chan), "can't get descriptor\n");
734 list_splice_init(&first->descs_list, &atchan->free_descs_list);
738 /* Linked list descriptor setup. */
739 if (direction == DMA_DEV_TO_MEM) {
740 desc->lld.mbr_sa = atchan->sconfig.src_addr;
741 desc->lld.mbr_da = mem;
743 desc->lld.mbr_sa = mem;
744 desc->lld.mbr_da = atchan->sconfig.dst_addr;
746 dwidth = at_xdmac_get_dwidth(atchan->cfg);
747 fixed_dwidth = IS_ALIGNED(len, 1 << dwidth)
749 : AT_XDMAC_CC_DWIDTH_BYTE;
750 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2 /* next descriptor view */
751 | AT_XDMAC_MBR_UBC_NDEN /* next descriptor dst parameter update */
752 | AT_XDMAC_MBR_UBC_NSEN /* next descriptor src parameter update */
753 | (len >> fixed_dwidth); /* microblock length */
754 desc->lld.mbr_cfg = (atchan->cfg & ~AT_XDMAC_CC_DWIDTH_MASK) |
755 AT_XDMAC_CC_DWIDTH(fixed_dwidth);
756 dev_dbg(chan2dev(chan),
757 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
758 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
762 at_xdmac_queue_desc(chan, prev, desc);
768 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
769 __func__, desc, first);
770 list_add_tail(&desc->desc_node, &first->descs_list);
775 first->tx_dma_desc.flags = flags;
776 first->xfer_size = xfer_size;
777 first->direction = direction;
778 ret = &first->tx_dma_desc;
781 spin_unlock_irqrestore(&atchan->lock, irqflags);
785 static struct dma_async_tx_descriptor *
786 at_xdmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
787 size_t buf_len, size_t period_len,
788 enum dma_transfer_direction direction,
791 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
792 struct at_xdmac_desc *first = NULL, *prev = NULL;
793 unsigned int periods = buf_len / period_len;
795 unsigned long irqflags;
797 dev_dbg(chan2dev(chan), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n",
798 __func__, &buf_addr, buf_len, period_len,
799 direction == DMA_MEM_TO_DEV ? "mem2per" : "per2mem", flags);
801 if (!is_slave_direction(direction)) {
802 dev_err(chan2dev(chan), "invalid DMA direction\n");
806 if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status)) {
807 dev_err(chan2dev(chan), "channel currently used\n");
811 if (at_xdmac_compute_chan_conf(chan, direction))
814 for (i = 0; i < periods; i++) {
815 struct at_xdmac_desc *desc = NULL;
817 spin_lock_irqsave(&atchan->lock, irqflags);
818 desc = at_xdmac_get_desc(atchan);
820 dev_err(chan2dev(chan), "can't get descriptor\n");
822 list_splice_init(&first->descs_list, &atchan->free_descs_list);
823 spin_unlock_irqrestore(&atchan->lock, irqflags);
826 spin_unlock_irqrestore(&atchan->lock, irqflags);
827 dev_dbg(chan2dev(chan),
828 "%s: desc=0x%p, tx_dma_desc.phys=%pad\n",
829 __func__, desc, &desc->tx_dma_desc.phys);
831 if (direction == DMA_DEV_TO_MEM) {
832 desc->lld.mbr_sa = atchan->sconfig.src_addr;
833 desc->lld.mbr_da = buf_addr + i * period_len;
835 desc->lld.mbr_sa = buf_addr + i * period_len;
836 desc->lld.mbr_da = atchan->sconfig.dst_addr;
838 desc->lld.mbr_cfg = atchan->cfg;
839 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV1
840 | AT_XDMAC_MBR_UBC_NDEN
841 | AT_XDMAC_MBR_UBC_NSEN
842 | period_len >> at_xdmac_get_dwidth(desc->lld.mbr_cfg);
844 dev_dbg(chan2dev(chan),
845 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
846 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc);
850 at_xdmac_queue_desc(chan, prev, desc);
856 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
857 __func__, desc, first);
858 list_add_tail(&desc->desc_node, &first->descs_list);
861 at_xdmac_queue_desc(chan, prev, first);
862 first->tx_dma_desc.flags = flags;
863 first->xfer_size = buf_len;
864 first->direction = direction;
866 return &first->tx_dma_desc;
869 static inline u32 at_xdmac_align_width(struct dma_chan *chan, dma_addr_t addr)
874 * Check address alignment to select the greater data width we
877 * Some XDMAC implementations don't provide dword transfer, in
878 * this case selecting dword has the same behavior as
879 * selecting word transfers.
882 width = AT_XDMAC_CC_DWIDTH_DWORD;
883 dev_dbg(chan2dev(chan), "%s: dwidth: double word\n", __func__);
884 } else if (!(addr & 3)) {
885 width = AT_XDMAC_CC_DWIDTH_WORD;
886 dev_dbg(chan2dev(chan), "%s: dwidth: word\n", __func__);
887 } else if (!(addr & 1)) {
888 width = AT_XDMAC_CC_DWIDTH_HALFWORD;
889 dev_dbg(chan2dev(chan), "%s: dwidth: half word\n", __func__);
891 width = AT_XDMAC_CC_DWIDTH_BYTE;
892 dev_dbg(chan2dev(chan), "%s: dwidth: byte\n", __func__);
898 static struct at_xdmac_desc *
899 at_xdmac_interleaved_queue_desc(struct dma_chan *chan,
900 struct at_xdmac_chan *atchan,
901 struct at_xdmac_desc *prev,
902 dma_addr_t src, dma_addr_t dst,
903 struct dma_interleaved_template *xt,
904 struct data_chunk *chunk)
906 struct at_xdmac_desc *desc;
911 * WARNING: The channel configuration is set here since there is no
912 * dmaengine_slave_config call in this case. Moreover we don't know the
913 * direction, it involves we can't dynamically set the source and dest
914 * interface so we have to use the same one. Only interface 0 allows EBI
915 * access. Hopefully we can access DDR through both ports (at least on
916 * SAMA5D4x), so we can use the same interface for source and dest,
917 * that solves the fact we don't know the direction.
918 * ERRATA: Even if useless for memory transfers, the PERID has to not
919 * match the one of another channel. If not, it could lead to spurious
921 * For SAMA7G5x case, the SIF and DIF fields are no longer used.
922 * Thus, no need to have the SIF/DIF interfaces here.
923 * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as
926 u32 chan_cc = AT_XDMAC_CC_PERID(0x7f)
927 | AT_XDMAC_CC_MBSIZE_SIXTEEN
928 | AT_XDMAC_CC_TYPE_MEM_TRAN;
930 dwidth = at_xdmac_align_width(chan, src | dst | chunk->size);
931 if (chunk->size >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
932 dev_dbg(chan2dev(chan),
933 "%s: chunk too big (%zu, max size %lu)...\n",
934 __func__, chunk->size,
935 AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth);
940 dev_dbg(chan2dev(chan),
941 "Adding items at the end of desc 0x%p\n", prev);
945 chan_cc |= AT_XDMAC_CC_SAM_UBS_AM;
947 chan_cc |= AT_XDMAC_CC_SAM_INCREMENTED_AM;
952 chan_cc |= AT_XDMAC_CC_DAM_UBS_AM;
954 chan_cc |= AT_XDMAC_CC_DAM_INCREMENTED_AM;
957 spin_lock_irqsave(&atchan->lock, flags);
958 desc = at_xdmac_get_desc(atchan);
959 spin_unlock_irqrestore(&atchan->lock, flags);
961 dev_err(chan2dev(chan), "can't get descriptor\n");
965 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
967 ublen = chunk->size >> dwidth;
969 desc->lld.mbr_sa = src;
970 desc->lld.mbr_da = dst;
971 desc->lld.mbr_sus = dmaengine_get_src_icg(xt, chunk);
972 desc->lld.mbr_dus = dmaengine_get_dst_icg(xt, chunk);
974 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
975 | AT_XDMAC_MBR_UBC_NDEN
976 | AT_XDMAC_MBR_UBC_NSEN
978 desc->lld.mbr_cfg = chan_cc;
980 dev_dbg(chan2dev(chan),
981 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
982 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da,
983 desc->lld.mbr_ubc, desc->lld.mbr_cfg);
987 at_xdmac_queue_desc(chan, prev, desc);
992 static struct dma_async_tx_descriptor *
993 at_xdmac_prep_interleaved(struct dma_chan *chan,
994 struct dma_interleaved_template *xt,
997 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
998 struct at_xdmac_desc *prev = NULL, *first = NULL;
999 dma_addr_t dst_addr, src_addr;
1000 size_t src_skip = 0, dst_skip = 0, len = 0;
1001 struct data_chunk *chunk;
1004 if (!xt || !xt->numf || (xt->dir != DMA_MEM_TO_MEM))
1008 * TODO: Handle the case where we have to repeat a chain of
1011 if ((xt->numf > 1) && (xt->frame_size > 1))
1014 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, numf=%zu, frame_size=%zu, flags=0x%lx\n",
1015 __func__, &xt->src_start, &xt->dst_start, xt->numf,
1016 xt->frame_size, flags);
1018 src_addr = xt->src_start;
1019 dst_addr = xt->dst_start;
1022 first = at_xdmac_interleaved_queue_desc(chan, atchan,
1027 /* Length of the block is (BLEN+1) microblocks. */
1028 for (i = 0; i < xt->numf - 1; i++)
1029 at_xdmac_increment_block_count(chan, first);
1031 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1032 __func__, first, first);
1033 list_add_tail(&first->desc_node, &first->descs_list);
1035 for (i = 0; i < xt->frame_size; i++) {
1036 size_t src_icg = 0, dst_icg = 0;
1037 struct at_xdmac_desc *desc;
1039 chunk = xt->sgl + i;
1041 dst_icg = dmaengine_get_dst_icg(xt, chunk);
1042 src_icg = dmaengine_get_src_icg(xt, chunk);
1044 src_skip = chunk->size + src_icg;
1045 dst_skip = chunk->size + dst_icg;
1047 dev_dbg(chan2dev(chan),
1048 "%s: chunk size=%zu, src icg=%zu, dst icg=%zu\n",
1049 __func__, chunk->size, src_icg, dst_icg);
1051 desc = at_xdmac_interleaved_queue_desc(chan, atchan,
1056 list_splice_init(&first->descs_list,
1057 &atchan->free_descs_list);
1064 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1065 __func__, desc, first);
1066 list_add_tail(&desc->desc_node, &first->descs_list);
1069 src_addr += src_skip;
1072 dst_addr += dst_skip;
1079 first->tx_dma_desc.cookie = -EBUSY;
1080 first->tx_dma_desc.flags = flags;
1081 first->xfer_size = len;
1083 return &first->tx_dma_desc;
1086 static struct dma_async_tx_descriptor *
1087 at_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1088 size_t len, unsigned long flags)
1090 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1091 struct at_xdmac_desc *first = NULL, *prev = NULL;
1092 size_t remaining_size = len, xfer_size = 0, ublen;
1093 dma_addr_t src_addr = src, dst_addr = dest;
1096 * WARNING: We don't know the direction, it involves we can't
1097 * dynamically set the source and dest interface so we have to use the
1098 * same one. Only interface 0 allows EBI access. Hopefully we can
1099 * access DDR through both ports (at least on SAMA5D4x), so we can use
1100 * the same interface for source and dest, that solves the fact we
1101 * don't know the direction.
1102 * ERRATA: Even if useless for memory transfers, the PERID has to not
1103 * match the one of another channel. If not, it could lead to spurious
1105 * For SAMA7G5x case, the SIF and DIF fields are no longer used.
1106 * Thus, no need to have the SIF/DIF interfaces here.
1107 * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as
1110 u32 chan_cc = AT_XDMAC_CC_PERID(0x7f)
1111 | AT_XDMAC_CC_DAM_INCREMENTED_AM
1112 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1113 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1114 | AT_XDMAC_CC_TYPE_MEM_TRAN;
1115 unsigned long irqflags;
1117 dev_dbg(chan2dev(chan), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n",
1118 __func__, &src, &dest, len, flags);
1123 dwidth = at_xdmac_align_width(chan, src_addr | dst_addr);
1125 /* Prepare descriptors. */
1126 while (remaining_size) {
1127 struct at_xdmac_desc *desc = NULL;
1129 dev_dbg(chan2dev(chan), "%s: remaining_size=%zu\n", __func__, remaining_size);
1131 spin_lock_irqsave(&atchan->lock, irqflags);
1132 desc = at_xdmac_get_desc(atchan);
1133 spin_unlock_irqrestore(&atchan->lock, irqflags);
1135 dev_err(chan2dev(chan), "can't get descriptor\n");
1137 list_splice_init(&first->descs_list, &atchan->free_descs_list);
1141 /* Update src and dest addresses. */
1142 src_addr += xfer_size;
1143 dst_addr += xfer_size;
1145 if (remaining_size >= AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)
1146 xfer_size = AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth;
1148 xfer_size = remaining_size;
1150 dev_dbg(chan2dev(chan), "%s: xfer_size=%zu\n", __func__, xfer_size);
1152 /* Check remaining length and change data width if needed. */
1153 dwidth = at_xdmac_align_width(chan,
1154 src_addr | dst_addr | xfer_size);
1155 chan_cc &= ~AT_XDMAC_CC_DWIDTH_MASK;
1156 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1158 ublen = xfer_size >> dwidth;
1159 remaining_size -= xfer_size;
1161 desc->lld.mbr_sa = src_addr;
1162 desc->lld.mbr_da = dst_addr;
1163 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV2
1164 | AT_XDMAC_MBR_UBC_NDEN
1165 | AT_XDMAC_MBR_UBC_NSEN
1167 desc->lld.mbr_cfg = chan_cc;
1169 dev_dbg(chan2dev(chan),
1170 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1171 __func__, &desc->lld.mbr_sa, &desc->lld.mbr_da, desc->lld.mbr_ubc, desc->lld.mbr_cfg);
1175 at_xdmac_queue_desc(chan, prev, desc);
1181 dev_dbg(chan2dev(chan), "%s: add desc 0x%p to descs_list 0x%p\n",
1182 __func__, desc, first);
1183 list_add_tail(&desc->desc_node, &first->descs_list);
1186 first->tx_dma_desc.flags = flags;
1187 first->xfer_size = len;
1189 return &first->tx_dma_desc;
1192 static struct at_xdmac_desc *at_xdmac_memset_create_desc(struct dma_chan *chan,
1193 struct at_xdmac_chan *atchan,
1194 dma_addr_t dst_addr,
1198 struct at_xdmac_desc *desc;
1199 unsigned long flags;
1203 * WARNING: The channel configuration is set here since there is no
1204 * dmaengine_slave_config call in this case. Moreover we don't know the
1205 * direction, it involves we can't dynamically set the source and dest
1206 * interface so we have to use the same one. Only interface 0 allows EBI
1207 * access. Hopefully we can access DDR through both ports (at least on
1208 * SAMA5D4x), so we can use the same interface for source and dest,
1209 * that solves the fact we don't know the direction.
1210 * ERRATA: Even if useless for memory transfers, the PERID has to not
1211 * match the one of another channel. If not, it could lead to spurious
1213 * For SAMA7G5x case, the SIF and DIF fields are no longer used.
1214 * Thus, no need to have the SIF/DIF interfaces here.
1215 * For SAMA5D4x and SAMA5D2x the SIF and DIF are already configured as
1218 u32 chan_cc = AT_XDMAC_CC_PERID(0x7f)
1219 | AT_XDMAC_CC_DAM_UBS_AM
1220 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1221 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1222 | AT_XDMAC_CC_MEMSET_HW_MODE
1223 | AT_XDMAC_CC_TYPE_MEM_TRAN;
1225 dwidth = at_xdmac_align_width(chan, dst_addr);
1227 if (len >= (AT_XDMAC_MBR_UBC_UBLEN_MAX << dwidth)) {
1228 dev_err(chan2dev(chan),
1229 "%s: Transfer too large, aborting...\n",
1234 spin_lock_irqsave(&atchan->lock, flags);
1235 desc = at_xdmac_get_desc(atchan);
1236 spin_unlock_irqrestore(&atchan->lock, flags);
1238 dev_err(chan2dev(chan), "can't get descriptor\n");
1242 chan_cc |= AT_XDMAC_CC_DWIDTH(dwidth);
1244 ublen = len >> dwidth;
1246 desc->lld.mbr_da = dst_addr;
1247 desc->lld.mbr_ds = value;
1248 desc->lld.mbr_ubc = AT_XDMAC_MBR_UBC_NDV3
1249 | AT_XDMAC_MBR_UBC_NDEN
1250 | AT_XDMAC_MBR_UBC_NSEN
1252 desc->lld.mbr_cfg = chan_cc;
1254 dev_dbg(chan2dev(chan),
1255 "%s: lld: mbr_da=%pad, mbr_ds=0x%08x, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1256 __func__, &desc->lld.mbr_da, desc->lld.mbr_ds, desc->lld.mbr_ubc,
1262 static struct dma_async_tx_descriptor *
1263 at_xdmac_prep_dma_memset(struct dma_chan *chan, dma_addr_t dest, int value,
1264 size_t len, unsigned long flags)
1266 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1267 struct at_xdmac_desc *desc;
1269 dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%zu, pattern=0x%x, flags=0x%lx\n",
1270 __func__, &dest, len, value, flags);
1275 desc = at_xdmac_memset_create_desc(chan, atchan, dest, len, value);
1276 list_add_tail(&desc->desc_node, &desc->descs_list);
1278 desc->tx_dma_desc.cookie = -EBUSY;
1279 desc->tx_dma_desc.flags = flags;
1280 desc->xfer_size = len;
1282 return &desc->tx_dma_desc;
1285 static struct dma_async_tx_descriptor *
1286 at_xdmac_prep_dma_memset_sg(struct dma_chan *chan, struct scatterlist *sgl,
1287 unsigned int sg_len, int value,
1288 unsigned long flags)
1290 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1291 struct at_xdmac_desc *desc, *pdesc = NULL,
1292 *ppdesc = NULL, *first = NULL;
1293 struct scatterlist *sg, *psg = NULL, *ppsg = NULL;
1294 size_t stride = 0, pstride = 0, len = 0;
1300 dev_dbg(chan2dev(chan), "%s: sg_len=%d, value=0x%x, flags=0x%lx\n",
1301 __func__, sg_len, value, flags);
1303 /* Prepare descriptors. */
1304 for_each_sg(sgl, sg, sg_len, i) {
1305 dev_dbg(chan2dev(chan), "%s: dest=%pad, len=%d, pattern=0x%x, flags=0x%lx\n",
1306 __func__, &sg_dma_address(sg), sg_dma_len(sg),
1308 desc = at_xdmac_memset_create_desc(chan, atchan,
1313 list_splice_init(&first->descs_list,
1314 &atchan->free_descs_list);
1319 /* Update our strides */
1322 stride = sg_dma_address(sg) -
1323 (sg_dma_address(psg) + sg_dma_len(psg));
1326 * The scatterlist API gives us only the address and
1327 * length of each elements.
1329 * Unfortunately, we don't have the stride, which we
1330 * will need to compute.
1332 * That make us end up in a situation like this one:
1333 * len stride len stride len
1334 * +-------+ +-------+ +-------+
1335 * | N-2 | | N-1 | | N |
1336 * +-------+ +-------+ +-------+
1338 * We need all these three elements (N-2, N-1 and N)
1339 * to actually take the decision on whether we need to
1340 * queue N-1 or reuse N-2.
1342 * We will only consider N if it is the last element.
1344 if (ppdesc && pdesc) {
1345 if ((stride == pstride) &&
1346 (sg_dma_len(ppsg) == sg_dma_len(psg))) {
1347 dev_dbg(chan2dev(chan),
1348 "%s: desc 0x%p can be merged with desc 0x%p\n",
1349 __func__, pdesc, ppdesc);
1352 * Increment the block count of the
1355 at_xdmac_increment_block_count(chan, ppdesc);
1356 ppdesc->lld.mbr_dus = stride;
1359 * Put back the N-1 descriptor in the
1360 * free descriptor list
1362 list_add_tail(&pdesc->desc_node,
1363 &atchan->free_descs_list);
1366 * Make our N-1 descriptor pointer
1367 * point to the N-2 since they were
1373 * Rule out the case where we don't have
1374 * pstride computed yet (our second sg
1377 * We also want to catch the case where there
1378 * would be a negative stride,
1380 } else if (pstride ||
1381 sg_dma_address(sg) < sg_dma_address(psg)) {
1383 * Queue the N-1 descriptor after the
1386 at_xdmac_queue_desc(chan, ppdesc, pdesc);
1389 * Add the N-1 descriptor to the list
1390 * of the descriptors used for this
1393 list_add_tail(&desc->desc_node,
1394 &first->descs_list);
1395 dev_dbg(chan2dev(chan),
1396 "%s: add desc 0x%p to descs_list 0x%p\n",
1397 __func__, desc, first);
1402 * If we are the last element, just see if we have the
1403 * same size than the previous element.
1405 * If so, we can merge it with the previous descriptor
1406 * since we don't care about the stride anymore.
1408 if ((i == (sg_len - 1)) &&
1409 sg_dma_len(psg) == sg_dma_len(sg)) {
1410 dev_dbg(chan2dev(chan),
1411 "%s: desc 0x%p can be merged with desc 0x%p\n",
1412 __func__, desc, pdesc);
1415 * Increment the block count of the N-1
1418 at_xdmac_increment_block_count(chan, pdesc);
1419 pdesc->lld.mbr_dus = stride;
1422 * Put back the N descriptor in the free
1425 list_add_tail(&desc->desc_node,
1426 &atchan->free_descs_list);
1429 /* Update our descriptors */
1433 /* Update our scatter pointers */
1437 len += sg_dma_len(sg);
1440 first->tx_dma_desc.cookie = -EBUSY;
1441 first->tx_dma_desc.flags = flags;
1442 first->xfer_size = len;
1444 return &first->tx_dma_desc;
1447 static enum dma_status
1448 at_xdmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1449 struct dma_tx_state *txstate)
1451 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1452 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1453 struct at_xdmac_desc *desc, *_desc, *iter;
1454 struct list_head *descs_list;
1455 enum dma_status ret;
1457 u32 cur_nda, check_nda, cur_ubc, mask, value;
1459 unsigned long flags;
1462 ret = dma_cookie_status(chan, cookie, txstate);
1463 if (ret == DMA_COMPLETE)
1469 spin_lock_irqsave(&atchan->lock, flags);
1471 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc, xfer_node);
1474 * If the transfer has not been started yet, don't need to compute the
1475 * residue, it's the transfer length.
1477 if (!desc->active_xfer) {
1478 dma_set_residue(txstate, desc->xfer_size);
1482 residue = desc->xfer_size;
1484 * Flush FIFO: only relevant when the transfer is source peripheral
1485 * synchronized. Flush is needed before reading CUBC because data in
1486 * the FIFO are not reported by CUBC. Reporting a residue of the
1487 * transfer length while we have data in FIFO can cause issue.
1488 * Usecase: atmel USART has a timeout which means I have received
1489 * characters but there is no more character received for a while. On
1490 * timeout, it requests the residue. If the data are in the DMA FIFO,
1491 * we will return a residue of the transfer length. It means no data
1492 * received. If an application is waiting for these data, it will hang
1493 * since we won't have another USART timeout without receiving new
1496 mask = AT_XDMAC_CC_TYPE | AT_XDMAC_CC_DSYNC;
1497 value = AT_XDMAC_CC_TYPE_PER_TRAN | AT_XDMAC_CC_DSYNC_PER2MEM;
1498 if ((desc->lld.mbr_cfg & mask) == value) {
1499 at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask);
1500 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
1505 * The easiest way to compute the residue should be to pause the DMA
1506 * but doing this can lead to miss some data as some devices don't
1508 * We need to read several registers because:
1509 * - DMA is running therefore a descriptor change is possible while
1510 * reading these registers
1511 * - When the block transfer is done, the value of the CUBC register
1512 * is set to its initial value until the fetch of the next descriptor.
1513 * This value will corrupt the residue calculation so we have to skip
1516 * INITD -------- ------------
1517 * |____________________|
1518 * _______________________ _______________
1519 * NDA @desc2 \/ @desc3
1520 * _______________________/\_______________
1521 * __________ ___________ _______________
1522 * CUBC 0 \/ MAX desc1 \/ MAX desc2
1523 * __________/\___________/\_______________
1525 * Since descriptors are aligned on 64 bits, we can assume that
1526 * the update of NDA and CUBC is atomic.
1527 * Memory barriers are used to ensure the read order of the registers.
1528 * A max number of retries is set because unlikely it could never ends.
1530 for (retry = 0; retry < AT_XDMAC_RESIDUE_MAX_RETRIES; retry++) {
1531 check_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
1533 cur_ubc = at_xdmac_chan_read(atchan, AT_XDMAC_CUBC);
1535 initd = !!(at_xdmac_chan_read(atchan, AT_XDMAC_CC) & AT_XDMAC_CC_INITD);
1537 cur_nda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA) & 0xfffffffc;
1540 if ((check_nda == cur_nda) && initd)
1544 if (unlikely(retry >= AT_XDMAC_RESIDUE_MAX_RETRIES)) {
1550 * Flush FIFO: only relevant when the transfer is source peripheral
1551 * synchronized. Another flush is needed here because CUBC is updated
1552 * when the controller sends the data write command. It can lead to
1553 * report data that are not written in the memory or the device. The
1554 * FIFO flush ensures that data are really written.
1556 if ((desc->lld.mbr_cfg & mask) == value) {
1557 at_xdmac_write(atxdmac, atxdmac->layout->gswf, atchan->mask);
1558 while (!(at_xdmac_chan_read(atchan, AT_XDMAC_CIS) & AT_XDMAC_CIS_FIS))
1563 * Remove size of all microblocks already transferred and the current
1564 * one. Then add the remaining size to transfer of the current
1567 descs_list = &desc->descs_list;
1568 list_for_each_entry_safe(iter, _desc, descs_list, desc_node) {
1569 dwidth = at_xdmac_get_dwidth(iter->lld.mbr_cfg);
1570 residue -= (iter->lld.mbr_ubc & 0xffffff) << dwidth;
1571 if ((iter->lld.mbr_nda & 0xfffffffc) == cur_nda) {
1576 residue += cur_ubc << dwidth;
1578 dma_set_residue(txstate, residue);
1580 dev_dbg(chan2dev(chan),
1581 "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n",
1582 __func__, desc, &desc->tx_dma_desc.phys, ret, cookie, residue);
1585 spin_unlock_irqrestore(&atchan->lock, flags);
1589 /* Call must be protected by lock. */
1590 static void at_xdmac_remove_xfer(struct at_xdmac_chan *atchan,
1591 struct at_xdmac_desc *desc)
1593 dev_dbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1596 * Remove the transfer from the transfer list then move the transfer
1597 * descriptors into the free descriptors list.
1599 list_del(&desc->xfer_node);
1600 list_splice_init(&desc->descs_list, &atchan->free_descs_list);
1603 static void at_xdmac_advance_work(struct at_xdmac_chan *atchan)
1605 struct at_xdmac_desc *desc;
1608 * If channel is enabled, do nothing, advance_work will be triggered
1609 * after the interruption.
1611 if (!at_xdmac_chan_is_enabled(atchan) && !list_empty(&atchan->xfers_list)) {
1612 desc = list_first_entry(&atchan->xfers_list,
1613 struct at_xdmac_desc,
1615 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1616 if (!desc->active_xfer)
1617 at_xdmac_start_xfer(atchan, desc);
1621 static void at_xdmac_handle_cyclic(struct at_xdmac_chan *atchan)
1623 struct at_xdmac_desc *desc;
1624 struct dma_async_tx_descriptor *txd;
1626 spin_lock_irq(&atchan->lock);
1627 if (list_empty(&atchan->xfers_list)) {
1628 spin_unlock_irq(&atchan->lock);
1631 desc = list_first_entry(&atchan->xfers_list, struct at_xdmac_desc,
1633 spin_unlock_irq(&atchan->lock);
1634 txd = &desc->tx_dma_desc;
1635 if (txd->flags & DMA_PREP_INTERRUPT)
1636 dmaengine_desc_get_callback_invoke(txd, NULL);
1639 static void at_xdmac_handle_error(struct at_xdmac_chan *atchan)
1641 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1642 struct at_xdmac_desc *bad_desc;
1645 * The descriptor currently at the head of the active list is
1646 * broken. Since we don't have any way to report errors, we'll
1647 * just have to scream loudly and try to continue with other
1648 * descriptors queued (if any).
1650 if (atchan->irq_status & AT_XDMAC_CIS_RBEIS)
1651 dev_err(chan2dev(&atchan->chan), "read bus error!!!");
1652 if (atchan->irq_status & AT_XDMAC_CIS_WBEIS)
1653 dev_err(chan2dev(&atchan->chan), "write bus error!!!");
1654 if (atchan->irq_status & AT_XDMAC_CIS_ROIS)
1655 dev_err(chan2dev(&atchan->chan), "request overflow error!!!");
1657 spin_lock_irq(&atchan->lock);
1659 /* Channel must be disabled first as it's not done automatically */
1660 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1661 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
1664 bad_desc = list_first_entry(&atchan->xfers_list,
1665 struct at_xdmac_desc,
1668 spin_unlock_irq(&atchan->lock);
1670 /* Print bad descriptor's details if needed */
1671 dev_dbg(chan2dev(&atchan->chan),
1672 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
1673 __func__, &bad_desc->lld.mbr_sa, &bad_desc->lld.mbr_da,
1674 bad_desc->lld.mbr_ubc);
1676 /* Then continue with usual descriptor management */
1679 static void at_xdmac_tasklet(struct tasklet_struct *t)
1681 struct at_xdmac_chan *atchan = from_tasklet(atchan, t, tasklet);
1682 struct at_xdmac_desc *desc;
1685 dev_dbg(chan2dev(&atchan->chan), "%s: status=0x%08x\n",
1686 __func__, atchan->irq_status);
1688 error_mask = AT_XDMAC_CIS_RBEIS
1689 | AT_XDMAC_CIS_WBEIS
1690 | AT_XDMAC_CIS_ROIS;
1692 if (at_xdmac_chan_is_cyclic(atchan)) {
1693 at_xdmac_handle_cyclic(atchan);
1694 } else if ((atchan->irq_status & AT_XDMAC_CIS_LIS)
1695 || (atchan->irq_status & error_mask)) {
1696 struct dma_async_tx_descriptor *txd;
1698 if (atchan->irq_status & error_mask)
1699 at_xdmac_handle_error(atchan);
1701 spin_lock_irq(&atchan->lock);
1702 desc = list_first_entry(&atchan->xfers_list,
1703 struct at_xdmac_desc,
1705 dev_vdbg(chan2dev(&atchan->chan), "%s: desc 0x%p\n", __func__, desc);
1706 if (!desc->active_xfer) {
1707 dev_err(chan2dev(&atchan->chan), "Xfer not active: exiting");
1708 spin_unlock_irq(&atchan->lock);
1712 txd = &desc->tx_dma_desc;
1714 at_xdmac_remove_xfer(atchan, desc);
1715 spin_unlock_irq(&atchan->lock);
1717 dma_cookie_complete(txd);
1718 if (txd->flags & DMA_PREP_INTERRUPT)
1719 dmaengine_desc_get_callback_invoke(txd, NULL);
1721 dma_run_dependencies(txd);
1723 spin_lock_irq(&atchan->lock);
1724 at_xdmac_advance_work(atchan);
1725 spin_unlock_irq(&atchan->lock);
1729 static irqreturn_t at_xdmac_interrupt(int irq, void *dev_id)
1731 struct at_xdmac *atxdmac = (struct at_xdmac *)dev_id;
1732 struct at_xdmac_chan *atchan;
1733 u32 imr, status, pending;
1734 u32 chan_imr, chan_status;
1735 int i, ret = IRQ_NONE;
1738 imr = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1739 status = at_xdmac_read(atxdmac, AT_XDMAC_GIS);
1740 pending = status & imr;
1742 dev_vdbg(atxdmac->dma.dev,
1743 "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n",
1744 __func__, status, imr, pending);
1749 /* We have to find which channel has generated the interrupt. */
1750 for (i = 0; i < atxdmac->dma.chancnt; i++) {
1751 if (!((1 << i) & pending))
1754 atchan = &atxdmac->chan[i];
1755 chan_imr = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1756 chan_status = at_xdmac_chan_read(atchan, AT_XDMAC_CIS);
1757 atchan->irq_status = chan_status & chan_imr;
1758 dev_vdbg(atxdmac->dma.dev,
1759 "%s: chan%d: imr=0x%x, status=0x%x\n",
1760 __func__, i, chan_imr, chan_status);
1761 dev_vdbg(chan2dev(&atchan->chan),
1762 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
1764 at_xdmac_chan_read(atchan, AT_XDMAC_CC),
1765 at_xdmac_chan_read(atchan, AT_XDMAC_CNDA),
1766 at_xdmac_chan_read(atchan, AT_XDMAC_CNDC),
1767 at_xdmac_chan_read(atchan, AT_XDMAC_CSA),
1768 at_xdmac_chan_read(atchan, AT_XDMAC_CDA),
1769 at_xdmac_chan_read(atchan, AT_XDMAC_CUBC));
1771 if (atchan->irq_status & (AT_XDMAC_CIS_RBEIS | AT_XDMAC_CIS_WBEIS))
1772 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1774 tasklet_schedule(&atchan->tasklet);
1783 static void at_xdmac_issue_pending(struct dma_chan *chan)
1785 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1786 unsigned long flags;
1788 dev_dbg(chan2dev(&atchan->chan), "%s\n", __func__);
1790 spin_lock_irqsave(&atchan->lock, flags);
1791 at_xdmac_advance_work(atchan);
1792 spin_unlock_irqrestore(&atchan->lock, flags);
1797 static int at_xdmac_device_config(struct dma_chan *chan,
1798 struct dma_slave_config *config)
1800 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1802 unsigned long flags;
1804 dev_dbg(chan2dev(chan), "%s\n", __func__);
1806 spin_lock_irqsave(&atchan->lock, flags);
1807 ret = at_xdmac_set_slave_config(chan, config);
1808 spin_unlock_irqrestore(&atchan->lock, flags);
1813 static int at_xdmac_device_pause(struct dma_chan *chan)
1815 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1816 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1817 unsigned long flags;
1819 dev_dbg(chan2dev(chan), "%s\n", __func__);
1821 if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status))
1824 spin_lock_irqsave(&atchan->lock, flags);
1825 at_xdmac_write(atxdmac, atxdmac->layout->grws, atchan->mask);
1826 while (at_xdmac_chan_read(atchan, AT_XDMAC_CC)
1827 & (AT_XDMAC_CC_WRIP | AT_XDMAC_CC_RDIP))
1829 spin_unlock_irqrestore(&atchan->lock, flags);
1834 static int at_xdmac_device_resume(struct dma_chan *chan)
1836 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1837 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1838 unsigned long flags;
1840 dev_dbg(chan2dev(chan), "%s\n", __func__);
1842 spin_lock_irqsave(&atchan->lock, flags);
1843 if (!at_xdmac_chan_is_paused(atchan)) {
1844 spin_unlock_irqrestore(&atchan->lock, flags);
1848 at_xdmac_write(atxdmac, atxdmac->layout->grwr, atchan->mask);
1849 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1850 spin_unlock_irqrestore(&atchan->lock, flags);
1855 static int at_xdmac_device_terminate_all(struct dma_chan *chan)
1857 struct at_xdmac_desc *desc, *_desc;
1858 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1859 struct at_xdmac *atxdmac = to_at_xdmac(atchan->chan.device);
1860 unsigned long flags;
1862 dev_dbg(chan2dev(chan), "%s\n", __func__);
1864 spin_lock_irqsave(&atchan->lock, flags);
1865 at_xdmac_write(atxdmac, AT_XDMAC_GD, atchan->mask);
1866 while (at_xdmac_read(atxdmac, AT_XDMAC_GS) & atchan->mask)
1869 /* Cancel all pending transfers. */
1870 list_for_each_entry_safe(desc, _desc, &atchan->xfers_list, xfer_node)
1871 at_xdmac_remove_xfer(atchan, desc);
1873 clear_bit(AT_XDMAC_CHAN_IS_PAUSED, &atchan->status);
1874 clear_bit(AT_XDMAC_CHAN_IS_CYCLIC, &atchan->status);
1875 spin_unlock_irqrestore(&atchan->lock, flags);
1880 static int at_xdmac_alloc_chan_resources(struct dma_chan *chan)
1882 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1883 struct at_xdmac_desc *desc;
1886 if (at_xdmac_chan_is_enabled(atchan)) {
1887 dev_err(chan2dev(chan),
1888 "can't allocate channel resources (channel enabled)\n");
1892 if (!list_empty(&atchan->free_descs_list)) {
1893 dev_err(chan2dev(chan),
1894 "can't allocate channel resources (channel not free from a previous use)\n");
1898 for (i = 0; i < init_nr_desc_per_channel; i++) {
1899 desc = at_xdmac_alloc_desc(chan, GFP_KERNEL);
1902 dev_warn(chan2dev(chan),
1903 "can't allocate any descriptors\n");
1906 dev_warn(chan2dev(chan),
1907 "only %d descriptors have been allocated\n", i);
1910 list_add_tail(&desc->desc_node, &atchan->free_descs_list);
1913 dma_cookie_init(chan);
1915 dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1920 static void at_xdmac_free_chan_resources(struct dma_chan *chan)
1922 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1923 struct at_xdmac *atxdmac = to_at_xdmac(chan->device);
1924 struct at_xdmac_desc *desc, *_desc;
1926 list_for_each_entry_safe(desc, _desc, &atchan->free_descs_list, desc_node) {
1927 dev_dbg(chan2dev(chan), "%s: freeing descriptor %p\n", __func__, desc);
1928 list_del(&desc->desc_node);
1929 dma_pool_free(atxdmac->at_xdmac_desc_pool, desc, desc->tx_dma_desc.phys);
1935 static void at_xdmac_axi_config(struct platform_device *pdev)
1937 struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
1938 bool dev_m2m = false;
1941 if (!atxdmac->layout->axi_config)
1942 return; /* Not supported */
1944 if (!of_property_read_u32(pdev->dev.of_node, "dma-requests",
1946 dev_info(&pdev->dev, "controller in mem2mem mode.\n");
1951 at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_M2M);
1952 at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_M2M);
1954 at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_P2M);
1955 at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_P2M);
1960 static int atmel_xdmac_prepare(struct device *dev)
1962 struct at_xdmac *atxdmac = dev_get_drvdata(dev);
1963 struct dma_chan *chan, *_chan;
1965 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1966 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1968 /* Wait for transfer completion, except in cyclic case. */
1969 if (at_xdmac_chan_is_enabled(atchan) && !at_xdmac_chan_is_cyclic(atchan))
1975 # define atmel_xdmac_prepare NULL
1978 #ifdef CONFIG_PM_SLEEP
1979 static int atmel_xdmac_suspend(struct device *dev)
1981 struct at_xdmac *atxdmac = dev_get_drvdata(dev);
1982 struct dma_chan *chan, *_chan;
1984 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
1985 struct at_xdmac_chan *atchan = to_at_xdmac_chan(chan);
1987 atchan->save_cc = at_xdmac_chan_read(atchan, AT_XDMAC_CC);
1988 if (at_xdmac_chan_is_cyclic(atchan)) {
1989 if (!at_xdmac_chan_is_paused(atchan))
1990 at_xdmac_device_pause(chan);
1991 atchan->save_cim = at_xdmac_chan_read(atchan, AT_XDMAC_CIM);
1992 atchan->save_cnda = at_xdmac_chan_read(atchan, AT_XDMAC_CNDA);
1993 atchan->save_cndc = at_xdmac_chan_read(atchan, AT_XDMAC_CNDC);
1996 atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM);
1998 at_xdmac_off(atxdmac);
1999 clk_disable_unprepare(atxdmac->clk);
2003 static int atmel_xdmac_resume(struct device *dev)
2005 struct at_xdmac *atxdmac = dev_get_drvdata(dev);
2006 struct at_xdmac_chan *atchan;
2007 struct dma_chan *chan, *_chan;
2008 struct platform_device *pdev = container_of(dev, struct platform_device, dev);
2012 ret = clk_prepare_enable(atxdmac->clk);
2016 at_xdmac_axi_config(pdev);
2018 /* Clear pending interrupts. */
2019 for (i = 0; i < atxdmac->dma.chancnt; i++) {
2020 atchan = &atxdmac->chan[i];
2021 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
2025 at_xdmac_write(atxdmac, AT_XDMAC_GIE, atxdmac->save_gim);
2026 list_for_each_entry_safe(chan, _chan, &atxdmac->dma.channels, device_node) {
2027 atchan = to_at_xdmac_chan(chan);
2028 at_xdmac_chan_write(atchan, AT_XDMAC_CC, atchan->save_cc);
2029 if (at_xdmac_chan_is_cyclic(atchan)) {
2030 if (at_xdmac_chan_is_paused(atchan))
2031 at_xdmac_device_resume(chan);
2032 at_xdmac_chan_write(atchan, AT_XDMAC_CNDA, atchan->save_cnda);
2033 at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc);
2034 at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim);
2036 at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask);
2041 #endif /* CONFIG_PM_SLEEP */
2043 static int at_xdmac_probe(struct platform_device *pdev)
2045 struct at_xdmac *atxdmac;
2046 int irq, size, nr_channels, i, ret;
2050 irq = platform_get_irq(pdev, 0);
2054 base = devm_platform_ioremap_resource(pdev, 0);
2056 return PTR_ERR(base);
2059 * Read number of xdmac channels, read helper function can't be used
2060 * since atxdmac is not yet allocated and we need to know the number
2061 * of channels to do the allocation.
2063 reg = readl_relaxed(base + AT_XDMAC_GTYPE);
2064 nr_channels = AT_XDMAC_NB_CH(reg);
2065 if (nr_channels > AT_XDMAC_MAX_CHAN) {
2066 dev_err(&pdev->dev, "invalid number of channels (%u)\n",
2071 size = sizeof(*atxdmac);
2072 size += nr_channels * sizeof(struct at_xdmac_chan);
2073 atxdmac = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
2075 dev_err(&pdev->dev, "can't allocate at_xdmac structure\n");
2079 atxdmac->regs = base;
2082 atxdmac->layout = of_device_get_match_data(&pdev->dev);
2083 if (!atxdmac->layout)
2086 atxdmac->clk = devm_clk_get(&pdev->dev, "dma_clk");
2087 if (IS_ERR(atxdmac->clk)) {
2088 dev_err(&pdev->dev, "can't get dma_clk\n");
2089 return PTR_ERR(atxdmac->clk);
2092 /* Do not use dev res to prevent races with tasklet */
2093 ret = request_irq(atxdmac->irq, at_xdmac_interrupt, 0, "at_xdmac", atxdmac);
2095 dev_err(&pdev->dev, "can't request irq\n");
2099 ret = clk_prepare_enable(atxdmac->clk);
2101 dev_err(&pdev->dev, "can't prepare or enable clock\n");
2105 atxdmac->at_xdmac_desc_pool =
2106 dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
2107 sizeof(struct at_xdmac_desc), 4, 0);
2108 if (!atxdmac->at_xdmac_desc_pool) {
2109 dev_err(&pdev->dev, "no memory for descriptors dma pool\n");
2111 goto err_clk_disable;
2114 dma_cap_set(DMA_CYCLIC, atxdmac->dma.cap_mask);
2115 dma_cap_set(DMA_INTERLEAVE, atxdmac->dma.cap_mask);
2116 dma_cap_set(DMA_MEMCPY, atxdmac->dma.cap_mask);
2117 dma_cap_set(DMA_MEMSET, atxdmac->dma.cap_mask);
2118 dma_cap_set(DMA_MEMSET_SG, atxdmac->dma.cap_mask);
2119 dma_cap_set(DMA_SLAVE, atxdmac->dma.cap_mask);
2121 * Without DMA_PRIVATE the driver is not able to allocate more than
2122 * one channel, second allocation fails in private_candidate.
2124 dma_cap_set(DMA_PRIVATE, atxdmac->dma.cap_mask);
2125 atxdmac->dma.dev = &pdev->dev;
2126 atxdmac->dma.device_alloc_chan_resources = at_xdmac_alloc_chan_resources;
2127 atxdmac->dma.device_free_chan_resources = at_xdmac_free_chan_resources;
2128 atxdmac->dma.device_tx_status = at_xdmac_tx_status;
2129 atxdmac->dma.device_issue_pending = at_xdmac_issue_pending;
2130 atxdmac->dma.device_prep_dma_cyclic = at_xdmac_prep_dma_cyclic;
2131 atxdmac->dma.device_prep_interleaved_dma = at_xdmac_prep_interleaved;
2132 atxdmac->dma.device_prep_dma_memcpy = at_xdmac_prep_dma_memcpy;
2133 atxdmac->dma.device_prep_dma_memset = at_xdmac_prep_dma_memset;
2134 atxdmac->dma.device_prep_dma_memset_sg = at_xdmac_prep_dma_memset_sg;
2135 atxdmac->dma.device_prep_slave_sg = at_xdmac_prep_slave_sg;
2136 atxdmac->dma.device_config = at_xdmac_device_config;
2137 atxdmac->dma.device_pause = at_xdmac_device_pause;
2138 atxdmac->dma.device_resume = at_xdmac_device_resume;
2139 atxdmac->dma.device_terminate_all = at_xdmac_device_terminate_all;
2140 atxdmac->dma.src_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
2141 atxdmac->dma.dst_addr_widths = AT_XDMAC_DMA_BUSWIDTHS;
2142 atxdmac->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2143 atxdmac->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
2145 /* Disable all chans and interrupts. */
2146 at_xdmac_off(atxdmac);
2148 /* Init channels. */
2149 INIT_LIST_HEAD(&atxdmac->dma.channels);
2150 for (i = 0; i < nr_channels; i++) {
2151 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
2153 atchan->chan.device = &atxdmac->dma;
2154 list_add_tail(&atchan->chan.device_node,
2155 &atxdmac->dma.channels);
2157 atchan->ch_regs = at_xdmac_chan_reg_base(atxdmac, i);
2158 atchan->mask = 1 << i;
2160 spin_lock_init(&atchan->lock);
2161 INIT_LIST_HEAD(&atchan->xfers_list);
2162 INIT_LIST_HEAD(&atchan->free_descs_list);
2163 tasklet_setup(&atchan->tasklet, at_xdmac_tasklet);
2165 /* Clear pending interrupts. */
2166 while (at_xdmac_chan_read(atchan, AT_XDMAC_CIS))
2169 platform_set_drvdata(pdev, atxdmac);
2171 ret = dma_async_device_register(&atxdmac->dma);
2173 dev_err(&pdev->dev, "fail to register DMA engine device\n");
2174 goto err_clk_disable;
2177 ret = of_dma_controller_register(pdev->dev.of_node,
2178 at_xdmac_xlate, atxdmac);
2180 dev_err(&pdev->dev, "could not register of dma controller\n");
2181 goto err_dma_unregister;
2184 dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
2185 nr_channels, atxdmac->regs);
2187 at_xdmac_axi_config(pdev);
2192 dma_async_device_unregister(&atxdmac->dma);
2194 clk_disable_unprepare(atxdmac->clk);
2196 free_irq(atxdmac->irq, atxdmac);
2200 static int at_xdmac_remove(struct platform_device *pdev)
2202 struct at_xdmac *atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
2205 at_xdmac_off(atxdmac);
2206 of_dma_controller_free(pdev->dev.of_node);
2207 dma_async_device_unregister(&atxdmac->dma);
2208 clk_disable_unprepare(atxdmac->clk);
2210 free_irq(atxdmac->irq, atxdmac);
2212 for (i = 0; i < atxdmac->dma.chancnt; i++) {
2213 struct at_xdmac_chan *atchan = &atxdmac->chan[i];
2215 tasklet_kill(&atchan->tasklet);
2216 at_xdmac_free_chan_resources(&atchan->chan);
2222 static const struct dev_pm_ops atmel_xdmac_dev_pm_ops = {
2223 .prepare = atmel_xdmac_prepare,
2224 SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend, atmel_xdmac_resume)
2227 static const struct of_device_id atmel_xdmac_dt_ids[] = {
2229 .compatible = "atmel,sama5d4-dma",
2230 .data = &at_xdmac_sama5d4_layout,
2232 .compatible = "microchip,sama7g5-dma",
2233 .data = &at_xdmac_sama7g5_layout,
2238 MODULE_DEVICE_TABLE(of, atmel_xdmac_dt_ids);
2240 static struct platform_driver at_xdmac_driver = {
2241 .probe = at_xdmac_probe,
2242 .remove = at_xdmac_remove,
2245 .of_match_table = of_match_ptr(atmel_xdmac_dt_ids),
2246 .pm = &atmel_xdmac_dev_pm_ops,
2250 static int __init at_xdmac_init(void)
2252 return platform_driver_register(&at_xdmac_driver);
2254 subsys_initcall(at_xdmac_init);
2256 static void __exit at_xdmac_exit(void)
2258 platform_driver_unregister(&at_xdmac_driver);
2260 module_exit(at_xdmac_exit);
2262 MODULE_DESCRIPTION("Atmel Extended DMA Controller driver");
2263 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
2264 MODULE_LICENSE("GPL");