2 * A devfreq driver for NVIDIA Tegra SoCs
4 * Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved.
5 * Copyright (C) 2014 Google, Inc
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/clk.h>
22 #include <linux/cpufreq.h>
23 #include <linux/devfreq.h>
24 #include <linux/interrupt.h>
26 #include <linux/module.h>
27 #include <linux/mod_devicetable.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_opp.h>
30 #include <linux/reset.h>
34 #define ACTMON_GLB_STATUS 0x0
35 #define ACTMON_GLB_PERIOD_CTRL 0x4
37 #define ACTMON_DEV_CTRL 0x0
38 #define ACTMON_DEV_CTRL_K_VAL_SHIFT 10
39 #define ACTMON_DEV_CTRL_ENB_PERIODIC BIT(18)
40 #define ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN BIT(20)
41 #define ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN BIT(21)
42 #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT 23
43 #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT 26
44 #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN BIT(29)
45 #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN BIT(30)
46 #define ACTMON_DEV_CTRL_ENB BIT(31)
48 #define ACTMON_DEV_UPPER_WMARK 0x4
49 #define ACTMON_DEV_LOWER_WMARK 0x8
50 #define ACTMON_DEV_INIT_AVG 0xc
51 #define ACTMON_DEV_AVG_UPPER_WMARK 0x10
52 #define ACTMON_DEV_AVG_LOWER_WMARK 0x14
53 #define ACTMON_DEV_COUNT_WEIGHT 0x18
54 #define ACTMON_DEV_AVG_COUNT 0x20
55 #define ACTMON_DEV_INTR_STATUS 0x24
57 #define ACTMON_INTR_STATUS_CLEAR 0xffffffff
59 #define ACTMON_DEV_INTR_CONSECUTIVE_UPPER BIT(31)
60 #define ACTMON_DEV_INTR_CONSECUTIVE_LOWER BIT(30)
62 #define ACTMON_ABOVE_WMARK_WINDOW 1
63 #define ACTMON_BELOW_WMARK_WINDOW 3
64 #define ACTMON_BOOST_FREQ_STEP 16000
67 * Activity counter is incremented every 256 memory transactions, and each
68 * transaction takes 4 EMC clocks for Tegra124; So the COUNT_WEIGHT is
71 #define ACTMON_COUNT_WEIGHT 0x400
74 * ACTMON_AVERAGE_WINDOW_LOG2: default value for @DEV_CTRL_K_VAL, which
75 * translates to 2 ^ (K_VAL + 1). ex: 2 ^ (6 + 1) = 128
77 #define ACTMON_AVERAGE_WINDOW_LOG2 6
78 #define ACTMON_SAMPLING_PERIOD 12 /* ms */
79 #define ACTMON_DEFAULT_AVG_BAND 6 /* 1/10 of % */
83 #define KHZ_MAX (ULONG_MAX / KHZ)
85 /* Assume that the bus is saturated if the utilization is 25% */
86 #define BUS_SATURATION_RATIO 25
89 * struct tegra_devfreq_device_config - configuration specific to an ACTMON
92 * Coefficients and thresholds are percentages unless otherwise noted
94 struct tegra_devfreq_device_config {
98 /* Factors applied to boost_freq every consecutive watermark breach */
99 unsigned int boost_up_coeff;
100 unsigned int boost_down_coeff;
102 /* Define the watermark bounds when applied to the current avg */
103 unsigned int boost_up_threshold;
104 unsigned int boost_down_threshold;
107 * Threshold of activity (cycles) below which the CPU frequency isn't
108 * to be taken into account. This is to avoid increasing the EMC
109 * frequency when the CPU is very busy but not accessing the bus often.
111 u32 avg_dependency_threshold;
114 enum tegra_actmon_device {
119 static struct tegra_devfreq_device_config actmon_device_configs[] = {
121 /* MCALL: All memory accesses (including from the CPUs) */
124 .boost_up_coeff = 200,
125 .boost_down_coeff = 50,
126 .boost_up_threshold = 60,
127 .boost_down_threshold = 40,
130 /* MCCPU: memory accesses from the CPUs */
133 .boost_up_coeff = 800,
134 .boost_down_coeff = 90,
135 .boost_up_threshold = 27,
136 .boost_down_threshold = 10,
137 .avg_dependency_threshold = 50000,
142 * struct tegra_devfreq_device - state specific to an ACTMON device
144 * Frequencies are in kHz.
146 struct tegra_devfreq_device {
147 const struct tegra_devfreq_device_config *config;
151 /* Average event count sampled in the last interrupt */
155 * Extra frequency to increase the target by due to consecutive
156 * watermark breaches.
158 unsigned long boost_freq;
160 /* Optimal frequency calculated from the stats for this device */
161 unsigned long target_freq;
164 struct tegra_devfreq {
165 struct devfreq *devfreq;
167 struct reset_control *reset;
171 struct clk *emc_clock;
172 unsigned long max_freq;
173 unsigned long cur_freq;
174 struct notifier_block rate_change_nb;
176 struct tegra_devfreq_device devices[ARRAY_SIZE(actmon_device_configs)];
179 struct tegra_actmon_emc_ratio {
180 unsigned long cpu_freq;
181 unsigned long emc_freq;
184 static struct tegra_actmon_emc_ratio actmon_emc_ratios[] = {
185 { 1400000, KHZ_MAX },
194 static u32 actmon_readl(struct tegra_devfreq *tegra, u32 offset)
196 return readl(tegra->regs + offset);
199 static void actmon_writel(struct tegra_devfreq *tegra, u32 val, u32 offset)
201 writel(val, tegra->regs + offset);
204 static u32 device_readl(struct tegra_devfreq_device *dev, u32 offset)
206 return readl(dev->regs + offset);
209 static void device_writel(struct tegra_devfreq_device *dev, u32 val,
212 writel(val, dev->regs + offset);
215 static unsigned long do_percent(unsigned long val, unsigned int pct)
217 return val * pct / 100;
220 static void tegra_devfreq_update_avg_wmark(struct tegra_devfreq *tegra,
221 struct tegra_devfreq_device *dev)
223 u32 avg = dev->avg_count;
224 u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ;
225 u32 band = avg_band_freq * ACTMON_SAMPLING_PERIOD;
227 device_writel(dev, avg + band, ACTMON_DEV_AVG_UPPER_WMARK);
229 avg = max(dev->avg_count, band);
230 device_writel(dev, avg - band, ACTMON_DEV_AVG_LOWER_WMARK);
233 static void tegra_devfreq_update_wmark(struct tegra_devfreq *tegra,
234 struct tegra_devfreq_device *dev)
236 u32 val = tegra->cur_freq * ACTMON_SAMPLING_PERIOD;
238 device_writel(dev, do_percent(val, dev->config->boost_up_threshold),
239 ACTMON_DEV_UPPER_WMARK);
241 device_writel(dev, do_percent(val, dev->config->boost_down_threshold),
242 ACTMON_DEV_LOWER_WMARK);
245 static void actmon_write_barrier(struct tegra_devfreq *tegra)
247 /* ensure the update has reached the ACTMON */
249 actmon_readl(tegra, ACTMON_GLB_STATUS);
252 static void actmon_isr_device(struct tegra_devfreq *tegra,
253 struct tegra_devfreq_device *dev)
256 u32 intr_status, dev_ctrl;
258 spin_lock_irqsave(&dev->lock, flags);
260 dev->avg_count = device_readl(dev, ACTMON_DEV_AVG_COUNT);
261 tegra_devfreq_update_avg_wmark(tegra, dev);
263 intr_status = device_readl(dev, ACTMON_DEV_INTR_STATUS);
264 dev_ctrl = device_readl(dev, ACTMON_DEV_CTRL);
266 if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_UPPER) {
268 * new_boost = min(old_boost * up_coef + step, max_freq)
270 dev->boost_freq = do_percent(dev->boost_freq,
271 dev->config->boost_up_coeff);
272 dev->boost_freq += ACTMON_BOOST_FREQ_STEP;
274 dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
276 if (dev->boost_freq >= tegra->max_freq)
277 dev->boost_freq = tegra->max_freq;
279 dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
280 } else if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_LOWER) {
282 * new_boost = old_boost * down_coef
283 * or 0 if (old_boost * down_coef < step / 2)
285 dev->boost_freq = do_percent(dev->boost_freq,
286 dev->config->boost_down_coeff);
288 dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
290 if (dev->boost_freq < (ACTMON_BOOST_FREQ_STEP >> 1))
293 dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
296 if (dev->config->avg_dependency_threshold) {
297 if (dev->avg_count >= dev->config->avg_dependency_threshold)
298 dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
299 else if (dev->boost_freq == 0)
300 dev_ctrl &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
303 device_writel(dev, dev_ctrl, ACTMON_DEV_CTRL);
305 device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS);
307 actmon_write_barrier(tegra);
309 spin_unlock_irqrestore(&dev->lock, flags);
312 static irqreturn_t actmon_isr(int irq, void *data)
314 struct tegra_devfreq *tegra = data;
315 bool handled = false;
319 val = actmon_readl(tegra, ACTMON_GLB_STATUS);
320 for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
321 if (val & tegra->devices[i].config->irq_mask) {
322 actmon_isr_device(tegra, tegra->devices + i);
327 return handled ? IRQ_WAKE_THREAD : IRQ_NONE;
330 static unsigned long actmon_cpu_to_emc_rate(struct tegra_devfreq *tegra,
331 unsigned long cpu_freq)
334 struct tegra_actmon_emc_ratio *ratio = actmon_emc_ratios;
336 for (i = 0; i < ARRAY_SIZE(actmon_emc_ratios); i++, ratio++) {
337 if (cpu_freq >= ratio->cpu_freq) {
338 if (ratio->emc_freq >= tegra->max_freq)
339 return tegra->max_freq;
341 return ratio->emc_freq;
348 static void actmon_update_target(struct tegra_devfreq *tegra,
349 struct tegra_devfreq_device *dev)
351 unsigned long cpu_freq = 0;
352 unsigned long static_cpu_emc_freq = 0;
353 unsigned int avg_sustain_coef;
356 if (dev->config->avg_dependency_threshold) {
357 cpu_freq = cpufreq_get(0);
358 static_cpu_emc_freq = actmon_cpu_to_emc_rate(tegra, cpu_freq);
361 spin_lock_irqsave(&dev->lock, flags);
363 dev->target_freq = dev->avg_count / ACTMON_SAMPLING_PERIOD;
364 avg_sustain_coef = 100 * 100 / dev->config->boost_up_threshold;
365 dev->target_freq = do_percent(dev->target_freq, avg_sustain_coef);
366 dev->target_freq += dev->boost_freq;
368 if (dev->avg_count >= dev->config->avg_dependency_threshold)
369 dev->target_freq = max(dev->target_freq, static_cpu_emc_freq);
371 spin_unlock_irqrestore(&dev->lock, flags);
374 static irqreturn_t actmon_thread_isr(int irq, void *data)
376 struct tegra_devfreq *tegra = data;
378 mutex_lock(&tegra->devfreq->lock);
379 update_devfreq(tegra->devfreq);
380 mutex_unlock(&tegra->devfreq->lock);
385 static int tegra_actmon_rate_notify_cb(struct notifier_block *nb,
386 unsigned long action, void *ptr)
388 struct clk_notifier_data *data = ptr;
389 struct tegra_devfreq *tegra;
390 struct tegra_devfreq_device *dev;
394 if (action != POST_RATE_CHANGE)
397 tegra = container_of(nb, struct tegra_devfreq, rate_change_nb);
399 tegra->cur_freq = data->new_rate / KHZ;
401 for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
402 dev = &tegra->devices[i];
404 spin_lock_irqsave(&dev->lock, flags);
405 tegra_devfreq_update_wmark(tegra, dev);
406 spin_unlock_irqrestore(&dev->lock, flags);
409 actmon_write_barrier(tegra);
414 static void tegra_actmon_enable_interrupts(struct tegra_devfreq *tegra)
416 struct tegra_devfreq_device *dev;
420 for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
421 dev = &tegra->devices[i];
423 val = device_readl(dev, ACTMON_DEV_CTRL);
424 val |= ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN;
425 val |= ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN;
426 val |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
427 val |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
429 device_writel(dev, val, ACTMON_DEV_CTRL);
432 actmon_write_barrier(tegra);
435 static void tegra_actmon_disable_interrupts(struct tegra_devfreq *tegra)
437 struct tegra_devfreq_device *dev;
441 for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
442 dev = &tegra->devices[i];
444 val = device_readl(dev, ACTMON_DEV_CTRL);
445 val &= ~ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN;
446 val &= ~ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN;
447 val &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
448 val &= ~ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
450 device_writel(dev, val, ACTMON_DEV_CTRL);
453 actmon_write_barrier(tegra);
456 static void tegra_actmon_configure_device(struct tegra_devfreq *tegra,
457 struct tegra_devfreq_device *dev)
461 dev->target_freq = tegra->cur_freq;
463 dev->avg_count = tegra->cur_freq * ACTMON_SAMPLING_PERIOD;
464 device_writel(dev, dev->avg_count, ACTMON_DEV_INIT_AVG);
466 tegra_devfreq_update_avg_wmark(tegra, dev);
467 tegra_devfreq_update_wmark(tegra, dev);
469 device_writel(dev, ACTMON_COUNT_WEIGHT, ACTMON_DEV_COUNT_WEIGHT);
470 device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS);
472 val |= ACTMON_DEV_CTRL_ENB_PERIODIC;
473 val |= (ACTMON_AVERAGE_WINDOW_LOG2 - 1)
474 << ACTMON_DEV_CTRL_K_VAL_SHIFT;
475 val |= (ACTMON_BELOW_WMARK_WINDOW - 1)
476 << ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT;
477 val |= (ACTMON_ABOVE_WMARK_WINDOW - 1)
478 << ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT;
479 val |= ACTMON_DEV_CTRL_ENB;
481 device_writel(dev, val, ACTMON_DEV_CTRL);
483 actmon_write_barrier(tegra);
486 static int tegra_devfreq_target(struct device *dev, unsigned long *freq,
489 struct tegra_devfreq *tegra = dev_get_drvdata(dev);
490 struct dev_pm_opp *opp;
493 opp = devfreq_recommended_opp(dev, freq, flags);
495 dev_err(dev, "Failed to find opp for %lu Hz\n", *freq);
498 rate = dev_pm_opp_get_freq(opp);
501 clk_set_min_rate(tegra->emc_clock, rate);
502 clk_set_rate(tegra->emc_clock, 0);
507 static int tegra_devfreq_get_dev_status(struct device *dev,
508 struct devfreq_dev_status *stat)
510 struct tegra_devfreq *tegra = dev_get_drvdata(dev);
511 struct tegra_devfreq_device *actmon_dev;
513 stat->current_frequency = tegra->cur_freq * KHZ;
515 /* To be used by the tegra governor */
516 stat->private_data = tegra;
518 /* The below are to be used by the other governors */
520 actmon_dev = &tegra->devices[MCALL];
522 /* Number of cycles spent on memory access */
523 stat->busy_time = device_readl(actmon_dev, ACTMON_DEV_AVG_COUNT);
525 /* The bus can be considered to be saturated way before 100% */
526 stat->busy_time *= 100 / BUS_SATURATION_RATIO;
528 /* Number of cycles in a sampling period */
529 stat->total_time = ACTMON_SAMPLING_PERIOD * tegra->cur_freq;
531 stat->busy_time = min(stat->busy_time, stat->total_time);
536 static struct devfreq_dev_profile tegra_devfreq_profile = {
538 .target = tegra_devfreq_target,
539 .get_dev_status = tegra_devfreq_get_dev_status,
542 static int tegra_governor_get_target(struct devfreq *devfreq,
545 struct devfreq_dev_status *stat;
546 struct tegra_devfreq *tegra;
547 struct tegra_devfreq_device *dev;
548 unsigned long target_freq = 0;
552 err = devfreq_update_stats(devfreq);
556 stat = &devfreq->last_status;
558 tegra = stat->private_data;
560 for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
561 dev = &tegra->devices[i];
563 actmon_update_target(tegra, dev);
565 target_freq = max(target_freq, dev->target_freq);
568 *freq = target_freq * KHZ;
573 static int tegra_governor_event_handler(struct devfreq *devfreq,
574 unsigned int event, void *data)
576 struct tegra_devfreq *tegra;
579 tegra = dev_get_drvdata(devfreq->dev.parent);
582 case DEVFREQ_GOV_START:
583 devfreq_monitor_start(devfreq);
584 tegra_actmon_enable_interrupts(tegra);
587 case DEVFREQ_GOV_STOP:
588 tegra_actmon_disable_interrupts(tegra);
589 devfreq_monitor_stop(devfreq);
592 case DEVFREQ_GOV_SUSPEND:
593 tegra_actmon_disable_interrupts(tegra);
594 devfreq_monitor_suspend(devfreq);
597 case DEVFREQ_GOV_RESUME:
598 devfreq_monitor_resume(devfreq);
599 tegra_actmon_enable_interrupts(tegra);
606 static struct devfreq_governor tegra_devfreq_governor = {
607 .name = "tegra_actmon",
608 .get_target_freq = tegra_governor_get_target,
609 .event_handler = tegra_governor_event_handler,
612 static int tegra_devfreq_probe(struct platform_device *pdev)
614 struct tegra_devfreq *tegra;
615 struct tegra_devfreq_device *dev;
616 struct resource *res;
622 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
626 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
628 tegra->regs = devm_ioremap_resource(&pdev->dev, res);
629 if (IS_ERR(tegra->regs))
630 return PTR_ERR(tegra->regs);
632 tegra->reset = devm_reset_control_get(&pdev->dev, "actmon");
633 if (IS_ERR(tegra->reset)) {
634 dev_err(&pdev->dev, "Failed to get reset\n");
635 return PTR_ERR(tegra->reset);
638 tegra->clock = devm_clk_get(&pdev->dev, "actmon");
639 if (IS_ERR(tegra->clock)) {
640 dev_err(&pdev->dev, "Failed to get actmon clock\n");
641 return PTR_ERR(tegra->clock);
644 tegra->emc_clock = devm_clk_get(&pdev->dev, "emc");
645 if (IS_ERR(tegra->emc_clock)) {
646 dev_err(&pdev->dev, "Failed to get emc clock\n");
647 return PTR_ERR(tegra->emc_clock);
650 clk_set_rate(tegra->emc_clock, ULONG_MAX);
652 tegra->rate_change_nb.notifier_call = tegra_actmon_rate_notify_cb;
653 err = clk_notifier_register(tegra->emc_clock, &tegra->rate_change_nb);
656 "Failed to register rate change notifier\n");
660 reset_control_assert(tegra->reset);
662 err = clk_prepare_enable(tegra->clock);
665 "Failed to prepare and enable ACTMON clock\n");
669 reset_control_deassert(tegra->reset);
671 tegra->max_freq = clk_round_rate(tegra->emc_clock, ULONG_MAX) / KHZ;
672 tegra->cur_freq = clk_get_rate(tegra->emc_clock) / KHZ;
674 actmon_writel(tegra, ACTMON_SAMPLING_PERIOD - 1,
675 ACTMON_GLB_PERIOD_CTRL);
677 for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) {
678 dev = tegra->devices + i;
679 dev->config = actmon_device_configs + i;
680 dev->regs = tegra->regs + dev->config->offset;
681 spin_lock_init(&dev->lock);
683 tegra_actmon_configure_device(tegra, dev);
686 for (rate = 0; rate <= tegra->max_freq * KHZ; rate++) {
687 rate = clk_round_rate(tegra->emc_clock, rate);
688 dev_pm_opp_add(&pdev->dev, rate, 0);
691 irq = platform_get_irq(pdev, 0);
693 dev_err(&pdev->dev, "Failed to get IRQ: %d\n", irq);
697 platform_set_drvdata(pdev, tegra);
699 err = devm_request_threaded_irq(&pdev->dev, irq, actmon_isr,
700 actmon_thread_isr, IRQF_SHARED,
701 "tegra-devfreq", tegra);
703 dev_err(&pdev->dev, "Interrupt request failed\n");
707 tegra_devfreq_profile.initial_freq = clk_get_rate(tegra->emc_clock);
708 tegra->devfreq = devm_devfreq_add_device(&pdev->dev,
709 &tegra_devfreq_profile,
716 static int tegra_devfreq_remove(struct platform_device *pdev)
718 struct tegra_devfreq *tegra = platform_get_drvdata(pdev);
719 int irq = platform_get_irq(pdev, 0);
723 for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) {
724 val = device_readl(&tegra->devices[i], ACTMON_DEV_CTRL);
725 val &= ~ACTMON_DEV_CTRL_ENB;
726 device_writel(&tegra->devices[i], val, ACTMON_DEV_CTRL);
729 actmon_write_barrier(tegra);
731 devm_free_irq(&pdev->dev, irq, tegra);
733 clk_notifier_unregister(tegra->emc_clock, &tegra->rate_change_nb);
735 clk_disable_unprepare(tegra->clock);
740 static const struct of_device_id tegra_devfreq_of_match[] = {
741 { .compatible = "nvidia,tegra124-actmon" },
745 MODULE_DEVICE_TABLE(of, tegra_devfreq_of_match);
747 static struct platform_driver tegra_devfreq_driver = {
748 .probe = tegra_devfreq_probe,
749 .remove = tegra_devfreq_remove,
751 .name = "tegra-devfreq",
752 .of_match_table = tegra_devfreq_of_match,
756 static int __init tegra_devfreq_init(void)
760 ret = devfreq_add_governor(&tegra_devfreq_governor);
762 pr_err("%s: failed to add governor: %d\n", __func__, ret);
766 ret = platform_driver_register(&tegra_devfreq_driver);
768 devfreq_remove_governor(&tegra_devfreq_governor);
772 module_init(tegra_devfreq_init)
774 static void __exit tegra_devfreq_exit(void)
778 platform_driver_unregister(&tegra_devfreq_driver);
780 ret = devfreq_remove_governor(&tegra_devfreq_governor);
782 pr_err("%s: failed to remove governor: %d\n", __func__, ret);
784 module_exit(tegra_devfreq_exit)
786 MODULE_LICENSE("GPL v2");
787 MODULE_DESCRIPTION("Tegra devfreq driver");
788 MODULE_AUTHOR("Tomeu Vizoso <tomeu.vizoso@collabora.com>");