drivers/devfreq/tegra-devfreq.c

   1 /*
   2  * A devfreq driver for NVIDIA Tegra SoCs
   3  *
   4  * Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved.
   5  * Copyright (C) 2014 Google, Inc
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18  *
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/cpufreq.h>
  23 #include <linux/devfreq.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_opp.h>
  29 #include <linux/reset.h>
  30
  31 #include "governor.h"
  32
  33 #define ACTMON_GLB_STATUS                                       0x0
  34 #define ACTMON_GLB_PERIOD_CTRL                                  0x4
  35
  36 #define ACTMON_DEV_CTRL                                         0x0
  37 #define ACTMON_DEV_CTRL_K_VAL_SHIFT                             10
  38 #define ACTMON_DEV_CTRL_ENB_PERIODIC                            BIT(18)
  39 #define ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN                      BIT(20)
  40 #define ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN                      BIT(21)
  41 #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT       23
  42 #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT       26
  43 #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN              BIT(29)
  44 #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN              BIT(30)
  45 #define ACTMON_DEV_CTRL_ENB                                     BIT(31)
  46
  47 #define ACTMON_DEV_UPPER_WMARK                                  0x4
  48 #define ACTMON_DEV_LOWER_WMARK                                  0x8
  49 #define ACTMON_DEV_INIT_AVG                                     0xc
  50 #define ACTMON_DEV_AVG_UPPER_WMARK                              0x10
  51 #define ACTMON_DEV_AVG_LOWER_WMARK                              0x14
  52 #define ACTMON_DEV_COUNT_WEIGHT                                 0x18
  53 #define ACTMON_DEV_AVG_COUNT                                    0x20
  54 #define ACTMON_DEV_INTR_STATUS                                  0x24
  55
  56 #define ACTMON_INTR_STATUS_CLEAR                                0xffffffff
  57
  58 #define ACTMON_DEV_INTR_CONSECUTIVE_UPPER                       BIT(31)
  59 #define ACTMON_DEV_INTR_CONSECUTIVE_LOWER                       BIT(30)
  60
  61 #define ACTMON_ABOVE_WMARK_WINDOW                               1
  62 #define ACTMON_BELOW_WMARK_WINDOW                               3
  63 #define ACTMON_BOOST_FREQ_STEP                                  16000
  64
  65 /*
  66  * Activity counter is incremented every 256 memory transactions, and each
  67  * transaction takes 4 EMC clocks for Tegra124; So the COUNT_WEIGHT is
  68  * 4 * 256 = 1024.
  69  */
  70 #define ACTMON_COUNT_WEIGHT                                     0x400
  71
  72 /*
  73  * ACTMON_AVERAGE_WINDOW_LOG2: default value for @DEV_CTRL_K_VAL, which
  74  * translates to 2 ^ (K_VAL + 1). ex: 2 ^ (6 + 1) = 128
  75  */
  76 #define ACTMON_AVERAGE_WINDOW_LOG2                      6
  77 #define ACTMON_SAMPLING_PERIOD                          12 /* ms */
  78 #define ACTMON_DEFAULT_AVG_BAND                         6  /* 1/10 of % */
  79
  80 #define KHZ                                                     1000
  81
  82 #define KHZ_MAX                                         (ULONG_MAX / KHZ)
  83
  84 /* Assume that the bus is saturated if the utilization is 25% */
  85 #define BUS_SATURATION_RATIO                                    25
  86
  87 /**
  88  * struct tegra_devfreq_device_config - configuration specific to an ACTMON
  89  * device
  90  *
  91  * Coefficients and thresholds are percentages unless otherwise noted
  92  */
  93 struct tegra_devfreq_device_config {
  94         u32             offset;
  95         u32             irq_mask;
  96
  97         /* Factors applied to boost_freq every consecutive watermark breach */
  98         unsigned int    boost_up_coeff;
  99         unsigned int    boost_down_coeff;
 100
 101         /* Define the watermark bounds when applied to the current avg */
 102         unsigned int    boost_up_threshold;
 103         unsigned int    boost_down_threshold;
 104
 105         /*
 106          * Threshold of activity (cycles) below which the CPU frequency isn't
 107          * to be taken into account. This is to avoid increasing the EMC
 108          * frequency when the CPU is very busy but not accessing the bus often.
 109          */
 110         u32             avg_dependency_threshold;
 111 };
 112
 113 enum tegra_actmon_device {
 114         MCALL = 0,
 115         MCCPU,
 116 };
 117
 118 static struct tegra_devfreq_device_config actmon_device_configs[] = {
 119         {
 120                 /* MCALL: All memory accesses (including from the CPUs) */
 121                 .offset = 0x1c0,
 122                 .irq_mask = 1 << 26,
 123                 .boost_up_coeff = 200,
 124                 .boost_down_coeff = 50,
 125                 .boost_up_threshold = 60,
 126                 .boost_down_threshold = 40,
 127         },
 128         {
 129                 /* MCCPU: memory accesses from the CPUs */
 130                 .offset = 0x200,
 131                 .irq_mask = 1 << 25,
 132                 .boost_up_coeff = 800,
 133                 .boost_down_coeff = 90,
 134                 .boost_up_threshold = 27,
 135                 .boost_down_threshold = 10,
 136                 .avg_dependency_threshold = 50000,
 137         },
 138 };
 139
 140 /**
 141  * struct tegra_devfreq_device - state specific to an ACTMON device
 142  *
 143  * Frequencies are in kHz.
 144  */
 145 struct tegra_devfreq_device {
 146         const struct tegra_devfreq_device_config *config;
 147         void __iomem *regs;
 148         spinlock_t lock;
 149
 150         /* Average event count sampled in the last interrupt */
 151         u32 avg_count;
 152
 153         /*
 154          * Extra frequency to increase the target by due to consecutive
 155          * watermark breaches.
 156          */
 157         unsigned long boost_freq;
 158
 159         /* Optimal frequency calculated from the stats for this device */
 160         unsigned long target_freq;
 161 };
 162
 163 struct tegra_devfreq {
 164         struct devfreq          *devfreq;
 165
 166         struct reset_control    *reset;
 167         struct clk              *clock;
 168         void __iomem            *regs;
 169
 170         struct clk              *emc_clock;
 171         unsigned long           max_freq;
 172         unsigned long           cur_freq;
 173         struct notifier_block   rate_change_nb;
 174
 175         struct tegra_devfreq_device devices[ARRAY_SIZE(actmon_device_configs)];
 176 };
 177
 178 struct tegra_actmon_emc_ratio {
 179         unsigned long cpu_freq;
 180         unsigned long emc_freq;
 181 };
 182
 183 static struct tegra_actmon_emc_ratio actmon_emc_ratios[] = {
 184         { 1400000,    KHZ_MAX },
 185         { 1200000,    750000 },
 186         { 1100000,    600000 },
 187         { 1000000,    500000 },
 188         {  800000,    375000 },
 189         {  500000,    200000 },
 190         {  250000,    100000 },
 191 };
 192
 193 static u32 actmon_readl(struct tegra_devfreq *tegra, u32 offset)
 194 {
 195         return readl(tegra->regs + offset);
 196 }
 197
 198 static void actmon_writel(struct tegra_devfreq *tegra, u32 val, u32 offset)
 199 {
 200         writel(val, tegra->regs + offset);
 201 }
 202
 203 static u32 device_readl(struct tegra_devfreq_device *dev, u32 offset)
 204 {
 205         return readl(dev->regs + offset);
 206 }
 207
 208 static void device_writel(struct tegra_devfreq_device *dev, u32 val,
 209                           u32 offset)
 210 {
 211         writel(val, dev->regs + offset);
 212 }
 213
 214 static unsigned long do_percent(unsigned long val, unsigned int pct)
 215 {
 216         return val * pct / 100;
 217 }
 218
 219 static void tegra_devfreq_update_avg_wmark(struct tegra_devfreq *tegra,
 220                                            struct tegra_devfreq_device *dev)
 221 {
 222         u32 avg = dev->avg_count;
 223         u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ;
 224         u32 band = avg_band_freq * ACTMON_SAMPLING_PERIOD;
 225
 226         device_writel(dev, avg + band, ACTMON_DEV_AVG_UPPER_WMARK);
 227
 228         avg = max(dev->avg_count, band);
 229         device_writel(dev, avg - band, ACTMON_DEV_AVG_LOWER_WMARK);
 230 }
 231
 232 static void tegra_devfreq_update_wmark(struct tegra_devfreq *tegra,
 233                                        struct tegra_devfreq_device *dev)
 234 {
 235         u32 val = tegra->cur_freq * ACTMON_SAMPLING_PERIOD;
 236
 237         device_writel(dev, do_percent(val, dev->config->boost_up_threshold),
 238                       ACTMON_DEV_UPPER_WMARK);
 239
 240         device_writel(dev, do_percent(val, dev->config->boost_down_threshold),
 241                       ACTMON_DEV_LOWER_WMARK);
 242 }
 243
 244 static void actmon_write_barrier(struct tegra_devfreq *tegra)
 245 {
 246         /* ensure the update has reached the ACTMON */
 247         wmb();
 248         actmon_readl(tegra, ACTMON_GLB_STATUS);
 249 }
 250
 251 static void actmon_isr_device(struct tegra_devfreq *tegra,
 252                               struct tegra_devfreq_device *dev)
 253 {
 254         unsigned long flags;
 255         u32 intr_status, dev_ctrl;
 256
 257         spin_lock_irqsave(&dev->lock, flags);
 258
 259         dev->avg_count = device_readl(dev, ACTMON_DEV_AVG_COUNT);
 260         tegra_devfreq_update_avg_wmark(tegra, dev);
 261
 262         intr_status = device_readl(dev, ACTMON_DEV_INTR_STATUS);
 263         dev_ctrl = device_readl(dev, ACTMON_DEV_CTRL);
 264
 265         if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_UPPER) {
 266                 /*
 267                  * new_boost = min(old_boost * up_coef + step, max_freq)
 268                  */
 269                 dev->boost_freq = do_percent(dev->boost_freq,
 270                                              dev->config->boost_up_coeff);
 271                 dev->boost_freq += ACTMON_BOOST_FREQ_STEP;
 272
 273                 dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
 274
 275                 if (dev->boost_freq >= tegra->max_freq)
 276                         dev->boost_freq = tegra->max_freq;
 277                 else
 278                         dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
 279         } else if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_LOWER) {
 280                 /*
 281                  * new_boost = old_boost * down_coef
 282                  * or 0 if (old_boost * down_coef < step / 2)
 283                  */
 284                 dev->boost_freq = do_percent(dev->boost_freq,
 285                                              dev->config->boost_down_coeff);
 286
 287                 dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
 288
 289                 if (dev->boost_freq < (ACTMON_BOOST_FREQ_STEP >> 1))
 290                         dev->boost_freq = 0;
 291                 else
 292                         dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
 293         }
 294
 295         if (dev->config->avg_dependency_threshold) {
 296                 if (dev->avg_count >= dev->config->avg_dependency_threshold)
 297                         dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
 298                 else if (dev->boost_freq == 0)
 299                         dev_ctrl &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
 300         }
 301
 302         device_writel(dev, dev_ctrl, ACTMON_DEV_CTRL);
 303
 304         device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS);
 305
 306         actmon_write_barrier(tegra);
 307
 308         spin_unlock_irqrestore(&dev->lock, flags);
 309 }
 310
 311 static irqreturn_t actmon_isr(int irq, void *data)
 312 {
 313         struct tegra_devfreq *tegra = data;
 314         bool handled = false;
 315         unsigned int i;
 316         u32 val;
 317
 318         val = actmon_readl(tegra, ACTMON_GLB_STATUS);
 319         for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
 320                 if (val & tegra->devices[i].config->irq_mask) {
 321                         actmon_isr_device(tegra, tegra->devices + i);
 322                         handled = true;
 323                 }
 324         }
 325
 326         return handled ? IRQ_WAKE_THREAD : IRQ_NONE;
 327 }
 328
 329 static unsigned long actmon_cpu_to_emc_rate(struct tegra_devfreq *tegra,
 330                                             unsigned long cpu_freq)
 331 {
 332         unsigned int i;
 333         struct tegra_actmon_emc_ratio *ratio = actmon_emc_ratios;
 334
 335         for (i = 0; i < ARRAY_SIZE(actmon_emc_ratios); i++, ratio++) {
 336                 if (cpu_freq >= ratio->cpu_freq) {
 337                         if (ratio->emc_freq >= tegra->max_freq)
 338                                 return tegra->max_freq;
 339                         else
 340                                 return ratio->emc_freq;
 341                 }
 342         }
 343
 344         return 0;
 345 }
 346
 347 static void actmon_update_target(struct tegra_devfreq *tegra,
 348                                  struct tegra_devfreq_device *dev)
 349 {
 350         unsigned long cpu_freq = 0;
 351         unsigned long static_cpu_emc_freq = 0;
 352         unsigned int avg_sustain_coef;
 353         unsigned long flags;
 354
 355         if (dev->config->avg_dependency_threshold) {
 356                 cpu_freq = cpufreq_get(0);
 357                 static_cpu_emc_freq = actmon_cpu_to_emc_rate(tegra, cpu_freq);
 358         }
 359
 360         spin_lock_irqsave(&dev->lock, flags);
 361
 362         dev->target_freq = dev->avg_count / ACTMON_SAMPLING_PERIOD;
 363         avg_sustain_coef = 100 * 100 / dev->config->boost_up_threshold;
 364         dev->target_freq = do_percent(dev->target_freq, avg_sustain_coef);
 365         dev->target_freq += dev->boost_freq;
 366
 367         if (dev->avg_count >= dev->config->avg_dependency_threshold)
 368                 dev->target_freq = max(dev->target_freq, static_cpu_emc_freq);
 369
 370         spin_unlock_irqrestore(&dev->lock, flags);
 371 }
 372
 373 static irqreturn_t actmon_thread_isr(int irq, void *data)
 374 {
 375         struct tegra_devfreq *tegra = data;
 376
 377         mutex_lock(&tegra->devfreq->lock);
 378         update_devfreq(tegra->devfreq);
 379         mutex_unlock(&tegra->devfreq->lock);
 380
 381         return IRQ_HANDLED;
 382 }
 383
 384 static int tegra_actmon_rate_notify_cb(struct notifier_block *nb,
 385                                        unsigned long action, void *ptr)
 386 {
 387         struct clk_notifier_data *data = ptr;
 388         struct tegra_devfreq *tegra;
 389         struct tegra_devfreq_device *dev;
 390         unsigned int i;
 391         unsigned long flags;
 392
 393         if (action != POST_RATE_CHANGE)
 394                 return NOTIFY_OK;
 395
 396         tegra = container_of(nb, struct tegra_devfreq, rate_change_nb);
 397
 398         tegra->cur_freq = data->new_rate / KHZ;
 399
 400         for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
 401                 dev = &tegra->devices[i];
 402
 403                 spin_lock_irqsave(&dev->lock, flags);
 404                 tegra_devfreq_update_wmark(tegra, dev);
 405                 spin_unlock_irqrestore(&dev->lock, flags);
 406         }
 407
 408         actmon_write_barrier(tegra);
 409
 410         return NOTIFY_OK;
 411 }
 412
 413 static void tegra_actmon_enable_interrupts(struct tegra_devfreq *tegra)
 414 {
 415         struct tegra_devfreq_device *dev;
 416         u32 val;
 417         unsigned int i;
 418
 419         for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
 420                 dev = &tegra->devices[i];
 421
 422                 val = device_readl(dev, ACTMON_DEV_CTRL);
 423                 val |= ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN;
 424                 val |= ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN;
 425                 val |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
 426                 val |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
 427
 428                 device_writel(dev, val, ACTMON_DEV_CTRL);
 429         }
 430
 431         actmon_write_barrier(tegra);
 432 }
 433
 434 static void tegra_actmon_disable_interrupts(struct tegra_devfreq *tegra)
 435 {
 436         struct tegra_devfreq_device *dev;
 437         u32 val;
 438         unsigned int i;
 439
 440         for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
 441                 dev = &tegra->devices[i];
 442
 443                 val = device_readl(dev, ACTMON_DEV_CTRL);
 444                 val &= ~ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN;
 445                 val &= ~ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN;
 446                 val &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
 447                 val &= ~ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
 448
 449                 device_writel(dev, val, ACTMON_DEV_CTRL);
 450         }
 451
 452         actmon_write_barrier(tegra);
 453 }
 454
 455 static void tegra_actmon_configure_device(struct tegra_devfreq *tegra,
 456                                           struct tegra_devfreq_device *dev)
 457 {
 458         u32 val = 0;
 459
 460         dev->target_freq = tegra->cur_freq;
 461
 462         dev->avg_count = tegra->cur_freq * ACTMON_SAMPLING_PERIOD;
 463         device_writel(dev, dev->avg_count, ACTMON_DEV_INIT_AVG);
 464
 465         tegra_devfreq_update_avg_wmark(tegra, dev);
 466         tegra_devfreq_update_wmark(tegra, dev);
 467
 468         device_writel(dev, ACTMON_COUNT_WEIGHT, ACTMON_DEV_COUNT_WEIGHT);
 469         device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS);
 470
 471         val |= ACTMON_DEV_CTRL_ENB_PERIODIC;
 472         val |= (ACTMON_AVERAGE_WINDOW_LOG2 - 1)
 473                 << ACTMON_DEV_CTRL_K_VAL_SHIFT;
 474         val |= (ACTMON_BELOW_WMARK_WINDOW - 1)
 475                 << ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT;
 476         val |= (ACTMON_ABOVE_WMARK_WINDOW - 1)
 477                 << ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT;
 478         val |= ACTMON_DEV_CTRL_ENB;
 479
 480         device_writel(dev, val, ACTMON_DEV_CTRL);
 481
 482         actmon_write_barrier(tegra);
 483 }
 484
 485 static int tegra_devfreq_target(struct device *dev, unsigned long *freq,
 486                                 u32 flags)
 487 {
 488         struct tegra_devfreq *tegra = dev_get_drvdata(dev);
 489         struct dev_pm_opp *opp;
 490         unsigned long rate = *freq * KHZ;
 491
 492         rcu_read_lock();
 493         opp = devfreq_recommended_opp(dev, &rate, flags);
 494         if (IS_ERR(opp)) {
 495                 rcu_read_unlock();
 496                 dev_err(dev, "Failed to find opp for %lu KHz\n", *freq);
 497                 return PTR_ERR(opp);
 498         }
 499         rate = dev_pm_opp_get_freq(opp);
 500         rcu_read_unlock();
 501
 502         clk_set_min_rate(tegra->emc_clock, rate);
 503         clk_set_rate(tegra->emc_clock, 0);
 504
 505         return 0;
 506 }
 507
 508 static int tegra_devfreq_get_dev_status(struct device *dev,
 509                                         struct devfreq_dev_status *stat)
 510 {
 511         struct tegra_devfreq *tegra = dev_get_drvdata(dev);
 512         struct tegra_devfreq_device *actmon_dev;
 513
 514         stat->current_frequency = tegra->cur_freq;
 515
 516         /* To be used by the tegra governor */
 517         stat->private_data = tegra;
 518
 519         /* The below are to be used by the other governors */
 520
 521         actmon_dev = &tegra->devices[MCALL];
 522
 523         /* Number of cycles spent on memory access */
 524         stat->busy_time = device_readl(actmon_dev, ACTMON_DEV_AVG_COUNT);
 525
 526         /* The bus can be considered to be saturated way before 100% */
 527         stat->busy_time *= 100 / BUS_SATURATION_RATIO;
 528
 529         /* Number of cycles in a sampling period */
 530         stat->total_time = ACTMON_SAMPLING_PERIOD * tegra->cur_freq;
 531
 532         stat->busy_time = min(stat->busy_time, stat->total_time);
 533
 534         return 0;
 535 }
 536
 537 static struct devfreq_dev_profile tegra_devfreq_profile = {
 538         .polling_ms     = 0,
 539         .target         = tegra_devfreq_target,
 540         .get_dev_status = tegra_devfreq_get_dev_status,
 541 };
 542
 543 static int tegra_governor_get_target(struct devfreq *devfreq,
 544                                      unsigned long *freq)
 545 {
 546         struct devfreq_dev_status *stat;
 547         struct tegra_devfreq *tegra;
 548         struct tegra_devfreq_device *dev;
 549         unsigned long target_freq = 0;
 550         unsigned int i;
 551         int err;
 552
 553         err = devfreq_update_stats(devfreq);
 554         if (err)
 555                 return err;
 556
 557         stat = &devfreq->last_status;
 558
 559         tegra = stat->private_data;
 560
 561         for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
 562                 dev = &tegra->devices[i];
 563
 564                 actmon_update_target(tegra, dev);
 565
 566                 target_freq = max(target_freq, dev->target_freq);
 567         }
 568
 569         *freq = target_freq;
 570
 571         return 0;
 572 }
 573
 574 static int tegra_governor_event_handler(struct devfreq *devfreq,
 575                                         unsigned int event, void *data)
 576 {
 577         struct tegra_devfreq *tegra;
 578         int ret = 0;
 579
 580         tegra = dev_get_drvdata(devfreq->dev.parent);
 581
 582         switch (event) {
 583         case DEVFREQ_GOV_START:
 584                 devfreq_monitor_start(devfreq);
 585                 tegra_actmon_enable_interrupts(tegra);
 586                 break;
 587
 588         case DEVFREQ_GOV_STOP:
 589                 tegra_actmon_disable_interrupts(tegra);
 590                 devfreq_monitor_stop(devfreq);
 591                 break;
 592
 593         case DEVFREQ_GOV_SUSPEND:
 594                 tegra_actmon_disable_interrupts(tegra);
 595                 devfreq_monitor_suspend(devfreq);
 596                 break;
 597
 598         case DEVFREQ_GOV_RESUME:
 599                 devfreq_monitor_resume(devfreq);
 600                 tegra_actmon_enable_interrupts(tegra);
 601                 break;
 602         }
 603
 604         return ret;
 605 }
 606
 607 static struct devfreq_governor tegra_devfreq_governor = {
 608         .name = "tegra_actmon",
 609         .get_target_freq = tegra_governor_get_target,
 610         .event_handler = tegra_governor_event_handler,
 611 };
 612
 613 static int tegra_devfreq_probe(struct platform_device *pdev)
 614 {
 615         struct tegra_devfreq *tegra;
 616         struct tegra_devfreq_device *dev;
 617         struct resource *res;
 618         unsigned int i;
 619         unsigned long rate;
 620         int irq;
 621         int err;
 622
 623         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
 624         if (!tegra)
 625                 return -ENOMEM;
 626
 627         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 628
 629         tegra->regs = devm_ioremap_resource(&pdev->dev, res);
 630         if (IS_ERR(tegra->regs))
 631                 return PTR_ERR(tegra->regs);
 632
 633         tegra->reset = devm_reset_control_get(&pdev->dev, "actmon");
 634         if (IS_ERR(tegra->reset)) {
 635                 dev_err(&pdev->dev, "Failed to get reset\n");
 636                 return PTR_ERR(tegra->reset);
 637         }
 638
 639         tegra->clock = devm_clk_get(&pdev->dev, "actmon");
 640         if (IS_ERR(tegra->clock)) {
 641                 dev_err(&pdev->dev, "Failed to get actmon clock\n");
 642                 return PTR_ERR(tegra->clock);
 643         }
 644
 645         tegra->emc_clock = devm_clk_get(&pdev->dev, "emc");
 646         if (IS_ERR(tegra->emc_clock)) {
 647                 dev_err(&pdev->dev, "Failed to get emc clock\n");
 648                 return PTR_ERR(tegra->emc_clock);
 649         }
 650
 651         clk_set_rate(tegra->emc_clock, ULONG_MAX);
 652
 653         tegra->rate_change_nb.notifier_call = tegra_actmon_rate_notify_cb;
 654         err = clk_notifier_register(tegra->emc_clock, &tegra->rate_change_nb);
 655         if (err) {
 656                 dev_err(&pdev->dev,
 657                         "Failed to register rate change notifier\n");
 658                 return err;
 659         }
 660
 661         reset_control_assert(tegra->reset);
 662
 663         err = clk_prepare_enable(tegra->clock);
 664         if (err) {
 665                 dev_err(&pdev->dev,
 666                         "Failed to prepare and enable ACTMON clock\n");
 667                 return err;
 668         }
 669
 670         reset_control_deassert(tegra->reset);
 671
 672         tegra->max_freq = clk_round_rate(tegra->emc_clock, ULONG_MAX) / KHZ;
 673         tegra->cur_freq = clk_get_rate(tegra->emc_clock) / KHZ;
 674
 675         actmon_writel(tegra, ACTMON_SAMPLING_PERIOD - 1,
 676                       ACTMON_GLB_PERIOD_CTRL);
 677
 678         for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) {
 679                 dev = tegra->devices + i;
 680                 dev->config = actmon_device_configs + i;
 681                 dev->regs = tegra->regs + dev->config->offset;
 682                 spin_lock_init(&dev->lock);
 683
 684                 tegra_actmon_configure_device(tegra, dev);
 685         }
 686
 687         for (rate = 0; rate <= tegra->max_freq * KHZ; rate++) {
 688                 rate = clk_round_rate(tegra->emc_clock, rate);
 689                 dev_pm_opp_add(&pdev->dev, rate, 0);
 690         }
 691
 692         irq = platform_get_irq(pdev, 0);
 693         if (irq < 0) {
 694                 dev_err(&pdev->dev, "Failed to get IRQ: %d\n", irq);
 695                 return irq;
 696         }
 697
 698         platform_set_drvdata(pdev, tegra);
 699
 700         err = devm_request_threaded_irq(&pdev->dev, irq, actmon_isr,
 701                                         actmon_thread_isr, IRQF_SHARED,
 702                                         "tegra-devfreq", tegra);
 703         if (err) {
 704                 dev_err(&pdev->dev, "Interrupt request failed\n");
 705                 return err;
 706         }
 707
 708         tegra_devfreq_profile.initial_freq = clk_get_rate(tegra->emc_clock);
 709         tegra->devfreq = devm_devfreq_add_device(&pdev->dev,
 710                                                  &tegra_devfreq_profile,
 711                                                  "tegra_actmon",
 712                                                  NULL);
 713
 714         return 0;
 715 }
 716
 717 static int tegra_devfreq_remove(struct platform_device *pdev)
 718 {
 719         struct tegra_devfreq *tegra = platform_get_drvdata(pdev);
 720         int irq = platform_get_irq(pdev, 0);
 721         u32 val;
 722         unsigned int i;
 723
 724         for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) {
 725                 val = device_readl(&tegra->devices[i], ACTMON_DEV_CTRL);
 726                 val &= ~ACTMON_DEV_CTRL_ENB;
 727                 device_writel(&tegra->devices[i], val, ACTMON_DEV_CTRL);
 728         }
 729
 730         actmon_write_barrier(tegra);
 731
 732         devm_free_irq(&pdev->dev, irq, tegra);
 733
 734         clk_notifier_unregister(tegra->emc_clock, &tegra->rate_change_nb);
 735
 736         clk_disable_unprepare(tegra->clock);
 737
 738         return 0;
 739 }
 740
 741 static const struct of_device_id tegra_devfreq_of_match[] = {
 742         { .compatible = "nvidia,tegra124-actmon" },
 743         { },
 744 };
 745
 746 MODULE_DEVICE_TABLE(of, tegra_devfreq_of_match);
 747
 748 static struct platform_driver tegra_devfreq_driver = {
 749         .probe  = tegra_devfreq_probe,
 750         .remove = tegra_devfreq_remove,
 751         .driver = {
 752                 .name = "tegra-devfreq",
 753                 .of_match_table = tegra_devfreq_of_match,
 754         },
 755 };
 756
 757 static int __init tegra_devfreq_init(void)
 758 {
 759         int ret = 0;
 760
 761         ret = devfreq_add_governor(&tegra_devfreq_governor);
 762         if (ret) {
 763                 pr_err("%s: failed to add governor: %d\n", __func__, ret);
 764                 return ret;
 765         }
 766
 767         ret = platform_driver_register(&tegra_devfreq_driver);
 768         if (ret)
 769                 devfreq_remove_governor(&tegra_devfreq_governor);
 770
 771         return ret;
 772 }
 773 module_init(tegra_devfreq_init)
 774
 775 static void __exit tegra_devfreq_exit(void)
 776 {
 777         int ret = 0;
 778
 779         platform_driver_unregister(&tegra_devfreq_driver);
 780
 781         ret = devfreq_remove_governor(&tegra_devfreq_governor);
 782         if (ret)
 783                 pr_err("%s: failed to remove governor: %d\n", __func__, ret);
 784 }
 785 module_exit(tegra_devfreq_exit)
 786
 787 MODULE_LICENSE("GPL v2");
 788 MODULE_DESCRIPTION("Tegra devfreq driver");
 789 MODULE_AUTHOR("Tomeu Vizoso <tomeu.vizoso@collabora.com>");