GNU Linux-libre 4.19.314-gnu1
[releases.git] / drivers / devfreq / event / exynos-ppmu.h
1 /*
2  * exynos_ppmu.h - EXYNOS PPMU header file
3  *
4  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
5  * Author : Chanwoo Choi <cw00.choi@samsung.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #ifndef __EXYNOS_PPMU_H__
13 #define __EXYNOS_PPMU_H__
14
15 enum ppmu_state {
16         PPMU_DISABLE = 0,
17         PPMU_ENABLE,
18 };
19
20 enum ppmu_counter {
21         PPMU_PMNCNT0 = 0,
22         PPMU_PMNCNT1,
23         PPMU_PMNCNT2,
24         PPMU_PMNCNT3,
25
26         PPMU_PMNCNT_MAX,
27 };
28
29 /***
30  * PPMUv1.1 Definitions
31  */
32 enum ppmu_event_type {
33         PPMU_RO_BUSY_CYCLE_CNT  = 0x0,
34         PPMU_WO_BUSY_CYCLE_CNT  = 0x1,
35         PPMU_RW_BUSY_CYCLE_CNT  = 0x2,
36         PPMU_RO_REQUEST_CNT     = 0x3,
37         PPMU_WO_REQUEST_CNT     = 0x4,
38         PPMU_RO_DATA_CNT        = 0x5,
39         PPMU_WO_DATA_CNT        = 0x6,
40         PPMU_RO_LATENCY         = 0x12,
41         PPMU_WO_LATENCY         = 0x16,
42 };
43
44 enum ppmu_reg {
45         /* PPC control register */
46         PPMU_PMNC               = 0x00,
47         PPMU_CNTENS             = 0x10,
48         PPMU_CNTENC             = 0x20,
49         PPMU_INTENS             = 0x30,
50         PPMU_INTENC             = 0x40,
51         PPMU_FLAG               = 0x50,
52
53         /* Cycle Counter and Performance Event Counter Register */
54         PPMU_CCNT               = 0x100,
55         PPMU_PMCNT0             = 0x110,
56         PPMU_PMCNT1             = 0x120,
57         PPMU_PMCNT2             = 0x130,
58         PPMU_PMCNT3_HIGH        = 0x140,
59         PPMU_PMCNT3_LOW         = 0x150,
60
61         /* Bus Event Generator */
62         PPMU_BEVT0SEL           = 0x1000,
63         PPMU_BEVT1SEL           = 0x1100,
64         PPMU_BEVT2SEL           = 0x1200,
65         PPMU_BEVT3SEL           = 0x1300,
66         PPMU_COUNTER_RESET      = 0x1810,
67         PPMU_READ_OVERFLOW_CNT  = 0x1810,
68         PPMU_READ_UNDERFLOW_CNT = 0x1814,
69         PPMU_WRITE_OVERFLOW_CNT = 0x1850,
70         PPMU_WRITE_UNDERFLOW_CNT = 0x1854,
71         PPMU_READ_PENDING_CNT   = 0x1880,
72         PPMU_WRITE_PENDING_CNT  = 0x1884
73 };
74
75 /* PMNC register */
76 #define PPMU_PMNC_CC_RESET_SHIFT        2
77 #define PPMU_PMNC_COUNTER_RESET_SHIFT   1
78 #define PPMU_PMNC_ENABLE_SHIFT          0
79 #define PPMU_PMNC_START_MODE_MASK       BIT(16)
80 #define PPMU_PMNC_CC_DIVIDER_MASK       BIT(3)
81 #define PPMU_PMNC_CC_RESET_MASK         BIT(2)
82 #define PPMU_PMNC_COUNTER_RESET_MASK    BIT(1)
83 #define PPMU_PMNC_ENABLE_MASK           BIT(0)
84
85 /* CNTENS/CNTENC/INTENS/INTENC/FLAG register */
86 #define PPMU_CCNT_MASK                  BIT(31)
87 #define PPMU_PMCNT3_MASK                BIT(3)
88 #define PPMU_PMCNT2_MASK                BIT(2)
89 #define PPMU_PMCNT1_MASK                BIT(1)
90 #define PPMU_PMCNT0_MASK                BIT(0)
91
92 /* PPMU_PMNCTx/PPMU_BETxSEL registers */
93 #define PPMU_PMNCT(x)                   (PPMU_PMCNT0 + (0x10 * x))
94 #define PPMU_BEVTxSEL(x)                (PPMU_BEVT0SEL + (0x100 * x))
95
96 /***
97  * PPMU_V2.0 definitions
98  */
99 enum ppmu_v2_mode {
100         PPMU_V2_MODE_MANUAL = 0,
101         PPMU_V2_MODE_AUTO = 1,
102         PPMU_V2_MODE_CIG = 2,   /* CIG (Conditional Interrupt Generation) */
103 };
104
105 enum ppmu_v2_event_type {
106         PPMU_V2_RO_DATA_CNT     = 0x4,
107         PPMU_V2_WO_DATA_CNT     = 0x5,
108
109         PPMU_V2_EVT3_RW_DATA_CNT = 0x22,        /* Only for Event3 */
110 };
111
112 enum ppmu_V2_reg {
113         /* PPC control register */
114         PPMU_V2_PMNC            = 0x04,
115         PPMU_V2_CNTENS          = 0x08,
116         PPMU_V2_CNTENC          = 0x0c,
117         PPMU_V2_INTENS          = 0x10,
118         PPMU_V2_INTENC          = 0x14,
119         PPMU_V2_FLAG            = 0x18,
120
121         /* Cycle Counter and Performance Event Counter Register */
122         PPMU_V2_CCNT            = 0x48,
123         PPMU_V2_PMCNT0          = 0x34,
124         PPMU_V2_PMCNT1          = 0x38,
125         PPMU_V2_PMCNT2          = 0x3c,
126         PPMU_V2_PMCNT3_LOW      = 0x40,
127         PPMU_V2_PMCNT3_HIGH     = 0x44,
128
129         /* Bus Event Generator */
130         PPMU_V2_CIG_CFG0                = 0x1c,
131         PPMU_V2_CIG_CFG1                = 0x20,
132         PPMU_V2_CIG_CFG2                = 0x24,
133         PPMU_V2_CIG_RESULT      = 0x28,
134         PPMU_V2_CNT_RESET       = 0x2c,
135         PPMU_V2_CNT_AUTO                = 0x30,
136         PPMU_V2_CH_EV0_TYPE     = 0x200,
137         PPMU_V2_CH_EV1_TYPE     = 0x204,
138         PPMU_V2_CH_EV2_TYPE     = 0x208,
139         PPMU_V2_CH_EV3_TYPE     = 0x20c,
140         PPMU_V2_SM_ID_V         = 0x220,
141         PPMU_V2_SM_ID_A         = 0x224,
142         PPMU_V2_SM_OTHERS_V     = 0x228,
143         PPMU_V2_SM_OTHERS_A     = 0x22c,
144         PPMU_V2_INTERRUPT_RESET = 0x260,
145 };
146
147 /* PMNC register */
148 #define PPMU_V2_PMNC_START_MODE_SHIFT   20
149 #define PPMU_V2_PMNC_START_MODE_MASK    (0x3 << PPMU_V2_PMNC_START_MODE_SHIFT)
150
151 #define PPMU_PMNC_CC_RESET_SHIFT        2
152 #define PPMU_PMNC_COUNTER_RESET_SHIFT   1
153 #define PPMU_PMNC_ENABLE_SHIFT          0
154 #define PPMU_PMNC_START_MODE_MASK       BIT(16)
155 #define PPMU_PMNC_CC_DIVIDER_MASK       BIT(3)
156 #define PPMU_PMNC_CC_RESET_MASK         BIT(2)
157 #define PPMU_PMNC_COUNTER_RESET_MASK    BIT(1)
158 #define PPMU_PMNC_ENABLE_MASK           BIT(0)
159
160 #define PPMU_V2_PMNCT(x)                (PPMU_V2_PMCNT0 + (0x4 * x))
161 #define PPMU_V2_CH_EVx_TYPE(x)          (PPMU_V2_CH_EV0_TYPE + (0x4 * x))
162
163 #endif /* __EXYNOS_PPMU_H__ */