1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright(c) 2022 Intel Corporation. All rights reserved. */
3 #include <linux/device.h>
4 #include <linux/module.h>
5 #include <linux/slab.h>
13 * The port driver enumerates dport via PCI and scans for HDM
14 * (Host-managed-Device-Memory) decoder resources via the
15 * @component_reg_phys value passed in by the agent that registered the
16 * port. All descendant ports of a CXL root port (described by platform
17 * firmware) are managed in this drivers context. Each driver instance
18 * is responsible for tearing down the driver context of immediate
19 * descendant ports. The locking for this is validated by
20 * CONFIG_PROVE_CXL_LOCKING.
22 * The primary service this driver provides is presenting APIs to other
23 * drivers to utilize the decoders, and indicating to userspace (via bind
24 * status) the connectivity of the CXL.mem protocol throughout the
28 static void schedule_detach(void *cxlmd)
30 schedule_cxl_memdev_detach(cxlmd);
33 static int cxl_port_probe(struct device *dev)
35 struct cxl_port *port = to_cxl_port(dev);
36 struct cxl_hdm *cxlhdm;
40 if (!is_cxl_endpoint(port)) {
41 rc = devm_cxl_port_enumerate_dports(port);
45 return devm_cxl_add_passthrough_decoder(port);
48 cxlhdm = devm_cxl_setup_hdm(port);
50 return PTR_ERR(cxlhdm);
52 if (is_cxl_endpoint(port)) {
53 struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport);
54 struct cxl_dev_state *cxlds = cxlmd->cxlds;
56 /* Cache the data early to ensure is_visible() works */
59 get_device(&cxlmd->dev);
60 rc = devm_add_action_or_reset(dev, schedule_detach, cxlmd);
64 rc = cxl_hdm_decode_init(cxlds, cxlhdm);
68 rc = cxl_await_media_ready(cxlds);
70 dev_err(dev, "Media not active (%d)\n", rc);
75 rc = devm_cxl_enumerate_decoders(cxlhdm);
77 dev_err(dev, "Couldn't enumerate decoders (%d)\n", rc);
84 static ssize_t CDAT_read(struct file *filp, struct kobject *kobj,
85 struct bin_attribute *bin_attr, char *buf,
86 loff_t offset, size_t count)
88 struct device *dev = kobj_to_dev(kobj);
89 struct cxl_port *port = to_cxl_port(dev);
91 if (!port->cdat_available)
94 if (!port->cdat.table)
97 return memory_read_from_buffer(buf, count, &offset,
102 static BIN_ATTR_ADMIN_RO(CDAT, 0);
104 static umode_t cxl_port_bin_attr_is_visible(struct kobject *kobj,
105 struct bin_attribute *attr, int i)
107 struct device *dev = kobj_to_dev(kobj);
108 struct cxl_port *port = to_cxl_port(dev);
110 if ((attr == &bin_attr_CDAT) && port->cdat_available)
111 return attr->attr.mode;
116 static struct bin_attribute *cxl_cdat_bin_attributes[] = {
121 static struct attribute_group cxl_cdat_attribute_group = {
122 .bin_attrs = cxl_cdat_bin_attributes,
123 .is_bin_visible = cxl_port_bin_attr_is_visible,
126 static const struct attribute_group *cxl_port_attribute_groups[] = {
127 &cxl_cdat_attribute_group,
131 static struct cxl_driver cxl_port_driver = {
133 .probe = cxl_port_probe,
134 .id = CXL_DEVICE_PORT,
136 .dev_groups = cxl_port_attribute_groups,
140 module_cxl_driver(cxl_port_driver);
141 MODULE_LICENSE("GPL v2");
142 MODULE_IMPORT_NS(CXL);
143 MODULE_ALIAS_CXL(CXL_DEVICE_PORT);