1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx ZynqMP SHA Driver.
4 * Copyright (c) 2022 Xilinx Inc.
6 #include <linux/cacheflush.h>
7 #include <crypto/hash.h>
8 #include <crypto/internal/hash.h>
9 #include <crypto/sha3.h>
10 #include <linux/crypto.h>
11 #include <linux/device.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/firmware/xlnx-zynqmp.h>
14 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
21 #define ZYNQMP_DMA_BIT_MASK 32U
22 #define ZYNQMP_DMA_ALLOC_FIXED_SIZE 0x1000U
26 ZYNQMP_SHA3_UPDATE = 2,
27 ZYNQMP_SHA3_FINAL = 4,
30 struct zynqmp_sha_drv_ctx {
31 struct shash_alg sha3_384;
35 struct zynqmp_sha_tfm_ctx {
37 struct crypto_shash *fbk_tfm;
40 struct zynqmp_sha_desc_ctx {
41 struct shash_desc fbk_req;
44 static dma_addr_t update_dma_addr, final_dma_addr;
45 static char *ubuf, *fbuf;
47 static int zynqmp_sha_init_tfm(struct crypto_shash *hash)
49 const char *fallback_driver_name = crypto_shash_alg_name(hash);
50 struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
51 struct shash_alg *alg = crypto_shash_alg(hash);
52 struct crypto_shash *fallback_tfm;
53 struct zynqmp_sha_drv_ctx *drv_ctx;
55 drv_ctx = container_of(alg, struct zynqmp_sha_drv_ctx, sha3_384);
56 tfm_ctx->dev = drv_ctx->dev;
58 /* Allocate a fallback and abort if it failed. */
59 fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
60 CRYPTO_ALG_NEED_FALLBACK);
61 if (IS_ERR(fallback_tfm))
62 return PTR_ERR(fallback_tfm);
64 tfm_ctx->fbk_tfm = fallback_tfm;
65 hash->descsize += crypto_shash_descsize(tfm_ctx->fbk_tfm);
70 static void zynqmp_sha_exit_tfm(struct crypto_shash *hash)
72 struct zynqmp_sha_tfm_ctx *tfm_ctx = crypto_shash_ctx(hash);
74 if (tfm_ctx->fbk_tfm) {
75 crypto_free_shash(tfm_ctx->fbk_tfm);
76 tfm_ctx->fbk_tfm = NULL;
79 memzero_explicit(tfm_ctx, sizeof(struct zynqmp_sha_tfm_ctx));
82 static int zynqmp_sha_init(struct shash_desc *desc)
84 struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
85 struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
87 dctx->fbk_req.tfm = tctx->fbk_tfm;
88 return crypto_shash_init(&dctx->fbk_req);
91 static int zynqmp_sha_update(struct shash_desc *desc, const u8 *data, unsigned int length)
93 struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
95 return crypto_shash_update(&dctx->fbk_req, data, length);
98 static int zynqmp_sha_final(struct shash_desc *desc, u8 *out)
100 struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
102 return crypto_shash_final(&dctx->fbk_req, out);
105 static int zynqmp_sha_finup(struct shash_desc *desc, const u8 *data, unsigned int length, u8 *out)
107 struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
109 return crypto_shash_finup(&dctx->fbk_req, data, length, out);
112 static int zynqmp_sha_import(struct shash_desc *desc, const void *in)
114 struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
115 struct zynqmp_sha_tfm_ctx *tctx = crypto_shash_ctx(desc->tfm);
117 dctx->fbk_req.tfm = tctx->fbk_tfm;
118 return crypto_shash_import(&dctx->fbk_req, in);
121 static int zynqmp_sha_export(struct shash_desc *desc, void *out)
123 struct zynqmp_sha_desc_ctx *dctx = shash_desc_ctx(desc);
125 return crypto_shash_export(&dctx->fbk_req, out);
128 static int zynqmp_sha_digest(struct shash_desc *desc, const u8 *data, unsigned int len, u8 *out)
130 unsigned int remaining_len = len;
134 ret = zynqmp_pm_sha_hash(0, 0, ZYNQMP_SHA3_INIT);
138 while (remaining_len != 0) {
139 memzero_explicit(ubuf, ZYNQMP_DMA_ALLOC_FIXED_SIZE);
140 if (remaining_len >= ZYNQMP_DMA_ALLOC_FIXED_SIZE) {
141 update_size = ZYNQMP_DMA_ALLOC_FIXED_SIZE;
142 remaining_len -= ZYNQMP_DMA_ALLOC_FIXED_SIZE;
144 update_size = remaining_len;
147 memcpy(ubuf, data, update_size);
148 flush_icache_range((unsigned long)ubuf, (unsigned long)ubuf + update_size);
149 ret = zynqmp_pm_sha_hash(update_dma_addr, update_size, ZYNQMP_SHA3_UPDATE);
156 ret = zynqmp_pm_sha_hash(final_dma_addr, SHA3_384_DIGEST_SIZE, ZYNQMP_SHA3_FINAL);
157 memcpy(out, fbuf, SHA3_384_DIGEST_SIZE);
158 memzero_explicit(fbuf, SHA3_384_DIGEST_SIZE);
163 static struct zynqmp_sha_drv_ctx sha3_drv_ctx = {
165 .init = zynqmp_sha_init,
166 .update = zynqmp_sha_update,
167 .final = zynqmp_sha_final,
168 .finup = zynqmp_sha_finup,
169 .digest = zynqmp_sha_digest,
170 .export = zynqmp_sha_export,
171 .import = zynqmp_sha_import,
172 .init_tfm = zynqmp_sha_init_tfm,
173 .exit_tfm = zynqmp_sha_exit_tfm,
174 .descsize = sizeof(struct zynqmp_sha_desc_ctx),
175 .statesize = sizeof(struct sha3_state),
176 .digestsize = SHA3_384_DIGEST_SIZE,
178 .cra_name = "sha3-384",
179 .cra_driver_name = "zynqmp-sha3-384",
181 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
182 CRYPTO_ALG_ALLOCATES_MEMORY |
183 CRYPTO_ALG_NEED_FALLBACK,
184 .cra_blocksize = SHA3_384_BLOCK_SIZE,
185 .cra_ctxsize = sizeof(struct zynqmp_sha_tfm_ctx),
187 .cra_module = THIS_MODULE,
192 static int zynqmp_sha_probe(struct platform_device *pdev)
194 struct device *dev = &pdev->dev;
198 /* Verify the hardware is present */
199 err = zynqmp_pm_get_api_version(&v);
204 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(ZYNQMP_DMA_BIT_MASK));
206 dev_err(dev, "No usable DMA configuration\n");
210 err = crypto_register_shash(&sha3_drv_ctx.sha3_384);
212 dev_err(dev, "Failed to register shash alg.\n");
216 sha3_drv_ctx.dev = dev;
217 platform_set_drvdata(pdev, &sha3_drv_ctx);
219 ubuf = dma_alloc_coherent(dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, &update_dma_addr, GFP_KERNEL);
225 fbuf = dma_alloc_coherent(dev, SHA3_384_DIGEST_SIZE, &final_dma_addr, GFP_KERNEL);
234 dma_free_coherent(sha3_drv_ctx.dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, ubuf, update_dma_addr);
237 crypto_unregister_shash(&sha3_drv_ctx.sha3_384);
242 static int zynqmp_sha_remove(struct platform_device *pdev)
244 sha3_drv_ctx.dev = platform_get_drvdata(pdev);
246 dma_free_coherent(sha3_drv_ctx.dev, ZYNQMP_DMA_ALLOC_FIXED_SIZE, ubuf, update_dma_addr);
247 dma_free_coherent(sha3_drv_ctx.dev, SHA3_384_DIGEST_SIZE, fbuf, final_dma_addr);
248 crypto_unregister_shash(&sha3_drv_ctx.sha3_384);
253 static struct platform_driver zynqmp_sha_driver = {
254 .probe = zynqmp_sha_probe,
255 .remove = zynqmp_sha_remove,
257 .name = "zynqmp-sha3-384",
261 module_platform_driver(zynqmp_sha_driver);
262 MODULE_DESCRIPTION("ZynqMP SHA3 hardware acceleration support.");
263 MODULE_LICENSE("GPL v2");
264 MODULE_AUTHOR("Harsha <harsha.harsha@xilinx.com>");