drivers/crypto/ux500/hash/hash_core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Cryptographic API.
   4  * Support for Nomadik hardware crypto engine.
   5
   6  * Copyright (C) ST-Ericsson SA 2010
   7  * Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson
   8  * Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson
   9  * Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
  10  * Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
  11  * Author: Andreas Westin <andreas.westin@stericsson.com> for ST-Ericsson.
  12  */
  13
  14 #define pr_fmt(fmt) "hashX hashX: " fmt
  15
  16 #include <linux/clk.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/klist.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/mod_devicetable.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/crypto.h>
  28
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/dmaengine.h>
  31 #include <linux/bitops.h>
  32
  33 #include <crypto/internal/hash.h>
  34 #include <crypto/sha.h>
  35 #include <crypto/scatterwalk.h>
  36 #include <crypto/algapi.h>
  37
  38 #include <linux/platform_data/crypto-ux500.h>
  39
  40 #include "hash_alg.h"
  41
  42 static int hash_mode;
  43 module_param(hash_mode, int, 0);
  44 MODULE_PARM_DESC(hash_mode, "CPU or DMA mode. CPU = 0 (default), DMA = 1");
  45
  46 /* HMAC-SHA1, no key */
  47 static const u8 zero_message_hmac_sha1[SHA1_DIGEST_SIZE] = {
  48         0xfb, 0xdb, 0x1d, 0x1b, 0x18, 0xaa, 0x6c, 0x08,
  49         0x32, 0x4b, 0x7d, 0x64, 0xb7, 0x1f, 0xb7, 0x63,
  50         0x70, 0x69, 0x0e, 0x1d
  51 };
  52
  53 /* HMAC-SHA256, no key */
  54 static const u8 zero_message_hmac_sha256[SHA256_DIGEST_SIZE] = {
  55         0xb6, 0x13, 0x67, 0x9a, 0x08, 0x14, 0xd9, 0xec,
  56         0x77, 0x2f, 0x95, 0xd7, 0x78, 0xc3, 0x5f, 0xc5,
  57         0xff, 0x16, 0x97, 0xc4, 0x93, 0x71, 0x56, 0x53,
  58         0xc6, 0xc7, 0x12, 0x14, 0x42, 0x92, 0xc5, 0xad
  59 };
  60
  61 /**
  62  * struct hash_driver_data - data specific to the driver.
  63  *
  64  * @device_list:        A list of registered devices to choose from.
  65  * @device_allocation:  A semaphore initialized with number of devices.
  66  */
  67 struct hash_driver_data {
  68         struct klist            device_list;
  69         struct semaphore        device_allocation;
  70 };
  71
  72 static struct hash_driver_data  driver_data;
  73
  74 /* Declaration of functions */
  75 /**
  76  * hash_messagepad - Pads a message and write the nblw bits.
  77  * @device_data:        Structure for the hash device.
  78  * @message:            Last word of a message
  79  * @index_bytes:        The number of bytes in the last message
  80  *
  81  * This function manages the final part of the digest calculation, when less
  82  * than 512 bits (64 bytes) remain in message. This means index_bytes < 64.
  83  *
  84  */
  85 static void hash_messagepad(struct hash_device_data *device_data,
  86                             const u32 *message, u8 index_bytes);
  87
  88 /**
  89  * release_hash_device - Releases a previously allocated hash device.
  90  * @device_data:        Structure for the hash device.
  91  *
  92  */
  93 static void release_hash_device(struct hash_device_data *device_data)
  94 {
  95         spin_lock(&device_data->ctx_lock);
  96         device_data->current_ctx->device = NULL;
  97         device_data->current_ctx = NULL;
  98         spin_unlock(&device_data->ctx_lock);
  99
 100         /*
 101          * The down_interruptible part for this semaphore is called in
 102          * cryp_get_device_data.
 103          */
 104         up(&driver_data.device_allocation);
 105 }
 106
 107 static void hash_dma_setup_channel(struct hash_device_data *device_data,
 108                                    struct device *dev)
 109 {
 110         struct hash_platform_data *platform_data = dev->platform_data;
 111         struct dma_slave_config conf = {
 112                 .direction = DMA_MEM_TO_DEV,
 113                 .dst_addr = device_data->phybase + HASH_DMA_FIFO,
 114                 .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
 115                 .dst_maxburst = 16,
 116         };
 117
 118         dma_cap_zero(device_data->dma.mask);
 119         dma_cap_set(DMA_SLAVE, device_data->dma.mask);
 120
 121         device_data->dma.cfg_mem2hash = platform_data->mem_to_engine;
 122         device_data->dma.chan_mem2hash =
 123                 dma_request_channel(device_data->dma.mask,
 124                                     platform_data->dma_filter,
 125                                     device_data->dma.cfg_mem2hash);
 126
 127         dmaengine_slave_config(device_data->dma.chan_mem2hash, &conf);
 128
 129         init_completion(&device_data->dma.complete);
 130 }
 131
 132 static void hash_dma_callback(void *data)
 133 {
 134         struct hash_ctx *ctx = data;
 135
 136         complete(&ctx->device->dma.complete);
 137 }
 138
 139 static int hash_set_dma_transfer(struct hash_ctx *ctx, struct scatterlist *sg,
 140                                  int len, enum dma_data_direction direction)
 141 {
 142         struct dma_async_tx_descriptor *desc = NULL;
 143         struct dma_chan *channel = NULL;
 144
 145         if (direction != DMA_TO_DEVICE) {
 146                 dev_err(ctx->device->dev, "%s: Invalid DMA direction\n",
 147                         __func__);
 148                 return -EFAULT;
 149         }
 150
 151         sg->length = ALIGN(sg->length, HASH_DMA_ALIGN_SIZE);
 152
 153         channel = ctx->device->dma.chan_mem2hash;
 154         ctx->device->dma.sg = sg;
 155         ctx->device->dma.sg_len = dma_map_sg(channel->device->dev,
 156                         ctx->device->dma.sg, ctx->device->dma.nents,
 157                         direction);
 158
 159         if (!ctx->device->dma.sg_len) {
 160                 dev_err(ctx->device->dev, "%s: Could not map the sg list (TO_DEVICE)\n",
 161                         __func__);
 162                 return -EFAULT;
 163         }
 164
 165         dev_dbg(ctx->device->dev, "%s: Setting up DMA for buffer (TO_DEVICE)\n",
 166                 __func__);
 167         desc = dmaengine_prep_slave_sg(channel,
 168                         ctx->device->dma.sg, ctx->device->dma.sg_len,
 169                         DMA_MEM_TO_DEV, DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
 170         if (!desc) {
 171                 dev_err(ctx->device->dev,
 172                         "%s: dmaengine_prep_slave_sg() failed!\n", __func__);
 173                 return -EFAULT;
 174         }
 175
 176         desc->callback = hash_dma_callback;
 177         desc->callback_param = ctx;
 178
 179         dmaengine_submit(desc);
 180         dma_async_issue_pending(channel);
 181
 182         return 0;
 183 }
 184
 185 static void hash_dma_done(struct hash_ctx *ctx)
 186 {
 187         struct dma_chan *chan;
 188
 189         chan = ctx->device->dma.chan_mem2hash;
 190         dmaengine_terminate_all(chan);
 191         dma_unmap_sg(chan->device->dev, ctx->device->dma.sg,
 192                      ctx->device->dma.sg_len, DMA_TO_DEVICE);
 193 }
 194
 195 static int hash_dma_write(struct hash_ctx *ctx,
 196                           struct scatterlist *sg, int len)
 197 {
 198         int error = hash_set_dma_transfer(ctx, sg, len, DMA_TO_DEVICE);
 199         if (error) {
 200                 dev_dbg(ctx->device->dev,
 201                         "%s: hash_set_dma_transfer() failed\n", __func__);
 202                 return error;
 203         }
 204
 205         return len;
 206 }
 207
 208 /**
 209  * get_empty_message_digest - Returns a pre-calculated digest for
 210  * the empty message.
 211  * @device_data:        Structure for the hash device.
 212  * @zero_hash:          Buffer to return the empty message digest.
 213  * @zero_hash_size:     Hash size of the empty message digest.
 214  * @zero_digest:        True if zero_digest returned.
 215  */
 216 static int get_empty_message_digest(
 217                 struct hash_device_data *device_data,
 218                 u8 *zero_hash, u32 *zero_hash_size, bool *zero_digest)
 219 {
 220         int ret = 0;
 221         struct hash_ctx *ctx = device_data->current_ctx;
 222         *zero_digest = false;
 223
 224         /**
 225          * Caller responsible for ctx != NULL.
 226          */
 227
 228         if (HASH_OPER_MODE_HASH == ctx->config.oper_mode) {
 229                 if (HASH_ALGO_SHA1 == ctx->config.algorithm) {
 230                         memcpy(zero_hash, &sha1_zero_message_hash[0],
 231                                SHA1_DIGEST_SIZE);
 232                         *zero_hash_size = SHA1_DIGEST_SIZE;
 233                         *zero_digest = true;
 234                 } else if (HASH_ALGO_SHA256 ==
 235                                 ctx->config.algorithm) {
 236                         memcpy(zero_hash, &sha256_zero_message_hash[0],
 237                                SHA256_DIGEST_SIZE);
 238                         *zero_hash_size = SHA256_DIGEST_SIZE;
 239                         *zero_digest = true;
 240                 } else {
 241                         dev_err(device_data->dev, "%s: Incorrect algorithm!\n",
 242                                 __func__);
 243                         ret = -EINVAL;
 244                         goto out;
 245                 }
 246         } else if (HASH_OPER_MODE_HMAC == ctx->config.oper_mode) {
 247                 if (!ctx->keylen) {
 248                         if (HASH_ALGO_SHA1 == ctx->config.algorithm) {
 249                                 memcpy(zero_hash, &zero_message_hmac_sha1[0],
 250                                        SHA1_DIGEST_SIZE);
 251                                 *zero_hash_size = SHA1_DIGEST_SIZE;
 252                                 *zero_digest = true;
 253                         } else if (HASH_ALGO_SHA256 == ctx->config.algorithm) {
 254                                 memcpy(zero_hash, &zero_message_hmac_sha256[0],
 255                                        SHA256_DIGEST_SIZE);
 256                                 *zero_hash_size = SHA256_DIGEST_SIZE;
 257                                 *zero_digest = true;
 258                         } else {
 259                                 dev_err(device_data->dev, "%s: Incorrect algorithm!\n",
 260                                         __func__);
 261                                 ret = -EINVAL;
 262                                 goto out;
 263                         }
 264                 } else {
 265                         dev_dbg(device_data->dev,
 266                                 "%s: Continue hash calculation, since hmac key available\n",
 267                                 __func__);
 268                 }
 269         }
 270 out:
 271
 272         return ret;
 273 }
 274
 275 /**
 276  * hash_disable_power - Request to disable power and clock.
 277  * @device_data:        Structure for the hash device.
 278  * @save_device_state:  If true, saves the current hw state.
 279  *
 280  * This function request for disabling power (regulator) and clock,
 281  * and could also save current hw state.
 282  */
 283 static int hash_disable_power(struct hash_device_data *device_data,
 284                               bool save_device_state)
 285 {
 286         int ret = 0;
 287         struct device *dev = device_data->dev;
 288
 289         spin_lock(&device_data->power_state_lock);
 290         if (!device_data->power_state)
 291                 goto out;
 292
 293         if (save_device_state) {
 294                 hash_save_state(device_data,
 295                                 &device_data->state);
 296                 device_data->restore_dev_state = true;
 297         }
 298
 299         clk_disable(device_data->clk);
 300         ret = regulator_disable(device_data->regulator);
 301         if (ret)
 302                 dev_err(dev, "%s: regulator_disable() failed!\n", __func__);
 303
 304         device_data->power_state = false;
 305
 306 out:
 307         spin_unlock(&device_data->power_state_lock);
 308
 309         return ret;
 310 }
 311
 312 /**
 313  * hash_enable_power - Request to enable power and clock.
 314  * @device_data:                Structure for the hash device.
 315  * @restore_device_state:       If true, restores a previous saved hw state.
 316  *
 317  * This function request for enabling power (regulator) and clock,
 318  * and could also restore a previously saved hw state.
 319  */
 320 static int hash_enable_power(struct hash_device_data *device_data,
 321                              bool restore_device_state)
 322 {
 323         int ret = 0;
 324         struct device *dev = device_data->dev;
 325
 326         spin_lock(&device_data->power_state_lock);
 327         if (!device_data->power_state) {
 328                 ret = regulator_enable(device_data->regulator);
 329                 if (ret) {
 330                         dev_err(dev, "%s: regulator_enable() failed!\n",
 331                                 __func__);
 332                         goto out;
 333                 }
 334                 ret = clk_enable(device_data->clk);
 335                 if (ret) {
 336                         dev_err(dev, "%s: clk_enable() failed!\n", __func__);
 337                         ret = regulator_disable(
 338                                         device_data->regulator);
 339                         goto out;
 340                 }
 341                 device_data->power_state = true;
 342         }
 343
 344         if (device_data->restore_dev_state) {
 345                 if (restore_device_state) {
 346                         device_data->restore_dev_state = false;
 347                         hash_resume_state(device_data, &device_data->state);
 348                 }
 349         }
 350 out:
 351         spin_unlock(&device_data->power_state_lock);
 352
 353         return ret;
 354 }
 355
 356 /**
 357  * hash_get_device_data - Checks for an available hash device and return it.
 358  * @hash_ctx:           Structure for the hash context.
 359  * @device_data:        Structure for the hash device.
 360  *
 361  * This function check for an available hash device and return it to
 362  * the caller.
 363  * Note! Caller need to release the device, calling up().
 364  */
 365 static int hash_get_device_data(struct hash_ctx *ctx,
 366                                 struct hash_device_data **device_data)
 367 {
 368         int                     ret;
 369         struct klist_iter       device_iterator;
 370         struct klist_node       *device_node;
 371         struct hash_device_data *local_device_data = NULL;
 372
 373         /* Wait until a device is available */
 374         ret = down_interruptible(&driver_data.device_allocation);
 375         if (ret)
 376                 return ret;  /* Interrupted */
 377
 378         /* Select a device */
 379         klist_iter_init(&driver_data.device_list, &device_iterator);
 380         device_node = klist_next(&device_iterator);
 381         while (device_node) {
 382                 local_device_data = container_of(device_node,
 383                                            struct hash_device_data, list_node);
 384                 spin_lock(&local_device_data->ctx_lock);
 385                 /* current_ctx allocates a device, NULL = unallocated */
 386                 if (local_device_data->current_ctx) {
 387                         device_node = klist_next(&device_iterator);
 388                 } else {
 389                         local_device_data->current_ctx = ctx;
 390                         ctx->device = local_device_data;
 391                         spin_unlock(&local_device_data->ctx_lock);
 392                         break;
 393                 }
 394                 spin_unlock(&local_device_data->ctx_lock);
 395         }
 396         klist_iter_exit(&device_iterator);
 397
 398         if (!device_node) {
 399                 /**
 400                  * No free device found.
 401                  * Since we allocated a device with down_interruptible, this
 402                  * should not be able to happen.
 403                  * Number of available devices, which are contained in
 404                  * device_allocation, is therefore decremented by not doing
 405                  * an up(device_allocation).
 406                  */
 407                 return -EBUSY;
 408         }
 409
 410         *device_data = local_device_data;
 411
 412         return 0;
 413 }
 414
 415 /**
 416  * hash_hw_write_key - Writes the key to the hardware registries.
 417  *
 418  * @device_data:        Structure for the hash device.
 419  * @key:                Key to be written.
 420  * @keylen:             The lengt of the key.
 421  *
 422  * Note! This function DOES NOT write to the NBLW registry, even though
 423  * specified in the the hw design spec. Either due to incorrect info in the
 424  * spec or due to a bug in the hw.
 425  */
 426 static void hash_hw_write_key(struct hash_device_data *device_data,
 427                               const u8 *key, unsigned int keylen)
 428 {
 429         u32 word = 0;
 430         int nwords = 1;
 431
 432         HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
 433
 434         while (keylen >= 4) {
 435                 u32 *key_word = (u32 *)key;
 436
 437                 HASH_SET_DIN(key_word, nwords);
 438                 keylen -= 4;
 439                 key += 4;
 440         }
 441
 442         /* Take care of the remaining bytes in the last word */
 443         if (keylen) {
 444                 word = 0;
 445                 while (keylen) {
 446                         word |= (key[keylen - 1] << (8 * (keylen - 1)));
 447                         keylen--;
 448                 }
 449
 450                 HASH_SET_DIN(&word, nwords);
 451         }
 452
 453         while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
 454                 cpu_relax();
 455
 456         HASH_SET_DCAL;
 457
 458         while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
 459                 cpu_relax();
 460 }
 461
 462 /**
 463  * init_hash_hw - Initialise the hash hardware for a new calculation.
 464  * @device_data:        Structure for the hash device.
 465  * @ctx:                The hash context.
 466  *
 467  * This function will enable the bits needed to clear and start a new
 468  * calculation.
 469  */
 470 static int init_hash_hw(struct hash_device_data *device_data,
 471                         struct hash_ctx *ctx)
 472 {
 473         int ret = 0;
 474
 475         ret = hash_setconfiguration(device_data, &ctx->config);
 476         if (ret) {
 477                 dev_err(device_data->dev, "%s: hash_setconfiguration() failed!\n",
 478                         __func__);
 479                 return ret;
 480         }
 481
 482         hash_begin(device_data, ctx);
 483
 484         if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC)
 485                 hash_hw_write_key(device_data, ctx->key, ctx->keylen);
 486
 487         return ret;
 488 }
 489
 490 /**
 491  * hash_get_nents - Return number of entries (nents) in scatterlist (sg).
 492  *
 493  * @sg:         Scatterlist.
 494  * @size:       Size in bytes.
 495  * @aligned:    True if sg data aligned to work in DMA mode.
 496  *
 497  */
 498 static int hash_get_nents(struct scatterlist *sg, int size, bool *aligned)
 499 {
 500         int nents = 0;
 501         bool aligned_data = true;
 502
 503         while (size > 0 && sg) {
 504                 nents++;
 505                 size -= sg->length;
 506
 507                 /* hash_set_dma_transfer will align last nent */
 508                 if ((aligned && !IS_ALIGNED(sg->offset, HASH_DMA_ALIGN_SIZE)) ||
 509                     (!IS_ALIGNED(sg->length, HASH_DMA_ALIGN_SIZE) && size > 0))
 510                         aligned_data = false;
 511
 512                 sg = sg_next(sg);
 513         }
 514
 515         if (aligned)
 516                 *aligned = aligned_data;
 517
 518         if (size != 0)
 519                 return -EFAULT;
 520
 521         return nents;
 522 }
 523
 524 /**
 525  * hash_dma_valid_data - checks for dma valid sg data.
 526  * @sg:         Scatterlist.
 527  * @datasize:   Datasize in bytes.
 528  *
 529  * NOTE! This function checks for dma valid sg data, since dma
 530  * only accept datasizes of even wordsize.
 531  */
 532 static bool hash_dma_valid_data(struct scatterlist *sg, int datasize)
 533 {
 534         bool aligned;
 535
 536         /* Need to include at least one nent, else error */
 537         if (hash_get_nents(sg, datasize, &aligned) < 1)
 538                 return false;
 539
 540         return aligned;
 541 }
 542
 543 /**
 544  * hash_init - Common hash init function for SHA1/SHA2 (SHA256).
 545  * @req: The hash request for the job.
 546  *
 547  * Initialize structures.
 548  */
 549 static int ux500_hash_init(struct ahash_request *req)
 550 {
 551         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 552         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 553         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
 554
 555         if (!ctx->key)
 556                 ctx->keylen = 0;
 557
 558         memset(&req_ctx->state, 0, sizeof(struct hash_state));
 559         req_ctx->updated = 0;
 560         if (hash_mode == HASH_MODE_DMA) {
 561                 if (req->nbytes < HASH_DMA_ALIGN_SIZE) {
 562                         req_ctx->dma_mode = false; /* Don't use DMA */
 563
 564                         pr_debug("%s: DMA mode, but direct to CPU mode for data size < %d\n",
 565                                  __func__, HASH_DMA_ALIGN_SIZE);
 566                 } else {
 567                         if (req->nbytes >= HASH_DMA_PERFORMANCE_MIN_SIZE &&
 568                             hash_dma_valid_data(req->src, req->nbytes)) {
 569                                 req_ctx->dma_mode = true;
 570                         } else {
 571                                 req_ctx->dma_mode = false;
 572                                 pr_debug("%s: DMA mode, but use CPU mode for datalength < %d or non-aligned data, except in last nent\n",
 573                                          __func__,
 574                                          HASH_DMA_PERFORMANCE_MIN_SIZE);
 575                         }
 576                 }
 577         }
 578         return 0;
 579 }
 580
 581 /**
 582  * hash_processblock - This function processes a single block of 512 bits (64
 583  *                     bytes), word aligned, starting at message.
 584  * @device_data:        Structure for the hash device.
 585  * @message:            Block (512 bits) of message to be written to
 586  *                      the HASH hardware.
 587  *
 588  */
 589 static void hash_processblock(struct hash_device_data *device_data,
 590                               const u32 *message, int length)
 591 {
 592         int len = length / HASH_BYTES_PER_WORD;
 593         /*
 594          * NBLW bits. Reset the number of bits in last word (NBLW).
 595          */
 596         HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
 597
 598         /*
 599          * Write message data to the HASH_DIN register.
 600          */
 601         HASH_SET_DIN(message, len);
 602 }
 603
 604 /**
 605  * hash_messagepad - Pads a message and write the nblw bits.
 606  * @device_data:        Structure for the hash device.
 607  * @message:            Last word of a message.
 608  * @index_bytes:        The number of bytes in the last message.
 609  *
 610  * This function manages the final part of the digest calculation, when less
 611  * than 512 bits (64 bytes) remain in message. This means index_bytes < 64.
 612  *
 613  */
 614 static void hash_messagepad(struct hash_device_data *device_data,
 615                             const u32 *message, u8 index_bytes)
 616 {
 617         int nwords = 1;
 618
 619         /*
 620          * Clear hash str register, only clear NBLW
 621          * since DCAL will be reset by hardware.
 622          */
 623         HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
 624
 625         /* Main loop */
 626         while (index_bytes >= 4) {
 627                 HASH_SET_DIN(message, nwords);
 628                 index_bytes -= 4;
 629                 message++;
 630         }
 631
 632         if (index_bytes)
 633                 HASH_SET_DIN(message, nwords);
 634
 635         while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
 636                 cpu_relax();
 637
 638         /* num_of_bytes == 0 => NBLW <- 0 (32 bits valid in DATAIN) */
 639         HASH_SET_NBLW(index_bytes * 8);
 640         dev_dbg(device_data->dev, "%s: DIN=0x%08x NBLW=%lu\n",
 641                 __func__, readl_relaxed(&device_data->base->din),
 642                 readl_relaxed(&device_data->base->str) & HASH_STR_NBLW_MASK);
 643         HASH_SET_DCAL;
 644         dev_dbg(device_data->dev, "%s: after dcal -> DIN=0x%08x NBLW=%lu\n",
 645                 __func__, readl_relaxed(&device_data->base->din),
 646                 readl_relaxed(&device_data->base->str) & HASH_STR_NBLW_MASK);
 647
 648         while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
 649                 cpu_relax();
 650 }
 651
 652 /**
 653  * hash_incrementlength - Increments the length of the current message.
 654  * @ctx: Hash context
 655  * @incr: Length of message processed already
 656  *
 657  * Overflow cannot occur, because conditions for overflow are checked in
 658  * hash_hw_update.
 659  */
 660 static void hash_incrementlength(struct hash_req_ctx *ctx, u32 incr)
 661 {
 662         ctx->state.length.low_word += incr;
 663
 664         /* Check for wrap-around */
 665         if (ctx->state.length.low_word < incr)
 666                 ctx->state.length.high_word++;
 667 }
 668
 669 /**
 670  * hash_setconfiguration - Sets the required configuration for the hash
 671  *                         hardware.
 672  * @device_data:        Structure for the hash device.
 673  * @config:             Pointer to a configuration structure.
 674  */
 675 int hash_setconfiguration(struct hash_device_data *device_data,
 676                           struct hash_config *config)
 677 {
 678         int ret = 0;
 679
 680         if (config->algorithm != HASH_ALGO_SHA1 &&
 681             config->algorithm != HASH_ALGO_SHA256)
 682                 return -EPERM;
 683
 684         /*
 685          * DATAFORM bits. Set the DATAFORM bits to 0b11, which means the data
 686          * to be written to HASH_DIN is considered as 32 bits.
 687          */
 688         HASH_SET_DATA_FORMAT(config->data_format);
 689
 690         /*
 691          * ALGO bit. Set to 0b1 for SHA-1 and 0b0 for SHA-256
 692          */
 693         switch (config->algorithm) {
 694         case HASH_ALGO_SHA1:
 695                 HASH_SET_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK);
 696                 break;
 697
 698         case HASH_ALGO_SHA256:
 699                 HASH_CLEAR_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK);
 700                 break;
 701
 702         default:
 703                 dev_err(device_data->dev, "%s: Incorrect algorithm\n",
 704                         __func__);
 705                 return -EPERM;
 706         }
 707
 708         /*
 709          * MODE bit. This bit selects between HASH or HMAC mode for the
 710          * selected algorithm. 0b0 = HASH and 0b1 = HMAC.
 711          */
 712         if (HASH_OPER_MODE_HASH == config->oper_mode)
 713                 HASH_CLEAR_BITS(&device_data->base->cr,
 714                                 HASH_CR_MODE_MASK);
 715         else if (HASH_OPER_MODE_HMAC == config->oper_mode) {
 716                 HASH_SET_BITS(&device_data->base->cr, HASH_CR_MODE_MASK);
 717                 if (device_data->current_ctx->keylen > HASH_BLOCK_SIZE) {
 718                         /* Truncate key to blocksize */
 719                         dev_dbg(device_data->dev, "%s: LKEY set\n", __func__);
 720                         HASH_SET_BITS(&device_data->base->cr,
 721                                       HASH_CR_LKEY_MASK);
 722                 } else {
 723                         dev_dbg(device_data->dev, "%s: LKEY cleared\n",
 724                                 __func__);
 725                         HASH_CLEAR_BITS(&device_data->base->cr,
 726                                         HASH_CR_LKEY_MASK);
 727                 }
 728         } else {        /* Wrong hash mode */
 729                 ret = -EPERM;
 730                 dev_err(device_data->dev, "%s: HASH_INVALID_PARAMETER!\n",
 731                         __func__);
 732         }
 733         return ret;
 734 }
 735
 736 /**
 737  * hash_begin - This routine resets some globals and initializes the hash
 738  *              hardware.
 739  * @device_data:        Structure for the hash device.
 740  * @ctx:                Hash context.
 741  */
 742 void hash_begin(struct hash_device_data *device_data, struct hash_ctx *ctx)
 743 {
 744         /* HW and SW initializations */
 745         /* Note: there is no need to initialize buffer and digest members */
 746
 747         while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
 748                 cpu_relax();
 749
 750         /*
 751          * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
 752          * prepare the initialize the HASH accelerator to compute the message
 753          * digest of a new message.
 754          */
 755         HASH_INITIALIZE;
 756
 757         /*
 758          * NBLW bits. Reset the number of bits in last word (NBLW).
 759          */
 760         HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
 761 }
 762
 763 static int hash_process_data(struct hash_device_data *device_data,
 764                              struct hash_ctx *ctx, struct hash_req_ctx *req_ctx,
 765                              int msg_length, u8 *data_buffer, u8 *buffer,
 766                              u8 *index)
 767 {
 768         int ret = 0;
 769         u32 count;
 770
 771         do {
 772                 if ((*index + msg_length) < HASH_BLOCK_SIZE) {
 773                         for (count = 0; count < msg_length; count++) {
 774                                 buffer[*index + count] =
 775                                         *(data_buffer + count);
 776                         }
 777                         *index += msg_length;
 778                         msg_length = 0;
 779                 } else {
 780                         if (req_ctx->updated) {
 781                                 ret = hash_resume_state(device_data,
 782                                                 &device_data->state);
 783                                 memmove(req_ctx->state.buffer,
 784                                         device_data->state.buffer,
 785                                         HASH_BLOCK_SIZE);
 786                                 if (ret) {
 787                                         dev_err(device_data->dev,
 788                                                 "%s: hash_resume_state() failed!\n",
 789                                                 __func__);
 790                                         goto out;
 791                                 }
 792                         } else {
 793                                 ret = init_hash_hw(device_data, ctx);
 794                                 if (ret) {
 795                                         dev_err(device_data->dev,
 796                                                 "%s: init_hash_hw() failed!\n",
 797                                                 __func__);
 798                                         goto out;
 799                                 }
 800                                 req_ctx->updated = 1;
 801                         }
 802                         /*
 803                          * If 'data_buffer' is four byte aligned and
 804                          * local buffer does not have any data, we can
 805                          * write data directly from 'data_buffer' to
 806                          * HW peripheral, otherwise we first copy data
 807                          * to a local buffer
 808                          */
 809                         if (IS_ALIGNED((unsigned long)data_buffer, 4) &&
 810                             (0 == *index))
 811                                 hash_processblock(device_data,
 812                                                   (const u32 *)data_buffer,
 813                                                   HASH_BLOCK_SIZE);
 814                         else {
 815                                 for (count = 0;
 816                                      count < (u32)(HASH_BLOCK_SIZE - *index);
 817                                      count++) {
 818                                         buffer[*index + count] =
 819                                                 *(data_buffer + count);
 820                                 }
 821                                 hash_processblock(device_data,
 822                                                   (const u32 *)buffer,
 823                                                   HASH_BLOCK_SIZE);
 824                         }
 825                         hash_incrementlength(req_ctx, HASH_BLOCK_SIZE);
 826                         data_buffer += (HASH_BLOCK_SIZE - *index);
 827
 828                         msg_length -= (HASH_BLOCK_SIZE - *index);
 829                         *index = 0;
 830
 831                         ret = hash_save_state(device_data,
 832                                         &device_data->state);
 833
 834                         memmove(device_data->state.buffer,
 835                                 req_ctx->state.buffer,
 836                                 HASH_BLOCK_SIZE);
 837                         if (ret) {
 838                                 dev_err(device_data->dev, "%s: hash_save_state() failed!\n",
 839                                         __func__);
 840                                 goto out;
 841                         }
 842                 }
 843         } while (msg_length != 0);
 844 out:
 845
 846         return ret;
 847 }
 848
 849 /**
 850  * hash_dma_final - The hash dma final function for SHA1/SHA256.
 851  * @req:        The hash request for the job.
 852  */
 853 static int hash_dma_final(struct ahash_request *req)
 854 {
 855         int ret = 0;
 856         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 857         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 858         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
 859         struct hash_device_data *device_data;
 860         u8 digest[SHA256_DIGEST_SIZE];
 861         int bytes_written = 0;
 862
 863         ret = hash_get_device_data(ctx, &device_data);
 864         if (ret)
 865                 return ret;
 866
 867         dev_dbg(device_data->dev, "%s: (ctx=0x%lx)!\n", __func__,
 868                 (unsigned long)ctx);
 869
 870         if (req_ctx->updated) {
 871                 ret = hash_resume_state(device_data, &device_data->state);
 872
 873                 if (ret) {
 874                         dev_err(device_data->dev, "%s: hash_resume_state() failed!\n",
 875                                 __func__);
 876                         goto out;
 877                 }
 878         }
 879
 880         if (!req_ctx->updated) {
 881                 ret = hash_setconfiguration(device_data, &ctx->config);
 882                 if (ret) {
 883                         dev_err(device_data->dev,
 884                                 "%s: hash_setconfiguration() failed!\n",
 885                                 __func__);
 886                         goto out;
 887                 }
 888
 889                 /* Enable DMA input */
 890                 if (hash_mode != HASH_MODE_DMA || !req_ctx->dma_mode) {
 891                         HASH_CLEAR_BITS(&device_data->base->cr,
 892                                         HASH_CR_DMAE_MASK);
 893                 } else {
 894                         HASH_SET_BITS(&device_data->base->cr,
 895                                       HASH_CR_DMAE_MASK);
 896                         HASH_SET_BITS(&device_data->base->cr,
 897                                       HASH_CR_PRIVN_MASK);
 898                 }
 899
 900                 HASH_INITIALIZE;
 901
 902                 if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC)
 903                         hash_hw_write_key(device_data, ctx->key, ctx->keylen);
 904
 905                 /* Number of bits in last word = (nbytes * 8) % 32 */
 906                 HASH_SET_NBLW((req->nbytes * 8) % 32);
 907                 req_ctx->updated = 1;
 908         }
 909
 910         /* Store the nents in the dma struct. */
 911         ctx->device->dma.nents = hash_get_nents(req->src, req->nbytes, NULL);
 912         if (!ctx->device->dma.nents) {
 913                 dev_err(device_data->dev, "%s: ctx->device->dma.nents = 0\n",
 914                         __func__);
 915                 ret = ctx->device->dma.nents;
 916                 goto out;
 917         }
 918
 919         bytes_written = hash_dma_write(ctx, req->src, req->nbytes);
 920         if (bytes_written != req->nbytes) {
 921                 dev_err(device_data->dev, "%s: hash_dma_write() failed!\n",
 922                         __func__);
 923                 ret = bytes_written;
 924                 goto out;
 925         }
 926
 927         wait_for_completion(&ctx->device->dma.complete);
 928         hash_dma_done(ctx);
 929
 930         while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
 931                 cpu_relax();
 932
 933         if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) {
 934                 unsigned int keylen = ctx->keylen;
 935                 u8 *key = ctx->key;
 936
 937                 dev_dbg(device_data->dev, "%s: keylen: %d\n",
 938                         __func__, ctx->keylen);
 939                 hash_hw_write_key(device_data, key, keylen);
 940         }
 941
 942         hash_get_digest(device_data, digest, ctx->config.algorithm);
 943         memcpy(req->result, digest, ctx->digestsize);
 944
 945 out:
 946         release_hash_device(device_data);
 947
 948         /**
 949          * Allocated in setkey, and only used in HMAC.
 950          */
 951         kfree(ctx->key);
 952
 953         return ret;
 954 }
 955
 956 /**
 957  * hash_hw_final - The final hash calculation function
 958  * @req:        The hash request for the job.
 959  */
 960 static int hash_hw_final(struct ahash_request *req)
 961 {
 962         int ret = 0;
 963         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 964         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 965         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
 966         struct hash_device_data *device_data;
 967         u8 digest[SHA256_DIGEST_SIZE];
 968
 969         ret = hash_get_device_data(ctx, &device_data);
 970         if (ret)
 971                 return ret;
 972
 973         dev_dbg(device_data->dev, "%s: (ctx=0x%lx)!\n", __func__,
 974                 (unsigned long)ctx);
 975
 976         if (req_ctx->updated) {
 977                 ret = hash_resume_state(device_data, &device_data->state);
 978
 979                 if (ret) {
 980                         dev_err(device_data->dev,
 981                                 "%s: hash_resume_state() failed!\n", __func__);
 982                         goto out;
 983                 }
 984         } else if (req->nbytes == 0 && ctx->keylen == 0) {
 985                 u8 zero_hash[SHA256_DIGEST_SIZE];
 986                 u32 zero_hash_size = 0;
 987                 bool zero_digest = false;
 988                 /**
 989                  * Use a pre-calculated empty message digest
 990                  * (workaround since hw return zeroes, hw bug!?)
 991                  */
 992                 ret = get_empty_message_digest(device_data, &zero_hash[0],
 993                                 &zero_hash_size, &zero_digest);
 994                 if (!ret && likely(zero_hash_size == ctx->digestsize) &&
 995                     zero_digest) {
 996                         memcpy(req->result, &zero_hash[0], ctx->digestsize);
 997                         goto out;
 998                 } else if (!ret && !zero_digest) {
 999                         dev_dbg(device_data->dev,
1000                                 "%s: HMAC zero msg with key, continue...\n",
1001                                 __func__);
1002                 } else {
1003                         dev_err(device_data->dev,
1004                                 "%s: ret=%d, or wrong digest size? %s\n",
1005                                 __func__, ret,
1006                                 zero_hash_size == ctx->digestsize ?
1007                                 "true" : "false");
1008                         /* Return error */
1009                         goto out;
1010                 }
1011         } else if (req->nbytes == 0 && ctx->keylen > 0) {
1012                 ret = -EPERM;
1013                 dev_err(device_data->dev, "%s: Empty message with keylength > 0, NOT supported\n",
1014                         __func__);
1015                 goto out;
1016         }
1017
1018         if (!req_ctx->updated) {
1019                 ret = init_hash_hw(device_data, ctx);
1020                 if (ret) {
1021                         dev_err(device_data->dev,
1022                                 "%s: init_hash_hw() failed!\n", __func__);
1023                         goto out;
1024                 }
1025         }
1026
1027         if (req_ctx->state.index) {
1028                 hash_messagepad(device_data, req_ctx->state.buffer,
1029                                 req_ctx->state.index);
1030         } else {
1031                 HASH_SET_DCAL;
1032                 while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
1033                         cpu_relax();
1034         }
1035
1036         if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) {
1037                 unsigned int keylen = ctx->keylen;
1038                 u8 *key = ctx->key;
1039
1040                 dev_dbg(device_data->dev, "%s: keylen: %d\n",
1041                         __func__, ctx->keylen);
1042                 hash_hw_write_key(device_data, key, keylen);
1043         }
1044
1045         hash_get_digest(device_data, digest, ctx->config.algorithm);
1046         memcpy(req->result, digest, ctx->digestsize);
1047
1048 out:
1049         release_hash_device(device_data);
1050
1051         /**
1052          * Allocated in setkey, and only used in HMAC.
1053          */
1054         kfree(ctx->key);
1055
1056         return ret;
1057 }
1058
1059 /**
1060  * hash_hw_update - Updates current HASH computation hashing another part of
1061  *                  the message.
1062  * @req:        Byte array containing the message to be hashed (caller
1063  *              allocated).
1064  */
1065 int hash_hw_update(struct ahash_request *req)
1066 {
1067         int ret = 0;
1068         u8 index = 0;
1069         u8 *buffer;
1070         struct hash_device_data *device_data;
1071         u8 *data_buffer;
1072         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1073         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1074         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1075         struct crypto_hash_walk walk;
1076         int msg_length;
1077
1078         index = req_ctx->state.index;
1079         buffer = (u8 *)req_ctx->state.buffer;
1080
1081         ret = hash_get_device_data(ctx, &device_data);
1082         if (ret)
1083                 return ret;
1084
1085         msg_length = crypto_hash_walk_first(req, &walk);
1086
1087         /* Empty message ("") is correct indata */
1088         if (msg_length == 0) {
1089                 ret = 0;
1090                 goto release_dev;
1091         }
1092
1093         /* Check if ctx->state.length + msg_length
1094            overflows */
1095         if (msg_length > (req_ctx->state.length.low_word + msg_length) &&
1096             HASH_HIGH_WORD_MAX_VAL == req_ctx->state.length.high_word) {
1097                 pr_err("%s: HASH_MSG_LENGTH_OVERFLOW!\n", __func__);
1098                 ret = crypto_hash_walk_done(&walk, -EPERM);
1099                 goto release_dev;
1100         }
1101
1102         /* Main loop */
1103         while (0 != msg_length) {
1104                 data_buffer = walk.data;
1105                 ret = hash_process_data(device_data, ctx, req_ctx, msg_length,
1106                                 data_buffer, buffer, &index);
1107
1108                 if (ret) {
1109                         dev_err(device_data->dev, "%s: hash_internal_hw_update() failed!\n",
1110                                 __func__);
1111                         crypto_hash_walk_done(&walk, ret);
1112                         goto release_dev;
1113                 }
1114
1115                 msg_length = crypto_hash_walk_done(&walk, 0);
1116         }
1117
1118         req_ctx->state.index = index;
1119         dev_dbg(device_data->dev, "%s: indata length=%d, bin=%d\n",
1120                 __func__, req_ctx->state.index, req_ctx->state.bit_index);
1121
1122 release_dev:
1123         release_hash_device(device_data);
1124
1125         return ret;
1126 }
1127
1128 /**
1129  * hash_resume_state - Function that resumes the state of an calculation.
1130  * @device_data:        Pointer to the device structure.
1131  * @device_state:       The state to be restored in the hash hardware
1132  */
1133 int hash_resume_state(struct hash_device_data *device_data,
1134                       const struct hash_state *device_state)
1135 {
1136         u32 temp_cr;
1137         s32 count;
1138         int hash_mode = HASH_OPER_MODE_HASH;
1139
1140         if (NULL == device_state) {
1141                 dev_err(device_data->dev, "%s: HASH_INVALID_PARAMETER!\n",
1142                         __func__);
1143                 return -EPERM;
1144         }
1145
1146         /* Check correctness of index and length members */
1147         if (device_state->index > HASH_BLOCK_SIZE ||
1148             (device_state->length.low_word % HASH_BLOCK_SIZE) != 0) {
1149                 dev_err(device_data->dev, "%s: HASH_INVALID_PARAMETER!\n",
1150                         __func__);
1151                 return -EPERM;
1152         }
1153
1154         /*
1155          * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
1156          * prepare the initialize the HASH accelerator to compute the message
1157          * digest of a new message.
1158          */
1159         HASH_INITIALIZE;
1160
1161         temp_cr = device_state->temp_cr;
1162         writel_relaxed(temp_cr & HASH_CR_RESUME_MASK, &device_data->base->cr);
1163
1164         if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK)
1165                 hash_mode = HASH_OPER_MODE_HMAC;
1166         else
1167                 hash_mode = HASH_OPER_MODE_HASH;
1168
1169         for (count = 0; count < HASH_CSR_COUNT; count++) {
1170                 if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
1171                         break;
1172
1173                 writel_relaxed(device_state->csr[count],
1174                                &device_data->base->csrx[count]);
1175         }
1176
1177         writel_relaxed(device_state->csfull, &device_data->base->csfull);
1178         writel_relaxed(device_state->csdatain, &device_data->base->csdatain);
1179
1180         writel_relaxed(device_state->str_reg, &device_data->base->str);
1181         writel_relaxed(temp_cr, &device_data->base->cr);
1182
1183         return 0;
1184 }
1185
1186 /**
1187  * hash_save_state - Function that saves the state of hardware.
1188  * @device_data:        Pointer to the device structure.
1189  * @device_state:       The strucure where the hardware state should be saved.
1190  */
1191 int hash_save_state(struct hash_device_data *device_data,
1192                     struct hash_state *device_state)
1193 {
1194         u32 temp_cr;
1195         u32 count;
1196         int hash_mode = HASH_OPER_MODE_HASH;
1197
1198         if (NULL == device_state) {
1199                 dev_err(device_data->dev, "%s: HASH_INVALID_PARAMETER!\n",
1200                         __func__);
1201                 return -ENOTSUPP;
1202         }
1203
1204         /* Write dummy value to force digest intermediate calculation. This
1205          * actually makes sure that there isn't any ongoing calculation in the
1206          * hardware.
1207          */
1208         while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
1209                 cpu_relax();
1210
1211         temp_cr = readl_relaxed(&device_data->base->cr);
1212
1213         device_state->str_reg = readl_relaxed(&device_data->base->str);
1214
1215         device_state->din_reg = readl_relaxed(&device_data->base->din);
1216
1217         if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK)
1218                 hash_mode = HASH_OPER_MODE_HMAC;
1219         else
1220                 hash_mode = HASH_OPER_MODE_HASH;
1221
1222         for (count = 0; count < HASH_CSR_COUNT; count++) {
1223                 if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
1224                         break;
1225
1226                 device_state->csr[count] =
1227                         readl_relaxed(&device_data->base->csrx[count]);
1228         }
1229
1230         device_state->csfull = readl_relaxed(&device_data->base->csfull);
1231         device_state->csdatain = readl_relaxed(&device_data->base->csdatain);
1232
1233         device_state->temp_cr = temp_cr;
1234
1235         return 0;
1236 }
1237
1238 /**
1239  * hash_check_hw - This routine checks for peripheral Ids and PCell Ids.
1240  * @device_data:
1241  *
1242  */
1243 int hash_check_hw(struct hash_device_data *device_data)
1244 {
1245         /* Checking Peripheral Ids  */
1246         if (HASH_P_ID0 == readl_relaxed(&device_data->base->periphid0) &&
1247             HASH_P_ID1 == readl_relaxed(&device_data->base->periphid1) &&
1248             HASH_P_ID2 == readl_relaxed(&device_data->base->periphid2) &&
1249             HASH_P_ID3 == readl_relaxed(&device_data->base->periphid3) &&
1250             HASH_CELL_ID0 == readl_relaxed(&device_data->base->cellid0) &&
1251             HASH_CELL_ID1 == readl_relaxed(&device_data->base->cellid1) &&
1252             HASH_CELL_ID2 == readl_relaxed(&device_data->base->cellid2) &&
1253             HASH_CELL_ID3 == readl_relaxed(&device_data->base->cellid3)) {
1254                 return 0;
1255         }
1256
1257         dev_err(device_data->dev, "%s: HASH_UNSUPPORTED_HW!\n", __func__);
1258         return -ENOTSUPP;
1259 }
1260
1261 /**
1262  * hash_get_digest - Gets the digest.
1263  * @device_data:        Pointer to the device structure.
1264  * @digest:             User allocated byte array for the calculated digest.
1265  * @algorithm:          The algorithm in use.
1266  */
1267 void hash_get_digest(struct hash_device_data *device_data,
1268                      u8 *digest, int algorithm)
1269 {
1270         u32 temp_hx_val, count;
1271         int loop_ctr;
1272
1273         if (algorithm != HASH_ALGO_SHA1 && algorithm != HASH_ALGO_SHA256) {
1274                 dev_err(device_data->dev, "%s: Incorrect algorithm %d\n",
1275                         __func__, algorithm);
1276                 return;
1277         }
1278
1279         if (algorithm == HASH_ALGO_SHA1)
1280                 loop_ctr = SHA1_DIGEST_SIZE / sizeof(u32);
1281         else
1282                 loop_ctr = SHA256_DIGEST_SIZE / sizeof(u32);
1283
1284         dev_dbg(device_data->dev, "%s: digest array:(0x%lx)\n",
1285                 __func__, (unsigned long)digest);
1286
1287         /* Copy result into digest array */
1288         for (count = 0; count < loop_ctr; count++) {
1289                 temp_hx_val = readl_relaxed(&device_data->base->hx[count]);
1290                 digest[count * 4] = (u8) ((temp_hx_val >> 24) & 0xFF);
1291                 digest[count * 4 + 1] = (u8) ((temp_hx_val >> 16) & 0xFF);
1292                 digest[count * 4 + 2] = (u8) ((temp_hx_val >> 8) & 0xFF);
1293                 digest[count * 4 + 3] = (u8) ((temp_hx_val >> 0) & 0xFF);
1294         }
1295 }
1296
1297 /**
1298  * hash_update - The hash update function for SHA1/SHA2 (SHA256).
1299  * @req: The hash request for the job.
1300  */
1301 static int ahash_update(struct ahash_request *req)
1302 {
1303         int ret = 0;
1304         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1305
1306         if (hash_mode != HASH_MODE_DMA || !req_ctx->dma_mode)
1307                 ret = hash_hw_update(req);
1308         /* Skip update for DMA, all data will be passed to DMA in final */
1309
1310         if (ret) {
1311                 pr_err("%s: hash_hw_update() failed!\n", __func__);
1312         }
1313
1314         return ret;
1315 }
1316
1317 /**
1318  * hash_final - The hash final function for SHA1/SHA2 (SHA256).
1319  * @req:        The hash request for the job.
1320  */
1321 static int ahash_final(struct ahash_request *req)
1322 {
1323         int ret = 0;
1324         struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
1325
1326         pr_debug("%s: data size: %d\n", __func__, req->nbytes);
1327
1328         if ((hash_mode == HASH_MODE_DMA) && req_ctx->dma_mode)
1329                 ret = hash_dma_final(req);
1330         else
1331                 ret = hash_hw_final(req);
1332
1333         if (ret) {
1334                 pr_err("%s: hash_hw/dma_final() failed\n", __func__);
1335         }
1336
1337         return ret;
1338 }
1339
1340 static int hash_setkey(struct crypto_ahash *tfm,
1341                        const u8 *key, unsigned int keylen, int alg)
1342 {
1343         int ret = 0;
1344         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1345
1346         /**
1347          * Freed in final.
1348          */
1349         ctx->key = kmemdup(key, keylen, GFP_KERNEL);
1350         if (!ctx->key) {
1351                 pr_err("%s: Failed to allocate ctx->key for %d\n",
1352                        __func__, alg);
1353                 return -ENOMEM;
1354         }
1355         ctx->keylen = keylen;
1356
1357         return ret;
1358 }
1359
1360 static int ahash_sha1_init(struct ahash_request *req)
1361 {
1362         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1363         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1364
1365         ctx->config.data_format = HASH_DATA_8_BITS;
1366         ctx->config.algorithm = HASH_ALGO_SHA1;
1367         ctx->config.oper_mode = HASH_OPER_MODE_HASH;
1368         ctx->digestsize = SHA1_DIGEST_SIZE;
1369
1370         return ux500_hash_init(req);
1371 }
1372
1373 static int ahash_sha256_init(struct ahash_request *req)
1374 {
1375         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1376         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1377
1378         ctx->config.data_format = HASH_DATA_8_BITS;
1379         ctx->config.algorithm = HASH_ALGO_SHA256;
1380         ctx->config.oper_mode = HASH_OPER_MODE_HASH;
1381         ctx->digestsize = SHA256_DIGEST_SIZE;
1382
1383         return ux500_hash_init(req);
1384 }
1385
1386 static int ahash_sha1_digest(struct ahash_request *req)
1387 {
1388         int ret2, ret1;
1389
1390         ret1 = ahash_sha1_init(req);
1391         if (ret1)
1392                 goto out;
1393
1394         ret1 = ahash_update(req);
1395         ret2 = ahash_final(req);
1396
1397 out:
1398         return ret1 ? ret1 : ret2;
1399 }
1400
1401 static int ahash_sha256_digest(struct ahash_request *req)
1402 {
1403         int ret2, ret1;
1404
1405         ret1 = ahash_sha256_init(req);
1406         if (ret1)
1407                 goto out;
1408
1409         ret1 = ahash_update(req);
1410         ret2 = ahash_final(req);
1411
1412 out:
1413         return ret1 ? ret1 : ret2;
1414 }
1415
1416 static int ahash_noimport(struct ahash_request *req, const void *in)
1417 {
1418         return -ENOSYS;
1419 }
1420
1421 static int ahash_noexport(struct ahash_request *req, void *out)
1422 {
1423         return -ENOSYS;
1424 }
1425
1426 static int hmac_sha1_init(struct ahash_request *req)
1427 {
1428         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1429         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1430
1431         ctx->config.data_format = HASH_DATA_8_BITS;
1432         ctx->config.algorithm   = HASH_ALGO_SHA1;
1433         ctx->config.oper_mode   = HASH_OPER_MODE_HMAC;
1434         ctx->digestsize         = SHA1_DIGEST_SIZE;
1435
1436         return ux500_hash_init(req);
1437 }
1438
1439 static int hmac_sha256_init(struct ahash_request *req)
1440 {
1441         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
1442         struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
1443
1444         ctx->config.data_format = HASH_DATA_8_BITS;
1445         ctx->config.algorithm   = HASH_ALGO_SHA256;
1446         ctx->config.oper_mode   = HASH_OPER_MODE_HMAC;
1447         ctx->digestsize         = SHA256_DIGEST_SIZE;
1448
1449         return ux500_hash_init(req);
1450 }
1451
1452 static int hmac_sha1_digest(struct ahash_request *req)
1453 {
1454         int ret2, ret1;
1455
1456         ret1 = hmac_sha1_init(req);
1457         if (ret1)
1458                 goto out;
1459
1460         ret1 = ahash_update(req);
1461         ret2 = ahash_final(req);
1462
1463 out:
1464         return ret1 ? ret1 : ret2;
1465 }
1466
1467 static int hmac_sha256_digest(struct ahash_request *req)
1468 {
1469         int ret2, ret1;
1470
1471         ret1 = hmac_sha256_init(req);
1472         if (ret1)
1473                 goto out;
1474
1475         ret1 = ahash_update(req);
1476         ret2 = ahash_final(req);
1477
1478 out:
1479         return ret1 ? ret1 : ret2;
1480 }
1481
1482 static int hmac_sha1_setkey(struct crypto_ahash *tfm,
1483                             const u8 *key, unsigned int keylen)
1484 {
1485         return hash_setkey(tfm, key, keylen, HASH_ALGO_SHA1);
1486 }
1487
1488 static int hmac_sha256_setkey(struct crypto_ahash *tfm,
1489                               const u8 *key, unsigned int keylen)
1490 {
1491         return hash_setkey(tfm, key, keylen, HASH_ALGO_SHA256);
1492 }
1493
1494 struct hash_algo_template {
1495         struct hash_config conf;
1496         struct ahash_alg hash;
1497 };
1498
1499 static int hash_cra_init(struct crypto_tfm *tfm)
1500 {
1501         struct hash_ctx *ctx = crypto_tfm_ctx(tfm);
1502         struct crypto_alg *alg = tfm->__crt_alg;
1503         struct hash_algo_template *hash_alg;
1504
1505         hash_alg = container_of(__crypto_ahash_alg(alg),
1506                         struct hash_algo_template,
1507                         hash);
1508
1509         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1510                                  sizeof(struct hash_req_ctx));
1511
1512         ctx->config.data_format = HASH_DATA_8_BITS;
1513         ctx->config.algorithm = hash_alg->conf.algorithm;
1514         ctx->config.oper_mode = hash_alg->conf.oper_mode;
1515
1516         ctx->digestsize = hash_alg->hash.halg.digestsize;
1517
1518         return 0;
1519 }
1520
1521 static struct hash_algo_template hash_algs[] = {
1522         {
1523                 .conf.algorithm = HASH_ALGO_SHA1,
1524                 .conf.oper_mode = HASH_OPER_MODE_HASH,
1525                 .hash = {
1526                         .init = ux500_hash_init,
1527                         .update = ahash_update,
1528                         .final = ahash_final,
1529                         .digest = ahash_sha1_digest,
1530                         .export = ahash_noexport,
1531                         .import = ahash_noimport,
1532                         .halg.digestsize = SHA1_DIGEST_SIZE,
1533                         .halg.statesize = sizeof(struct hash_ctx),
1534                         .halg.base = {
1535                                 .cra_name = "sha1",
1536                                 .cra_driver_name = "sha1-ux500",
1537                                 .cra_flags = CRYPTO_ALG_ASYNC,
1538                                 .cra_blocksize = SHA1_BLOCK_SIZE,
1539                                 .cra_ctxsize = sizeof(struct hash_ctx),
1540                                 .cra_init = hash_cra_init,
1541                                 .cra_module = THIS_MODULE,
1542                         }
1543                 }
1544         },
1545         {
1546                 .conf.algorithm = HASH_ALGO_SHA256,
1547                 .conf.oper_mode = HASH_OPER_MODE_HASH,
1548                 .hash = {
1549                         .init = ux500_hash_init,
1550                         .update = ahash_update,
1551                         .final = ahash_final,
1552                         .digest = ahash_sha256_digest,
1553                         .export = ahash_noexport,
1554                         .import = ahash_noimport,
1555                         .halg.digestsize = SHA256_DIGEST_SIZE,
1556                         .halg.statesize = sizeof(struct hash_ctx),
1557                         .halg.base = {
1558                                 .cra_name = "sha256",
1559                                 .cra_driver_name = "sha256-ux500",
1560                                 .cra_flags = CRYPTO_ALG_ASYNC,
1561                                 .cra_blocksize = SHA256_BLOCK_SIZE,
1562                                 .cra_ctxsize = sizeof(struct hash_ctx),
1563                                 .cra_init = hash_cra_init,
1564                                 .cra_module = THIS_MODULE,
1565                         }
1566                 }
1567         },
1568         {
1569                 .conf.algorithm = HASH_ALGO_SHA1,
1570                 .conf.oper_mode = HASH_OPER_MODE_HMAC,
1571                         .hash = {
1572                         .init = ux500_hash_init,
1573                         .update = ahash_update,
1574                         .final = ahash_final,
1575                         .digest = hmac_sha1_digest,
1576                         .setkey = hmac_sha1_setkey,
1577                         .export = ahash_noexport,
1578                         .import = ahash_noimport,
1579                         .halg.digestsize = SHA1_DIGEST_SIZE,
1580                         .halg.statesize = sizeof(struct hash_ctx),
1581                         .halg.base = {
1582                                 .cra_name = "hmac(sha1)",
1583                                 .cra_driver_name = "hmac-sha1-ux500",
1584                                 .cra_flags = CRYPTO_ALG_ASYNC,
1585                                 .cra_blocksize = SHA1_BLOCK_SIZE,
1586                                 .cra_ctxsize = sizeof(struct hash_ctx),
1587                                 .cra_init = hash_cra_init,
1588                                 .cra_module = THIS_MODULE,
1589                         }
1590                 }
1591         },
1592         {
1593                 .conf.algorithm = HASH_ALGO_SHA256,
1594                 .conf.oper_mode = HASH_OPER_MODE_HMAC,
1595                 .hash = {
1596                         .init = ux500_hash_init,
1597                         .update = ahash_update,
1598                         .final = ahash_final,
1599                         .digest = hmac_sha256_digest,
1600                         .setkey = hmac_sha256_setkey,
1601                         .export = ahash_noexport,
1602                         .import = ahash_noimport,
1603                         .halg.digestsize = SHA256_DIGEST_SIZE,
1604                         .halg.statesize = sizeof(struct hash_ctx),
1605                         .halg.base = {
1606                                 .cra_name = "hmac(sha256)",
1607                                 .cra_driver_name = "hmac-sha256-ux500",
1608                                 .cra_flags = CRYPTO_ALG_ASYNC,
1609                                 .cra_blocksize = SHA256_BLOCK_SIZE,
1610                                 .cra_ctxsize = sizeof(struct hash_ctx),
1611                                 .cra_init = hash_cra_init,
1612                                 .cra_module = THIS_MODULE,
1613                         }
1614                 }
1615         }
1616 };
1617
1618 /**
1619  * hash_algs_register_all -
1620  */
1621 static int ahash_algs_register_all(struct hash_device_data *device_data)
1622 {
1623         int ret;
1624         int i;
1625         int count;
1626
1627         for (i = 0; i < ARRAY_SIZE(hash_algs); i++) {
1628                 ret = crypto_register_ahash(&hash_algs[i].hash);
1629                 if (ret) {
1630                         count = i;
1631                         dev_err(device_data->dev, "%s: alg registration failed\n",
1632                                 hash_algs[i].hash.halg.base.cra_driver_name);
1633                         goto unreg;
1634                 }
1635         }
1636         return 0;
1637 unreg:
1638         for (i = 0; i < count; i++)
1639                 crypto_unregister_ahash(&hash_algs[i].hash);
1640         return ret;
1641 }
1642
1643 /**
1644  * hash_algs_unregister_all -
1645  */
1646 static void ahash_algs_unregister_all(struct hash_device_data *device_data)
1647 {
1648         int i;
1649
1650         for (i = 0; i < ARRAY_SIZE(hash_algs); i++)
1651                 crypto_unregister_ahash(&hash_algs[i].hash);
1652 }
1653
1654 /**
1655  * ux500_hash_probe - Function that probes the hash hardware.
1656  * @pdev: The platform device.
1657  */
1658 static int ux500_hash_probe(struct platform_device *pdev)
1659 {
1660         int                     ret = 0;
1661         struct resource         *res = NULL;
1662         struct hash_device_data *device_data;
1663         struct device           *dev = &pdev->dev;
1664
1665         device_data = devm_kzalloc(dev, sizeof(*device_data), GFP_ATOMIC);
1666         if (!device_data) {
1667                 ret = -ENOMEM;
1668                 goto out;
1669         }
1670
1671         device_data->dev = dev;
1672         device_data->current_ctx = NULL;
1673
1674         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1675         if (!res) {
1676                 dev_dbg(dev, "%s: platform_get_resource() failed!\n", __func__);
1677                 ret = -ENODEV;
1678                 goto out;
1679         }
1680
1681         device_data->phybase = res->start;
1682         device_data->base = devm_ioremap_resource(dev, res);
1683         if (IS_ERR(device_data->base)) {
1684                 dev_err(dev, "%s: ioremap() failed!\n", __func__);
1685                 ret = PTR_ERR(device_data->base);
1686                 goto out;
1687         }
1688         spin_lock_init(&device_data->ctx_lock);
1689         spin_lock_init(&device_data->power_state_lock);
1690
1691         /* Enable power for HASH1 hardware block */
1692         device_data->regulator = regulator_get(dev, "v-ape");
1693         if (IS_ERR(device_data->regulator)) {
1694                 dev_err(dev, "%s: regulator_get() failed!\n", __func__);
1695                 ret = PTR_ERR(device_data->regulator);
1696                 device_data->regulator = NULL;
1697                 goto out;
1698         }
1699
1700         /* Enable the clock for HASH1 hardware block */
1701         device_data->clk = devm_clk_get(dev, NULL);
1702         if (IS_ERR(device_data->clk)) {
1703                 dev_err(dev, "%s: clk_get() failed!\n", __func__);
1704                 ret = PTR_ERR(device_data->clk);
1705                 goto out_regulator;
1706         }
1707
1708         ret = clk_prepare(device_data->clk);
1709         if (ret) {
1710                 dev_err(dev, "%s: clk_prepare() failed!\n", __func__);
1711                 goto out_regulator;
1712         }
1713
1714         /* Enable device power (and clock) */
1715         ret = hash_enable_power(device_data, false);
1716         if (ret) {
1717                 dev_err(dev, "%s: hash_enable_power() failed!\n", __func__);
1718                 goto out_clk_unprepare;
1719         }
1720
1721         ret = hash_check_hw(device_data);
1722         if (ret) {
1723                 dev_err(dev, "%s: hash_check_hw() failed!\n", __func__);
1724                 goto out_power;
1725         }
1726
1727         if (hash_mode == HASH_MODE_DMA)
1728                 hash_dma_setup_channel(device_data, dev);
1729
1730         platform_set_drvdata(pdev, device_data);
1731
1732         /* Put the new device into the device list... */
1733         klist_add_tail(&device_data->list_node, &driver_data.device_list);
1734         /* ... and signal that a new device is available. */
1735         up(&driver_data.device_allocation);
1736
1737         ret = ahash_algs_register_all(device_data);
1738         if (ret) {
1739                 dev_err(dev, "%s: ahash_algs_register_all() failed!\n",
1740                         __func__);
1741                 goto out_power;
1742         }
1743
1744         dev_info(dev, "successfully registered\n");
1745         return 0;
1746
1747 out_power:
1748         hash_disable_power(device_data, false);
1749
1750 out_clk_unprepare:
1751         clk_unprepare(device_data->clk);
1752
1753 out_regulator:
1754         regulator_put(device_data->regulator);
1755
1756 out:
1757         return ret;
1758 }
1759
1760 /**
1761  * ux500_hash_remove - Function that removes the hash device from the platform.
1762  * @pdev: The platform device.
1763  */
1764 static int ux500_hash_remove(struct platform_device *pdev)
1765 {
1766         struct hash_device_data *device_data;
1767         struct device           *dev = &pdev->dev;
1768
1769         device_data = platform_get_drvdata(pdev);
1770         if (!device_data) {
1771                 dev_err(dev, "%s: platform_get_drvdata() failed!\n", __func__);
1772                 return -ENOMEM;
1773         }
1774
1775         /* Try to decrease the number of available devices. */
1776         if (down_trylock(&driver_data.device_allocation))
1777                 return -EBUSY;
1778
1779         /* Check that the device is free */
1780         spin_lock(&device_data->ctx_lock);
1781         /* current_ctx allocates a device, NULL = unallocated */
1782         if (device_data->current_ctx) {
1783                 /* The device is busy */
1784                 spin_unlock(&device_data->ctx_lock);
1785                 /* Return the device to the pool. */
1786                 up(&driver_data.device_allocation);
1787                 return -EBUSY;
1788         }
1789
1790         spin_unlock(&device_data->ctx_lock);
1791
1792         /* Remove the device from the list */
1793         if (klist_node_attached(&device_data->list_node))
1794                 klist_remove(&device_data->list_node);
1795
1796         /* If this was the last device, remove the services */
1797         if (list_empty(&driver_data.device_list.k_list))
1798                 ahash_algs_unregister_all(device_data);
1799
1800         if (hash_disable_power(device_data, false))
1801                 dev_err(dev, "%s: hash_disable_power() failed\n",
1802                         __func__);
1803
1804         clk_unprepare(device_data->clk);
1805         regulator_put(device_data->regulator);
1806
1807         return 0;
1808 }
1809
1810 /**
1811  * ux500_hash_shutdown - Function that shutdown the hash device.
1812  * @pdev: The platform device
1813  */
1814 static void ux500_hash_shutdown(struct platform_device *pdev)
1815 {
1816         struct hash_device_data *device_data;
1817
1818         device_data = platform_get_drvdata(pdev);
1819         if (!device_data) {
1820                 dev_err(&pdev->dev, "%s: platform_get_drvdata() failed!\n",
1821                         __func__);
1822                 return;
1823         }
1824
1825         /* Check that the device is free */
1826         spin_lock(&device_data->ctx_lock);
1827         /* current_ctx allocates a device, NULL = unallocated */
1828         if (!device_data->current_ctx) {
1829                 if (down_trylock(&driver_data.device_allocation))
1830                         dev_dbg(&pdev->dev, "%s: Cryp still in use! Shutting down anyway...\n",
1831                                 __func__);
1832                 /**
1833                  * (Allocate the device)
1834                  * Need to set this to non-null (dummy) value,
1835                  * to avoid usage if context switching.
1836                  */
1837                 device_data->current_ctx++;
1838         }
1839         spin_unlock(&device_data->ctx_lock);
1840
1841         /* Remove the device from the list */
1842         if (klist_node_attached(&device_data->list_node))
1843                 klist_remove(&device_data->list_node);
1844
1845         /* If this was the last device, remove the services */
1846         if (list_empty(&driver_data.device_list.k_list))
1847                 ahash_algs_unregister_all(device_data);
1848
1849         if (hash_disable_power(device_data, false))
1850                 dev_err(&pdev->dev, "%s: hash_disable_power() failed\n",
1851                         __func__);
1852 }
1853
1854 #ifdef CONFIG_PM_SLEEP
1855 /**
1856  * ux500_hash_suspend - Function that suspends the hash device.
1857  * @dev:        Device to suspend.
1858  */
1859 static int ux500_hash_suspend(struct device *dev)
1860 {
1861         int ret;
1862         struct hash_device_data *device_data;
1863         struct hash_ctx *temp_ctx = NULL;
1864
1865         device_data = dev_get_drvdata(dev);
1866         if (!device_data) {
1867                 dev_err(dev, "%s: platform_get_drvdata() failed!\n", __func__);
1868                 return -ENOMEM;
1869         }
1870
1871         spin_lock(&device_data->ctx_lock);
1872         if (!device_data->current_ctx)
1873                 device_data->current_ctx++;
1874         spin_unlock(&device_data->ctx_lock);
1875
1876         if (device_data->current_ctx == ++temp_ctx) {
1877                 if (down_interruptible(&driver_data.device_allocation))
1878                         dev_dbg(dev, "%s: down_interruptible() failed\n",
1879                                 __func__);
1880                 ret = hash_disable_power(device_data, false);
1881
1882         } else {
1883                 ret = hash_disable_power(device_data, true);
1884         }
1885
1886         if (ret)
1887                 dev_err(dev, "%s: hash_disable_power()\n", __func__);
1888
1889         return ret;
1890 }
1891
1892 /**
1893  * ux500_hash_resume - Function that resume the hash device.
1894  * @dev:        Device to resume.
1895  */
1896 static int ux500_hash_resume(struct device *dev)
1897 {
1898         int ret = 0;
1899         struct hash_device_data *device_data;
1900         struct hash_ctx *temp_ctx = NULL;
1901
1902         device_data = dev_get_drvdata(dev);
1903         if (!device_data) {
1904                 dev_err(dev, "%s: platform_get_drvdata() failed!\n", __func__);
1905                 return -ENOMEM;
1906         }
1907
1908         spin_lock(&device_data->ctx_lock);
1909         if (device_data->current_ctx == ++temp_ctx)
1910                 device_data->current_ctx = NULL;
1911         spin_unlock(&device_data->ctx_lock);
1912
1913         if (!device_data->current_ctx)
1914                 up(&driver_data.device_allocation);
1915         else
1916                 ret = hash_enable_power(device_data, true);
1917
1918         if (ret)
1919                 dev_err(dev, "%s: hash_enable_power() failed!\n", __func__);
1920
1921         return ret;
1922 }
1923 #endif
1924
1925 static SIMPLE_DEV_PM_OPS(ux500_hash_pm, ux500_hash_suspend, ux500_hash_resume);
1926
1927 static const struct of_device_id ux500_hash_match[] = {
1928         { .compatible = "stericsson,ux500-hash" },
1929         { },
1930 };
1931 MODULE_DEVICE_TABLE(of, ux500_hash_match);
1932
1933 static struct platform_driver hash_driver = {
1934         .probe  = ux500_hash_probe,
1935         .remove = ux500_hash_remove,
1936         .shutdown = ux500_hash_shutdown,
1937         .driver = {
1938                 .name  = "hash1",
1939                 .of_match_table = ux500_hash_match,
1940                 .pm    = &ux500_hash_pm,
1941         }
1942 };
1943
1944 /**
1945  * ux500_hash_mod_init - The kernel module init function.
1946  */
1947 static int __init ux500_hash_mod_init(void)
1948 {
1949         klist_init(&driver_data.device_list, NULL, NULL);
1950         /* Initialize the semaphore to 0 devices (locked state) */
1951         sema_init(&driver_data.device_allocation, 0);
1952
1953         return platform_driver_register(&hash_driver);
1954 }
1955
1956 /**
1957  * ux500_hash_mod_fini - The kernel module exit function.
1958  */
1959 static void __exit ux500_hash_mod_fini(void)
1960 {
1961         platform_driver_unregister(&hash_driver);
1962 }
1963
1964 module_init(ux500_hash_mod_init);
1965 module_exit(ux500_hash_mod_fini);
1966
1967 MODULE_DESCRIPTION("Driver for ST-Ericsson UX500 HASH engine.");
1968 MODULE_LICENSE("GPL");
1969
1970 MODULE_ALIAS_CRYPTO("sha1-all");
1971 MODULE_ALIAS_CRYPTO("sha256-all");
1972 MODULE_ALIAS_CRYPTO("hmac-sha1-all");
1973 MODULE_ALIAS_CRYPTO("hmac-sha256-all");