2 * Copyright (C) STMicroelectronics SA 2017
3 * Author: Fabien Dessenne <fabien.dessenne@st.com>
4 * License terms: GNU General Public License (GPL), version 2
7 #include <linux/bitrev.h>
9 #include <linux/crc32poly.h>
10 #include <linux/module.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
15 #include <crypto/internal/hash.h>
17 #include <asm/unaligned.h>
19 #define DRIVER_NAME "stm32-crc32"
20 #define CHKSUM_DIGEST_SIZE 4
21 #define CHKSUM_BLOCK_SIZE 1
24 #define CRC_DR 0x00000000
25 #define CRC_CR 0x00000008
26 #define CRC_INIT 0x00000010
27 #define CRC_POL 0x00000014
29 /* Registers values */
30 #define CRC_CR_RESET BIT(0)
31 #define CRC_CR_REV_IN_WORD (BIT(6) | BIT(5))
32 #define CRC_CR_REV_IN_BYTE BIT(5)
33 #define CRC_CR_REV_OUT BIT(7)
34 #define CRC32C_INIT_DEFAULT 0xFFFFFFFF
36 #define CRC_AUTOSUSPEND_DELAY 50
39 struct list_head list;
45 struct stm32_crc_list {
46 struct list_head dev_list;
47 spinlock_t lock; /* protect dev_list */
50 static struct stm32_crc_list crc_list = {
51 .dev_list = LIST_HEAD_INIT(crc_list.dev_list),
52 .lock = __SPIN_LOCK_UNLOCKED(crc_list.lock),
55 struct stm32_crc_ctx {
60 struct stm32_crc_desc_ctx {
61 u32 partial; /* crc32c: partial in first 4 bytes of that struct */
64 static int stm32_crc32_cra_init(struct crypto_tfm *tfm)
66 struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
69 mctx->poly = CRC32_POLY_LE;
73 static int stm32_crc32c_cra_init(struct crypto_tfm *tfm)
75 struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
77 mctx->key = CRC32C_INIT_DEFAULT;
78 mctx->poly = CRC32C_POLY_LE;
82 static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key,
85 struct stm32_crc_ctx *mctx = crypto_shash_ctx(tfm);
87 if (keylen != sizeof(u32)) {
88 crypto_shash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
92 mctx->key = get_unaligned_le32(key);
96 static struct stm32_crc *stm32_crc_get_next_crc(void)
98 struct stm32_crc *crc;
100 spin_lock_bh(&crc_list.lock);
101 crc = list_first_entry(&crc_list.dev_list, struct stm32_crc, list);
103 list_move_tail(&crc->list, &crc_list.dev_list);
104 spin_unlock_bh(&crc_list.lock);
109 static int stm32_crc_init(struct shash_desc *desc)
111 struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
112 struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
113 struct stm32_crc *crc;
115 crc = stm32_crc_get_next_crc();
119 pm_runtime_get_sync(crc->dev);
121 /* Reset, set key, poly and configure in bit reverse mode */
122 writel_relaxed(bitrev32(mctx->key), crc->regs + CRC_INIT);
123 writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
124 writel_relaxed(CRC_CR_RESET | CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
127 /* Store partial result */
128 ctx->partial = readl_relaxed(crc->regs + CRC_DR);
130 pm_runtime_mark_last_busy(crc->dev);
131 pm_runtime_put_autosuspend(crc->dev);
136 static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
139 struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
140 struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
141 struct stm32_crc *crc;
143 crc = stm32_crc_get_next_crc();
147 pm_runtime_get_sync(crc->dev);
150 * Restore previously calculated CRC for this context as init value
151 * Restore polynomial configuration
152 * Configure in register for word input data,
153 * Configure out register in reversed bit mode data.
155 writel_relaxed(bitrev32(ctx->partial), crc->regs + CRC_INIT);
156 writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
157 writel_relaxed(CRC_CR_RESET | CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
160 if (d8 != PTR_ALIGN(d8, sizeof(u32))) {
161 /* Configure for byte data */
162 writel_relaxed(CRC_CR_REV_IN_BYTE | CRC_CR_REV_OUT,
164 while (d8 != PTR_ALIGN(d8, sizeof(u32)) && length) {
165 writeb_relaxed(*d8++, crc->regs + CRC_DR);
168 /* Configure for word data */
169 writel_relaxed(CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
173 for (; length >= sizeof(u32); d8 += sizeof(u32), length -= sizeof(u32))
174 writel_relaxed(*((u32 *)d8), crc->regs + CRC_DR);
177 /* Configure for byte data */
178 writel_relaxed(CRC_CR_REV_IN_BYTE | CRC_CR_REV_OUT,
181 writeb_relaxed(*d8++, crc->regs + CRC_DR);
184 /* Store partial result */
185 ctx->partial = readl_relaxed(crc->regs + CRC_DR);
187 pm_runtime_mark_last_busy(crc->dev);
188 pm_runtime_put_autosuspend(crc->dev);
193 static int stm32_crc_final(struct shash_desc *desc, u8 *out)
195 struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
196 struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
198 /* Send computed CRC */
199 put_unaligned_le32(mctx->poly == CRC32C_POLY_LE ?
200 ~ctx->partial : ctx->partial, out);
205 static int stm32_crc_finup(struct shash_desc *desc, const u8 *data,
206 unsigned int length, u8 *out)
208 return stm32_crc_update(desc, data, length) ?:
209 stm32_crc_final(desc, out);
212 static int stm32_crc_digest(struct shash_desc *desc, const u8 *data,
213 unsigned int length, u8 *out)
215 return stm32_crc_init(desc) ?: stm32_crc_finup(desc, data, length, out);
218 static unsigned int refcnt;
219 static DEFINE_MUTEX(refcnt_lock);
220 static struct shash_alg algs[] = {
223 .setkey = stm32_crc_setkey,
224 .init = stm32_crc_init,
225 .update = stm32_crc_update,
226 .final = stm32_crc_final,
227 .finup = stm32_crc_finup,
228 .digest = stm32_crc_digest,
229 .descsize = sizeof(struct stm32_crc_desc_ctx),
230 .digestsize = CHKSUM_DIGEST_SIZE,
233 .cra_driver_name = "stm32-crc32-crc32",
235 .cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
236 .cra_blocksize = CHKSUM_BLOCK_SIZE,
238 .cra_ctxsize = sizeof(struct stm32_crc_ctx),
239 .cra_module = THIS_MODULE,
240 .cra_init = stm32_crc32_cra_init,
243 /* CRC-32Castagnoli */
245 .setkey = stm32_crc_setkey,
246 .init = stm32_crc_init,
247 .update = stm32_crc_update,
248 .final = stm32_crc_final,
249 .finup = stm32_crc_finup,
250 .digest = stm32_crc_digest,
251 .descsize = sizeof(struct stm32_crc_desc_ctx),
252 .digestsize = CHKSUM_DIGEST_SIZE,
254 .cra_name = "crc32c",
255 .cra_driver_name = "stm32-crc32-crc32c",
257 .cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
258 .cra_blocksize = CHKSUM_BLOCK_SIZE,
260 .cra_ctxsize = sizeof(struct stm32_crc_ctx),
261 .cra_module = THIS_MODULE,
262 .cra_init = stm32_crc32c_cra_init,
267 static int stm32_crc_probe(struct platform_device *pdev)
269 struct device *dev = &pdev->dev;
270 struct stm32_crc *crc;
271 struct resource *res;
274 crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
280 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
281 crc->regs = devm_ioremap_resource(dev, res);
282 if (IS_ERR(crc->regs)) {
283 dev_err(dev, "Cannot map CRC IO\n");
284 return PTR_ERR(crc->regs);
287 crc->clk = devm_clk_get(dev, NULL);
288 if (IS_ERR(crc->clk)) {
289 dev_err(dev, "Could not get clock\n");
290 return PTR_ERR(crc->clk);
293 ret = clk_prepare_enable(crc->clk);
295 dev_err(crc->dev, "Failed to enable clock\n");
299 pm_runtime_set_autosuspend_delay(dev, CRC_AUTOSUSPEND_DELAY);
300 pm_runtime_use_autosuspend(dev);
302 pm_runtime_get_noresume(dev);
303 pm_runtime_set_active(dev);
304 pm_runtime_enable(dev);
306 platform_set_drvdata(pdev, crc);
308 spin_lock(&crc_list.lock);
309 list_add(&crc->list, &crc_list.dev_list);
310 spin_unlock(&crc_list.lock);
312 mutex_lock(&refcnt_lock);
314 ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
316 mutex_unlock(&refcnt_lock);
317 dev_err(dev, "Failed to register\n");
318 clk_disable_unprepare(crc->clk);
323 mutex_unlock(&refcnt_lock);
325 dev_info(dev, "Initialized\n");
327 pm_runtime_put_sync(dev);
332 static int stm32_crc_remove(struct platform_device *pdev)
334 struct stm32_crc *crc = platform_get_drvdata(pdev);
335 int ret = pm_runtime_get_sync(crc->dev);
338 pm_runtime_put_noidle(crc->dev);
342 spin_lock(&crc_list.lock);
343 list_del(&crc->list);
344 spin_unlock(&crc_list.lock);
346 mutex_lock(&refcnt_lock);
348 crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
349 mutex_unlock(&refcnt_lock);
351 pm_runtime_disable(crc->dev);
352 pm_runtime_put_noidle(crc->dev);
354 clk_disable_unprepare(crc->clk);
360 static int stm32_crc_runtime_suspend(struct device *dev)
362 struct stm32_crc *crc = dev_get_drvdata(dev);
364 clk_disable_unprepare(crc->clk);
369 static int stm32_crc_runtime_resume(struct device *dev)
371 struct stm32_crc *crc = dev_get_drvdata(dev);
374 ret = clk_prepare_enable(crc->clk);
376 dev_err(crc->dev, "Failed to prepare_enable clock\n");
384 static const struct dev_pm_ops stm32_crc_pm_ops = {
385 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
386 pm_runtime_force_resume)
387 SET_RUNTIME_PM_OPS(stm32_crc_runtime_suspend,
388 stm32_crc_runtime_resume, NULL)
391 static const struct of_device_id stm32_dt_ids[] = {
392 { .compatible = "st,stm32f7-crc", },
395 MODULE_DEVICE_TABLE(of, stm32_dt_ids);
397 static struct platform_driver stm32_crc_driver = {
398 .probe = stm32_crc_probe,
399 .remove = stm32_crc_remove,
402 .pm = &stm32_crc_pm_ops,
403 .of_match_table = stm32_dt_ids,
407 module_platform_driver(stm32_crc_driver);
409 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
410 MODULE_DESCRIPTION("STMicrolectronics STM32 CRC32 hardware driver");
411 MODULE_LICENSE("GPL");