1 // SPDX-License-Identifier: GPL-2.0-only
3 * This file is part of STM32 Crypto driver for Linux.
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author(s): Lionel DEBIEVE <lionel.debieve@st.com> for STMicroelectronics.
10 #include <linux/crypto.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmaengine.h>
14 #include <linux/interrupt.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/reset.h>
24 #include <crypto/engine.h>
25 #include <crypto/hash.h>
26 #include <crypto/md5.h>
27 #include <crypto/scatterwalk.h>
28 #include <crypto/sha.h>
29 #include <crypto/internal/hash.h>
36 #define HASH_CSR(x) (0x0F8 + ((x) * 0x04))
37 #define HASH_HREG(x) (0x310 + ((x) * 0x04))
38 #define HASH_HWCFGR 0x3F0
39 #define HASH_VER 0x3F4
42 /* Control Register */
43 #define HASH_CR_INIT BIT(2)
44 #define HASH_CR_DMAE BIT(3)
45 #define HASH_CR_DATATYPE_POS 4
46 #define HASH_CR_MODE BIT(6)
47 #define HASH_CR_MDMAT BIT(13)
48 #define HASH_CR_DMAA BIT(14)
49 #define HASH_CR_LKEY BIT(16)
51 #define HASH_CR_ALGO_SHA1 0x0
52 #define HASH_CR_ALGO_MD5 0x80
53 #define HASH_CR_ALGO_SHA224 0x40000
54 #define HASH_CR_ALGO_SHA256 0x40080
57 #define HASH_DINIE BIT(0)
58 #define HASH_DCIE BIT(1)
61 #define HASH_MASK_CALC_COMPLETION BIT(0)
62 #define HASH_MASK_DATA_INPUT BIT(1)
64 /* Context swap register */
65 #define HASH_CSR_REGISTER_NUMBER 53
68 #define HASH_SR_DATA_INPUT_READY BIT(0)
69 #define HASH_SR_OUTPUT_READY BIT(1)
70 #define HASH_SR_DMA_ACTIVE BIT(2)
71 #define HASH_SR_BUSY BIT(3)
74 #define HASH_STR_NBLW_MASK GENMASK(4, 0)
75 #define HASH_STR_DCAL BIT(8)
77 #define HASH_FLAGS_INIT BIT(0)
78 #define HASH_FLAGS_OUTPUT_READY BIT(1)
79 #define HASH_FLAGS_CPU BIT(2)
80 #define HASH_FLAGS_DMA_READY BIT(3)
81 #define HASH_FLAGS_DMA_ACTIVE BIT(4)
82 #define HASH_FLAGS_HMAC_INIT BIT(5)
83 #define HASH_FLAGS_HMAC_FINAL BIT(6)
84 #define HASH_FLAGS_HMAC_KEY BIT(7)
86 #define HASH_FLAGS_FINAL BIT(15)
87 #define HASH_FLAGS_FINUP BIT(16)
88 #define HASH_FLAGS_ALGO_MASK GENMASK(21, 18)
89 #define HASH_FLAGS_MD5 BIT(18)
90 #define HASH_FLAGS_SHA1 BIT(19)
91 #define HASH_FLAGS_SHA224 BIT(20)
92 #define HASH_FLAGS_SHA256 BIT(21)
93 #define HASH_FLAGS_ERRORS BIT(22)
94 #define HASH_FLAGS_HMAC BIT(23)
96 #define HASH_OP_UPDATE 1
97 #define HASH_OP_FINAL 2
99 enum stm32_hash_data_format {
100 HASH_DATA_32_BITS = 0x0,
101 HASH_DATA_16_BITS = 0x1,
102 HASH_DATA_8_BITS = 0x2,
103 HASH_DATA_1_BIT = 0x3
106 #define HASH_BUFLEN 256
107 #define HASH_LONG_KEY 64
108 #define HASH_MAX_KEY_SIZE (SHA256_BLOCK_SIZE * 8)
109 #define HASH_QUEUE_LENGTH 16
110 #define HASH_DMA_THRESHOLD 50
112 #define HASH_AUTOSUSPEND_DELAY 50
114 struct stm32_hash_ctx {
115 struct crypto_engine_ctx enginectx;
116 struct stm32_hash_dev *hdev;
119 u8 key[HASH_MAX_KEY_SIZE];
123 struct stm32_hash_request_ctx {
124 struct stm32_hash_dev *hdev;
128 u8 digest[SHA256_DIGEST_SIZE] __aligned(sizeof(u32));
134 struct scatterlist *sg;
137 struct scatterlist sg_key;
145 u8 buffer[HASH_BUFLEN] __aligned(sizeof(u32));
151 struct stm32_hash_algs_info {
152 struct ahash_alg *algs_list;
156 struct stm32_hash_pdata {
157 struct stm32_hash_algs_info *algs_info;
158 size_t algs_info_size;
161 struct stm32_hash_dev {
162 struct list_head list;
165 struct reset_control *rst;
166 void __iomem *io_base;
167 phys_addr_t phys_base;
171 struct ahash_request *req;
172 struct crypto_engine *engine;
177 struct dma_chan *dma_lch;
178 struct completion dma_completion;
180 const struct stm32_hash_pdata *pdata;
183 struct stm32_hash_drv {
184 struct list_head dev_list;
185 spinlock_t lock; /* List protection access */
188 static struct stm32_hash_drv stm32_hash = {
189 .dev_list = LIST_HEAD_INIT(stm32_hash.dev_list),
190 .lock = __SPIN_LOCK_UNLOCKED(stm32_hash.lock),
193 static void stm32_hash_dma_callback(void *param);
195 static inline u32 stm32_hash_read(struct stm32_hash_dev *hdev, u32 offset)
197 return readl_relaxed(hdev->io_base + offset);
200 static inline void stm32_hash_write(struct stm32_hash_dev *hdev,
201 u32 offset, u32 value)
203 writel_relaxed(value, hdev->io_base + offset);
206 static inline int stm32_hash_wait_busy(struct stm32_hash_dev *hdev)
210 return readl_relaxed_poll_timeout(hdev->io_base + HASH_SR, status,
211 !(status & HASH_SR_BUSY), 10, 10000);
214 static void stm32_hash_set_nblw(struct stm32_hash_dev *hdev, int length)
218 reg = stm32_hash_read(hdev, HASH_STR);
219 reg &= ~(HASH_STR_NBLW_MASK);
220 reg |= (8U * ((length) % 4U));
221 stm32_hash_write(hdev, HASH_STR, reg);
224 static int stm32_hash_write_key(struct stm32_hash_dev *hdev)
226 struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req);
227 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
229 int keylen = ctx->keylen;
230 void *key = ctx->key;
233 stm32_hash_set_nblw(hdev, keylen);
236 stm32_hash_write(hdev, HASH_DIN, *(u32 *)key);
241 reg = stm32_hash_read(hdev, HASH_STR);
242 reg |= HASH_STR_DCAL;
243 stm32_hash_write(hdev, HASH_STR, reg);
251 static void stm32_hash_write_ctrl(struct stm32_hash_dev *hdev)
253 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
254 struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req);
255 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
257 u32 reg = HASH_CR_INIT;
259 if (!(hdev->flags & HASH_FLAGS_INIT)) {
260 switch (rctx->flags & HASH_FLAGS_ALGO_MASK) {
262 reg |= HASH_CR_ALGO_MD5;
264 case HASH_FLAGS_SHA1:
265 reg |= HASH_CR_ALGO_SHA1;
267 case HASH_FLAGS_SHA224:
268 reg |= HASH_CR_ALGO_SHA224;
270 case HASH_FLAGS_SHA256:
271 reg |= HASH_CR_ALGO_SHA256;
274 reg |= HASH_CR_ALGO_MD5;
277 reg |= (rctx->data_type << HASH_CR_DATATYPE_POS);
279 if (rctx->flags & HASH_FLAGS_HMAC) {
280 hdev->flags |= HASH_FLAGS_HMAC;
282 if (ctx->keylen > HASH_LONG_KEY)
286 stm32_hash_write(hdev, HASH_IMR, HASH_DCIE);
288 stm32_hash_write(hdev, HASH_CR, reg);
290 hdev->flags |= HASH_FLAGS_INIT;
292 dev_dbg(hdev->dev, "Write Control %x\n", reg);
296 static void stm32_hash_append_sg(struct stm32_hash_request_ctx *rctx)
300 while ((rctx->bufcnt < rctx->buflen) && rctx->total) {
301 count = min(rctx->sg->length - rctx->offset, rctx->total);
302 count = min(count, rctx->buflen - rctx->bufcnt);
305 if ((rctx->sg->length == 0) && !sg_is_last(rctx->sg)) {
306 rctx->sg = sg_next(rctx->sg);
313 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, rctx->sg,
314 rctx->offset, count, 0);
316 rctx->bufcnt += count;
317 rctx->offset += count;
318 rctx->total -= count;
320 if (rctx->offset == rctx->sg->length) {
321 rctx->sg = sg_next(rctx->sg);
330 static int stm32_hash_xmit_cpu(struct stm32_hash_dev *hdev,
331 const u8 *buf, size_t length, int final)
333 unsigned int count, len32;
334 const u32 *buffer = (const u32 *)buf;
338 hdev->flags |= HASH_FLAGS_FINAL;
340 len32 = DIV_ROUND_UP(length, sizeof(u32));
342 dev_dbg(hdev->dev, "%s: length: %zd, final: %x len32 %i\n",
343 __func__, length, final, len32);
345 hdev->flags |= HASH_FLAGS_CPU;
347 stm32_hash_write_ctrl(hdev);
349 if (stm32_hash_wait_busy(hdev))
352 if ((hdev->flags & HASH_FLAGS_HMAC) &&
353 (!(hdev->flags & HASH_FLAGS_HMAC_KEY))) {
354 hdev->flags |= HASH_FLAGS_HMAC_KEY;
355 stm32_hash_write_key(hdev);
356 if (stm32_hash_wait_busy(hdev))
360 for (count = 0; count < len32; count++)
361 stm32_hash_write(hdev, HASH_DIN, buffer[count]);
364 stm32_hash_set_nblw(hdev, length);
365 reg = stm32_hash_read(hdev, HASH_STR);
366 reg |= HASH_STR_DCAL;
367 stm32_hash_write(hdev, HASH_STR, reg);
368 if (hdev->flags & HASH_FLAGS_HMAC) {
369 if (stm32_hash_wait_busy(hdev))
371 stm32_hash_write_key(hdev);
379 static int stm32_hash_update_cpu(struct stm32_hash_dev *hdev)
381 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
382 int bufcnt, err = 0, final;
384 dev_dbg(hdev->dev, "%s flags %lx\n", __func__, rctx->flags);
386 final = (rctx->flags & HASH_FLAGS_FINUP);
388 while ((rctx->total >= rctx->buflen) ||
389 (rctx->bufcnt + rctx->total >= rctx->buflen)) {
390 stm32_hash_append_sg(rctx);
391 bufcnt = rctx->bufcnt;
393 err = stm32_hash_xmit_cpu(hdev, rctx->buffer, bufcnt, 0);
396 stm32_hash_append_sg(rctx);
399 bufcnt = rctx->bufcnt;
401 err = stm32_hash_xmit_cpu(hdev, rctx->buffer, bufcnt,
402 (rctx->flags & HASH_FLAGS_FINUP));
408 static int stm32_hash_xmit_dma(struct stm32_hash_dev *hdev,
409 struct scatterlist *sg, int length, int mdma)
411 struct dma_async_tx_descriptor *in_desc;
416 in_desc = dmaengine_prep_slave_sg(hdev->dma_lch, sg, 1,
417 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT |
420 dev_err(hdev->dev, "dmaengine_prep_slave error\n");
424 reinit_completion(&hdev->dma_completion);
425 in_desc->callback = stm32_hash_dma_callback;
426 in_desc->callback_param = hdev;
428 hdev->flags |= HASH_FLAGS_FINAL;
429 hdev->flags |= HASH_FLAGS_DMA_ACTIVE;
431 reg = stm32_hash_read(hdev, HASH_CR);
434 reg |= HASH_CR_MDMAT;
436 reg &= ~HASH_CR_MDMAT;
440 stm32_hash_write(hdev, HASH_CR, reg);
442 stm32_hash_set_nblw(hdev, length);
444 cookie = dmaengine_submit(in_desc);
445 err = dma_submit_error(cookie);
449 dma_async_issue_pending(hdev->dma_lch);
451 if (!wait_for_completion_timeout(&hdev->dma_completion,
452 msecs_to_jiffies(100)))
455 if (dma_async_is_tx_complete(hdev->dma_lch, cookie,
456 NULL, NULL) != DMA_COMPLETE)
460 dev_err(hdev->dev, "DMA Error %i\n", err);
461 dmaengine_terminate_all(hdev->dma_lch);
468 static void stm32_hash_dma_callback(void *param)
470 struct stm32_hash_dev *hdev = param;
472 complete(&hdev->dma_completion);
474 hdev->flags |= HASH_FLAGS_DMA_READY;
477 static int stm32_hash_hmac_dma_send(struct stm32_hash_dev *hdev)
479 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
480 struct crypto_ahash *tfm = crypto_ahash_reqtfm(hdev->req);
481 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
484 if (ctx->keylen < HASH_DMA_THRESHOLD || (hdev->dma_mode == 1)) {
485 err = stm32_hash_write_key(hdev);
486 if (stm32_hash_wait_busy(hdev))
489 if (!(hdev->flags & HASH_FLAGS_HMAC_KEY))
490 sg_init_one(&rctx->sg_key, ctx->key,
491 ALIGN(ctx->keylen, sizeof(u32)));
493 rctx->dma_ct = dma_map_sg(hdev->dev, &rctx->sg_key, 1,
495 if (rctx->dma_ct == 0) {
496 dev_err(hdev->dev, "dma_map_sg error\n");
500 err = stm32_hash_xmit_dma(hdev, &rctx->sg_key, ctx->keylen, 0);
502 dma_unmap_sg(hdev->dev, &rctx->sg_key, 1, DMA_TO_DEVICE);
508 static int stm32_hash_dma_init(struct stm32_hash_dev *hdev)
510 struct dma_slave_config dma_conf;
511 struct dma_chan *chan;
514 memset(&dma_conf, 0, sizeof(dma_conf));
516 dma_conf.direction = DMA_MEM_TO_DEV;
517 dma_conf.dst_addr = hdev->phys_base + HASH_DIN;
518 dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
519 dma_conf.src_maxburst = hdev->dma_maxburst;
520 dma_conf.dst_maxburst = hdev->dma_maxburst;
521 dma_conf.device_fc = false;
523 chan = dma_request_chan(hdev->dev, "in");
525 return PTR_ERR(chan);
527 hdev->dma_lch = chan;
529 err = dmaengine_slave_config(hdev->dma_lch, &dma_conf);
531 dma_release_channel(hdev->dma_lch);
532 hdev->dma_lch = NULL;
533 dev_err(hdev->dev, "Couldn't configure DMA slave.\n");
537 init_completion(&hdev->dma_completion);
542 static int stm32_hash_dma_send(struct stm32_hash_dev *hdev)
544 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(hdev->req);
545 struct scatterlist sg[1], *tsg;
546 int err = 0, len = 0, reg, ncp = 0;
548 u32 *buffer = (void *)rctx->buffer;
550 rctx->sg = hdev->req->src;
551 rctx->total = hdev->req->nbytes;
553 rctx->nents = sg_nents(rctx->sg);
558 stm32_hash_write_ctrl(hdev);
560 if (hdev->flags & HASH_FLAGS_HMAC) {
561 err = stm32_hash_hmac_dma_send(hdev);
562 if (err != -EINPROGRESS)
566 for_each_sg(rctx->sg, tsg, rctx->nents, i) {
570 if (sg_is_last(sg)) {
571 if (hdev->dma_mode == 1) {
572 len = (ALIGN(sg->length, 16) - 16);
574 ncp = sg_pcopy_to_buffer(
575 rctx->sg, rctx->nents,
576 rctx->buffer, sg->length - len,
577 rctx->total - sg->length + len);
581 if (!(IS_ALIGNED(sg->length, sizeof(u32)))) {
583 sg->length = ALIGN(sg->length,
589 rctx->dma_ct = dma_map_sg(hdev->dev, sg, 1,
591 if (rctx->dma_ct == 0) {
592 dev_err(hdev->dev, "dma_map_sg error\n");
596 err = stm32_hash_xmit_dma(hdev, sg, len,
599 dma_unmap_sg(hdev->dev, sg, 1, DMA_TO_DEVICE);
605 if (hdev->dma_mode == 1) {
606 if (stm32_hash_wait_busy(hdev))
608 reg = stm32_hash_read(hdev, HASH_CR);
609 reg &= ~HASH_CR_DMAE;
611 stm32_hash_write(hdev, HASH_CR, reg);
614 memset(buffer + ncp, 0,
615 DIV_ROUND_UP(ncp, sizeof(u32)) - ncp);
616 writesl(hdev->io_base + HASH_DIN, buffer,
617 DIV_ROUND_UP(ncp, sizeof(u32)));
619 stm32_hash_set_nblw(hdev, ncp);
620 reg = stm32_hash_read(hdev, HASH_STR);
621 reg |= HASH_STR_DCAL;
622 stm32_hash_write(hdev, HASH_STR, reg);
626 if (hdev->flags & HASH_FLAGS_HMAC) {
627 if (stm32_hash_wait_busy(hdev))
629 err = stm32_hash_hmac_dma_send(hdev);
635 static struct stm32_hash_dev *stm32_hash_find_dev(struct stm32_hash_ctx *ctx)
637 struct stm32_hash_dev *hdev = NULL, *tmp;
639 spin_lock_bh(&stm32_hash.lock);
641 list_for_each_entry(tmp, &stm32_hash.dev_list, list) {
650 spin_unlock_bh(&stm32_hash.lock);
655 static bool stm32_hash_dma_aligned_data(struct ahash_request *req)
657 struct scatterlist *sg;
658 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
659 struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
662 if (req->nbytes <= HASH_DMA_THRESHOLD)
665 if (sg_nents(req->src) > 1) {
666 if (hdev->dma_mode == 1)
668 for_each_sg(req->src, sg, sg_nents(req->src), i) {
669 if ((!IS_ALIGNED(sg->length, sizeof(u32))) &&
675 if (req->src->offset % 4)
681 static int stm32_hash_init(struct ahash_request *req)
683 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
684 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
685 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
686 struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
690 rctx->flags = HASH_FLAGS_CPU;
692 rctx->digcnt = crypto_ahash_digestsize(tfm);
693 switch (rctx->digcnt) {
694 case MD5_DIGEST_SIZE:
695 rctx->flags |= HASH_FLAGS_MD5;
697 case SHA1_DIGEST_SIZE:
698 rctx->flags |= HASH_FLAGS_SHA1;
700 case SHA224_DIGEST_SIZE:
701 rctx->flags |= HASH_FLAGS_SHA224;
703 case SHA256_DIGEST_SIZE:
704 rctx->flags |= HASH_FLAGS_SHA256;
711 rctx->buflen = HASH_BUFLEN;
714 rctx->data_type = HASH_DATA_8_BITS;
716 memset(rctx->buffer, 0, HASH_BUFLEN);
718 if (ctx->flags & HASH_FLAGS_HMAC)
719 rctx->flags |= HASH_FLAGS_HMAC;
721 dev_dbg(hdev->dev, "%s Flags %lx\n", __func__, rctx->flags);
726 static int stm32_hash_update_req(struct stm32_hash_dev *hdev)
728 return stm32_hash_update_cpu(hdev);
731 static int stm32_hash_final_req(struct stm32_hash_dev *hdev)
733 struct ahash_request *req = hdev->req;
734 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
736 int buflen = rctx->bufcnt;
740 if (!(rctx->flags & HASH_FLAGS_CPU))
741 err = stm32_hash_dma_send(hdev);
743 err = stm32_hash_xmit_cpu(hdev, rctx->buffer, buflen, 1);
749 static void stm32_hash_copy_hash(struct ahash_request *req)
751 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
752 __be32 *hash = (void *)rctx->digest;
753 unsigned int i, hashsize;
755 switch (rctx->flags & HASH_FLAGS_ALGO_MASK) {
757 hashsize = MD5_DIGEST_SIZE;
759 case HASH_FLAGS_SHA1:
760 hashsize = SHA1_DIGEST_SIZE;
762 case HASH_FLAGS_SHA224:
763 hashsize = SHA224_DIGEST_SIZE;
765 case HASH_FLAGS_SHA256:
766 hashsize = SHA256_DIGEST_SIZE;
772 for (i = 0; i < hashsize / sizeof(u32); i++)
773 hash[i] = cpu_to_be32(stm32_hash_read(rctx->hdev,
777 static int stm32_hash_finish(struct ahash_request *req)
779 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
784 memcpy(req->result, rctx->digest, rctx->digcnt);
789 static void stm32_hash_finish_req(struct ahash_request *req, int err)
791 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
792 struct stm32_hash_dev *hdev = rctx->hdev;
794 if (!err && (HASH_FLAGS_FINAL & hdev->flags)) {
795 stm32_hash_copy_hash(req);
796 err = stm32_hash_finish(req);
797 hdev->flags &= ~(HASH_FLAGS_FINAL | HASH_FLAGS_CPU |
798 HASH_FLAGS_INIT | HASH_FLAGS_DMA_READY |
799 HASH_FLAGS_OUTPUT_READY | HASH_FLAGS_HMAC |
800 HASH_FLAGS_HMAC_INIT | HASH_FLAGS_HMAC_FINAL |
801 HASH_FLAGS_HMAC_KEY);
803 rctx->flags |= HASH_FLAGS_ERRORS;
806 pm_runtime_mark_last_busy(hdev->dev);
807 pm_runtime_put_autosuspend(hdev->dev);
809 crypto_finalize_hash_request(hdev->engine, req, err);
812 static int stm32_hash_hw_init(struct stm32_hash_dev *hdev,
813 struct stm32_hash_request_ctx *rctx)
815 pm_runtime_get_sync(hdev->dev);
817 if (!(HASH_FLAGS_INIT & hdev->flags)) {
818 stm32_hash_write(hdev, HASH_CR, HASH_CR_INIT);
819 stm32_hash_write(hdev, HASH_STR, 0);
820 stm32_hash_write(hdev, HASH_DIN, 0);
821 stm32_hash_write(hdev, HASH_IMR, 0);
828 static int stm32_hash_one_request(struct crypto_engine *engine, void *areq);
829 static int stm32_hash_prepare_req(struct crypto_engine *engine, void *areq);
831 static int stm32_hash_handle_queue(struct stm32_hash_dev *hdev,
832 struct ahash_request *req)
834 return crypto_transfer_hash_request_to_engine(hdev->engine, req);
837 static int stm32_hash_prepare_req(struct crypto_engine *engine, void *areq)
839 struct ahash_request *req = container_of(areq, struct ahash_request,
841 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
842 struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
843 struct stm32_hash_request_ctx *rctx;
850 rctx = ahash_request_ctx(req);
852 dev_dbg(hdev->dev, "processing new req, op: %lu, nbytes %d\n",
853 rctx->op, req->nbytes);
855 return stm32_hash_hw_init(hdev, rctx);
858 static int stm32_hash_one_request(struct crypto_engine *engine, void *areq)
860 struct ahash_request *req = container_of(areq, struct ahash_request,
862 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
863 struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
864 struct stm32_hash_request_ctx *rctx;
872 rctx = ahash_request_ctx(req);
874 if (rctx->op == HASH_OP_UPDATE)
875 err = stm32_hash_update_req(hdev);
876 else if (rctx->op == HASH_OP_FINAL)
877 err = stm32_hash_final_req(hdev);
879 if (err != -EINPROGRESS)
880 /* done task will not finish it, so do it here */
881 stm32_hash_finish_req(req, err);
886 static int stm32_hash_enqueue(struct ahash_request *req, unsigned int op)
888 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
889 struct stm32_hash_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
890 struct stm32_hash_dev *hdev = ctx->hdev;
894 return stm32_hash_handle_queue(hdev, req);
897 static int stm32_hash_update(struct ahash_request *req)
899 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
901 if (!req->nbytes || !(rctx->flags & HASH_FLAGS_CPU))
904 rctx->total = req->nbytes;
908 if ((rctx->bufcnt + rctx->total < rctx->buflen)) {
909 stm32_hash_append_sg(rctx);
913 return stm32_hash_enqueue(req, HASH_OP_UPDATE);
916 static int stm32_hash_final(struct ahash_request *req)
918 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
920 rctx->flags |= HASH_FLAGS_FINUP;
922 return stm32_hash_enqueue(req, HASH_OP_FINAL);
925 static int stm32_hash_finup(struct ahash_request *req)
927 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
928 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
929 struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
932 rctx->flags |= HASH_FLAGS_FINUP;
934 if (hdev->dma_lch && stm32_hash_dma_aligned_data(req))
935 rctx->flags &= ~HASH_FLAGS_CPU;
937 err1 = stm32_hash_update(req);
939 if (err1 == -EINPROGRESS || err1 == -EBUSY)
943 * final() has to be always called to cleanup resources
944 * even if update() failed, except EINPROGRESS
946 err2 = stm32_hash_final(req);
951 static int stm32_hash_digest(struct ahash_request *req)
953 return stm32_hash_init(req) ?: stm32_hash_finup(req);
956 static int stm32_hash_export(struct ahash_request *req, void *out)
958 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
959 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
960 struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
964 pm_runtime_get_sync(hdev->dev);
966 while ((stm32_hash_read(hdev, HASH_SR) & HASH_SR_BUSY))
969 rctx->hw_context = kmalloc_array(3 + HASH_CSR_REGISTER_NUMBER,
973 preg = rctx->hw_context;
975 *preg++ = stm32_hash_read(hdev, HASH_IMR);
976 *preg++ = stm32_hash_read(hdev, HASH_STR);
977 *preg++ = stm32_hash_read(hdev, HASH_CR);
978 for (i = 0; i < HASH_CSR_REGISTER_NUMBER; i++)
979 *preg++ = stm32_hash_read(hdev, HASH_CSR(i));
981 pm_runtime_mark_last_busy(hdev->dev);
982 pm_runtime_put_autosuspend(hdev->dev);
984 memcpy(out, rctx, sizeof(*rctx));
989 static int stm32_hash_import(struct ahash_request *req, const void *in)
991 struct stm32_hash_request_ctx *rctx = ahash_request_ctx(req);
992 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req));
993 struct stm32_hash_dev *hdev = stm32_hash_find_dev(ctx);
994 const u32 *preg = in;
998 memcpy(rctx, in, sizeof(*rctx));
1000 preg = rctx->hw_context;
1002 pm_runtime_get_sync(hdev->dev);
1004 stm32_hash_write(hdev, HASH_IMR, *preg++);
1005 stm32_hash_write(hdev, HASH_STR, *preg++);
1006 stm32_hash_write(hdev, HASH_CR, *preg);
1007 reg = *preg++ | HASH_CR_INIT;
1008 stm32_hash_write(hdev, HASH_CR, reg);
1010 for (i = 0; i < HASH_CSR_REGISTER_NUMBER; i++)
1011 stm32_hash_write(hdev, HASH_CSR(i), *preg++);
1013 pm_runtime_mark_last_busy(hdev->dev);
1014 pm_runtime_put_autosuspend(hdev->dev);
1016 kfree(rctx->hw_context);
1021 static int stm32_hash_setkey(struct crypto_ahash *tfm,
1022 const u8 *key, unsigned int keylen)
1024 struct stm32_hash_ctx *ctx = crypto_ahash_ctx(tfm);
1026 if (keylen <= HASH_MAX_KEY_SIZE) {
1027 memcpy(ctx->key, key, keylen);
1028 ctx->keylen = keylen;
1036 static int stm32_hash_cra_init_algs(struct crypto_tfm *tfm,
1037 const char *algs_hmac_name)
1039 struct stm32_hash_ctx *ctx = crypto_tfm_ctx(tfm);
1041 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1042 sizeof(struct stm32_hash_request_ctx));
1047 ctx->flags |= HASH_FLAGS_HMAC;
1049 ctx->enginectx.op.do_one_request = stm32_hash_one_request;
1050 ctx->enginectx.op.prepare_request = stm32_hash_prepare_req;
1051 ctx->enginectx.op.unprepare_request = NULL;
1055 static int stm32_hash_cra_init(struct crypto_tfm *tfm)
1057 return stm32_hash_cra_init_algs(tfm, NULL);
1060 static int stm32_hash_cra_md5_init(struct crypto_tfm *tfm)
1062 return stm32_hash_cra_init_algs(tfm, "md5");
1065 static int stm32_hash_cra_sha1_init(struct crypto_tfm *tfm)
1067 return stm32_hash_cra_init_algs(tfm, "sha1");
1070 static int stm32_hash_cra_sha224_init(struct crypto_tfm *tfm)
1072 return stm32_hash_cra_init_algs(tfm, "sha224");
1075 static int stm32_hash_cra_sha256_init(struct crypto_tfm *tfm)
1077 return stm32_hash_cra_init_algs(tfm, "sha256");
1080 static irqreturn_t stm32_hash_irq_thread(int irq, void *dev_id)
1082 struct stm32_hash_dev *hdev = dev_id;
1084 if (HASH_FLAGS_CPU & hdev->flags) {
1085 if (HASH_FLAGS_OUTPUT_READY & hdev->flags) {
1086 hdev->flags &= ~HASH_FLAGS_OUTPUT_READY;
1089 } else if (HASH_FLAGS_DMA_READY & hdev->flags) {
1090 if (HASH_FLAGS_DMA_ACTIVE & hdev->flags) {
1091 hdev->flags &= ~HASH_FLAGS_DMA_ACTIVE;
1099 /* Finish current request */
1100 stm32_hash_finish_req(hdev->req, 0);
1105 static irqreturn_t stm32_hash_irq_handler(int irq, void *dev_id)
1107 struct stm32_hash_dev *hdev = dev_id;
1110 reg = stm32_hash_read(hdev, HASH_SR);
1111 if (reg & HASH_SR_OUTPUT_READY) {
1112 reg &= ~HASH_SR_OUTPUT_READY;
1113 stm32_hash_write(hdev, HASH_SR, reg);
1114 hdev->flags |= HASH_FLAGS_OUTPUT_READY;
1116 stm32_hash_write(hdev, HASH_IMR, 0);
1117 return IRQ_WAKE_THREAD;
1123 static struct ahash_alg algs_md5_sha1[] = {
1125 .init = stm32_hash_init,
1126 .update = stm32_hash_update,
1127 .final = stm32_hash_final,
1128 .finup = stm32_hash_finup,
1129 .digest = stm32_hash_digest,
1130 .export = stm32_hash_export,
1131 .import = stm32_hash_import,
1133 .digestsize = MD5_DIGEST_SIZE,
1134 .statesize = sizeof(struct stm32_hash_request_ctx),
1137 .cra_driver_name = "stm32-md5",
1138 .cra_priority = 200,
1139 .cra_flags = CRYPTO_ALG_ASYNC |
1140 CRYPTO_ALG_KERN_DRIVER_ONLY,
1141 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
1142 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1144 .cra_init = stm32_hash_cra_init,
1145 .cra_module = THIS_MODULE,
1150 .init = stm32_hash_init,
1151 .update = stm32_hash_update,
1152 .final = stm32_hash_final,
1153 .finup = stm32_hash_finup,
1154 .digest = stm32_hash_digest,
1155 .export = stm32_hash_export,
1156 .import = stm32_hash_import,
1157 .setkey = stm32_hash_setkey,
1159 .digestsize = MD5_DIGEST_SIZE,
1160 .statesize = sizeof(struct stm32_hash_request_ctx),
1162 .cra_name = "hmac(md5)",
1163 .cra_driver_name = "stm32-hmac-md5",
1164 .cra_priority = 200,
1165 .cra_flags = CRYPTO_ALG_ASYNC |
1166 CRYPTO_ALG_KERN_DRIVER_ONLY,
1167 .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
1168 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1170 .cra_init = stm32_hash_cra_md5_init,
1171 .cra_module = THIS_MODULE,
1176 .init = stm32_hash_init,
1177 .update = stm32_hash_update,
1178 .final = stm32_hash_final,
1179 .finup = stm32_hash_finup,
1180 .digest = stm32_hash_digest,
1181 .export = stm32_hash_export,
1182 .import = stm32_hash_import,
1184 .digestsize = SHA1_DIGEST_SIZE,
1185 .statesize = sizeof(struct stm32_hash_request_ctx),
1188 .cra_driver_name = "stm32-sha1",
1189 .cra_priority = 200,
1190 .cra_flags = CRYPTO_ALG_ASYNC |
1191 CRYPTO_ALG_KERN_DRIVER_ONLY,
1192 .cra_blocksize = SHA1_BLOCK_SIZE,
1193 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1195 .cra_init = stm32_hash_cra_init,
1196 .cra_module = THIS_MODULE,
1201 .init = stm32_hash_init,
1202 .update = stm32_hash_update,
1203 .final = stm32_hash_final,
1204 .finup = stm32_hash_finup,
1205 .digest = stm32_hash_digest,
1206 .export = stm32_hash_export,
1207 .import = stm32_hash_import,
1208 .setkey = stm32_hash_setkey,
1210 .digestsize = SHA1_DIGEST_SIZE,
1211 .statesize = sizeof(struct stm32_hash_request_ctx),
1213 .cra_name = "hmac(sha1)",
1214 .cra_driver_name = "stm32-hmac-sha1",
1215 .cra_priority = 200,
1216 .cra_flags = CRYPTO_ALG_ASYNC |
1217 CRYPTO_ALG_KERN_DRIVER_ONLY,
1218 .cra_blocksize = SHA1_BLOCK_SIZE,
1219 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1221 .cra_init = stm32_hash_cra_sha1_init,
1222 .cra_module = THIS_MODULE,
1228 static struct ahash_alg algs_sha224_sha256[] = {
1230 .init = stm32_hash_init,
1231 .update = stm32_hash_update,
1232 .final = stm32_hash_final,
1233 .finup = stm32_hash_finup,
1234 .digest = stm32_hash_digest,
1235 .export = stm32_hash_export,
1236 .import = stm32_hash_import,
1238 .digestsize = SHA224_DIGEST_SIZE,
1239 .statesize = sizeof(struct stm32_hash_request_ctx),
1241 .cra_name = "sha224",
1242 .cra_driver_name = "stm32-sha224",
1243 .cra_priority = 200,
1244 .cra_flags = CRYPTO_ALG_ASYNC |
1245 CRYPTO_ALG_KERN_DRIVER_ONLY,
1246 .cra_blocksize = SHA224_BLOCK_SIZE,
1247 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1249 .cra_init = stm32_hash_cra_init,
1250 .cra_module = THIS_MODULE,
1255 .init = stm32_hash_init,
1256 .update = stm32_hash_update,
1257 .final = stm32_hash_final,
1258 .finup = stm32_hash_finup,
1259 .digest = stm32_hash_digest,
1260 .setkey = stm32_hash_setkey,
1261 .export = stm32_hash_export,
1262 .import = stm32_hash_import,
1264 .digestsize = SHA224_DIGEST_SIZE,
1265 .statesize = sizeof(struct stm32_hash_request_ctx),
1267 .cra_name = "hmac(sha224)",
1268 .cra_driver_name = "stm32-hmac-sha224",
1269 .cra_priority = 200,
1270 .cra_flags = CRYPTO_ALG_ASYNC |
1271 CRYPTO_ALG_KERN_DRIVER_ONLY,
1272 .cra_blocksize = SHA224_BLOCK_SIZE,
1273 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1275 .cra_init = stm32_hash_cra_sha224_init,
1276 .cra_module = THIS_MODULE,
1281 .init = stm32_hash_init,
1282 .update = stm32_hash_update,
1283 .final = stm32_hash_final,
1284 .finup = stm32_hash_finup,
1285 .digest = stm32_hash_digest,
1286 .export = stm32_hash_export,
1287 .import = stm32_hash_import,
1289 .digestsize = SHA256_DIGEST_SIZE,
1290 .statesize = sizeof(struct stm32_hash_request_ctx),
1292 .cra_name = "sha256",
1293 .cra_driver_name = "stm32-sha256",
1294 .cra_priority = 200,
1295 .cra_flags = CRYPTO_ALG_ASYNC |
1296 CRYPTO_ALG_KERN_DRIVER_ONLY,
1297 .cra_blocksize = SHA256_BLOCK_SIZE,
1298 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1300 .cra_init = stm32_hash_cra_init,
1301 .cra_module = THIS_MODULE,
1306 .init = stm32_hash_init,
1307 .update = stm32_hash_update,
1308 .final = stm32_hash_final,
1309 .finup = stm32_hash_finup,
1310 .digest = stm32_hash_digest,
1311 .export = stm32_hash_export,
1312 .import = stm32_hash_import,
1313 .setkey = stm32_hash_setkey,
1315 .digestsize = SHA256_DIGEST_SIZE,
1316 .statesize = sizeof(struct stm32_hash_request_ctx),
1318 .cra_name = "hmac(sha256)",
1319 .cra_driver_name = "stm32-hmac-sha256",
1320 .cra_priority = 200,
1321 .cra_flags = CRYPTO_ALG_ASYNC |
1322 CRYPTO_ALG_KERN_DRIVER_ONLY,
1323 .cra_blocksize = SHA256_BLOCK_SIZE,
1324 .cra_ctxsize = sizeof(struct stm32_hash_ctx),
1326 .cra_init = stm32_hash_cra_sha256_init,
1327 .cra_module = THIS_MODULE,
1333 static int stm32_hash_register_algs(struct stm32_hash_dev *hdev)
1338 for (i = 0; i < hdev->pdata->algs_info_size; i++) {
1339 for (j = 0; j < hdev->pdata->algs_info[i].size; j++) {
1340 err = crypto_register_ahash(
1341 &hdev->pdata->algs_info[i].algs_list[j]);
1349 dev_err(hdev->dev, "Algo %d : %d failed\n", i, j);
1352 crypto_unregister_ahash(
1353 &hdev->pdata->algs_info[i].algs_list[j]);
1359 static int stm32_hash_unregister_algs(struct stm32_hash_dev *hdev)
1363 for (i = 0; i < hdev->pdata->algs_info_size; i++) {
1364 for (j = 0; j < hdev->pdata->algs_info[i].size; j++)
1365 crypto_unregister_ahash(
1366 &hdev->pdata->algs_info[i].algs_list[j]);
1372 static struct stm32_hash_algs_info stm32_hash_algs_info_stm32f4[] = {
1374 .algs_list = algs_md5_sha1,
1375 .size = ARRAY_SIZE(algs_md5_sha1),
1379 static const struct stm32_hash_pdata stm32_hash_pdata_stm32f4 = {
1380 .algs_info = stm32_hash_algs_info_stm32f4,
1381 .algs_info_size = ARRAY_SIZE(stm32_hash_algs_info_stm32f4),
1384 static struct stm32_hash_algs_info stm32_hash_algs_info_stm32f7[] = {
1386 .algs_list = algs_md5_sha1,
1387 .size = ARRAY_SIZE(algs_md5_sha1),
1390 .algs_list = algs_sha224_sha256,
1391 .size = ARRAY_SIZE(algs_sha224_sha256),
1395 static const struct stm32_hash_pdata stm32_hash_pdata_stm32f7 = {
1396 .algs_info = stm32_hash_algs_info_stm32f7,
1397 .algs_info_size = ARRAY_SIZE(stm32_hash_algs_info_stm32f7),
1400 static const struct of_device_id stm32_hash_of_match[] = {
1402 .compatible = "st,stm32f456-hash",
1403 .data = &stm32_hash_pdata_stm32f4,
1406 .compatible = "st,stm32f756-hash",
1407 .data = &stm32_hash_pdata_stm32f7,
1412 MODULE_DEVICE_TABLE(of, stm32_hash_of_match);
1414 static int stm32_hash_get_of_match(struct stm32_hash_dev *hdev,
1417 hdev->pdata = of_device_get_match_data(dev);
1419 dev_err(dev, "no compatible OF match\n");
1423 if (of_property_read_u32(dev->of_node, "dma-maxburst",
1424 &hdev->dma_maxburst)) {
1425 dev_info(dev, "dma-maxburst not specified, using 0\n");
1426 hdev->dma_maxburst = 0;
1432 static int stm32_hash_probe(struct platform_device *pdev)
1434 struct stm32_hash_dev *hdev;
1435 struct device *dev = &pdev->dev;
1436 struct resource *res;
1439 hdev = devm_kzalloc(dev, sizeof(*hdev), GFP_KERNEL);
1443 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1444 hdev->io_base = devm_ioremap_resource(dev, res);
1445 if (IS_ERR(hdev->io_base))
1446 return PTR_ERR(hdev->io_base);
1448 hdev->phys_base = res->start;
1450 ret = stm32_hash_get_of_match(hdev, dev);
1454 irq = platform_get_irq(pdev, 0);
1458 ret = devm_request_threaded_irq(dev, irq, stm32_hash_irq_handler,
1459 stm32_hash_irq_thread, IRQF_ONESHOT,
1460 dev_name(dev), hdev);
1462 dev_err(dev, "Cannot grab IRQ\n");
1466 hdev->clk = devm_clk_get(&pdev->dev, NULL);
1467 if (IS_ERR(hdev->clk))
1468 return dev_err_probe(dev, PTR_ERR(hdev->clk),
1469 "failed to get clock for hash\n");
1471 ret = clk_prepare_enable(hdev->clk);
1473 dev_err(dev, "failed to enable hash clock (%d)\n", ret);
1477 pm_runtime_set_autosuspend_delay(dev, HASH_AUTOSUSPEND_DELAY);
1478 pm_runtime_use_autosuspend(dev);
1480 pm_runtime_get_noresume(dev);
1481 pm_runtime_set_active(dev);
1482 pm_runtime_enable(dev);
1484 hdev->rst = devm_reset_control_get(&pdev->dev, NULL);
1485 if (IS_ERR(hdev->rst)) {
1486 if (PTR_ERR(hdev->rst) == -EPROBE_DEFER) {
1487 ret = -EPROBE_DEFER;
1491 reset_control_assert(hdev->rst);
1493 reset_control_deassert(hdev->rst);
1498 platform_set_drvdata(pdev, hdev);
1500 ret = stm32_hash_dma_init(hdev);
1505 dev_dbg(dev, "DMA mode not available\n");
1511 spin_lock(&stm32_hash.lock);
1512 list_add_tail(&hdev->list, &stm32_hash.dev_list);
1513 spin_unlock(&stm32_hash.lock);
1515 /* Initialize crypto engine */
1516 hdev->engine = crypto_engine_alloc_init(dev, 1);
1517 if (!hdev->engine) {
1522 ret = crypto_engine_start(hdev->engine);
1524 goto err_engine_start;
1526 hdev->dma_mode = stm32_hash_read(hdev, HASH_HWCFGR);
1528 /* Register algos */
1529 ret = stm32_hash_register_algs(hdev);
1533 dev_info(dev, "Init HASH done HW ver %x DMA mode %u\n",
1534 stm32_hash_read(hdev, HASH_VER), hdev->dma_mode);
1536 pm_runtime_put_sync(dev);
1542 crypto_engine_exit(hdev->engine);
1544 spin_lock(&stm32_hash.lock);
1545 list_del(&hdev->list);
1546 spin_unlock(&stm32_hash.lock);
1549 dma_release_channel(hdev->dma_lch);
1551 pm_runtime_disable(dev);
1552 pm_runtime_put_noidle(dev);
1554 clk_disable_unprepare(hdev->clk);
1559 static int stm32_hash_remove(struct platform_device *pdev)
1561 struct stm32_hash_dev *hdev;
1564 hdev = platform_get_drvdata(pdev);
1568 ret = pm_runtime_resume_and_get(hdev->dev);
1572 stm32_hash_unregister_algs(hdev);
1574 crypto_engine_exit(hdev->engine);
1576 spin_lock(&stm32_hash.lock);
1577 list_del(&hdev->list);
1578 spin_unlock(&stm32_hash.lock);
1581 dma_release_channel(hdev->dma_lch);
1583 pm_runtime_disable(hdev->dev);
1584 pm_runtime_put_noidle(hdev->dev);
1586 clk_disable_unprepare(hdev->clk);
1592 static int stm32_hash_runtime_suspend(struct device *dev)
1594 struct stm32_hash_dev *hdev = dev_get_drvdata(dev);
1596 clk_disable_unprepare(hdev->clk);
1601 static int stm32_hash_runtime_resume(struct device *dev)
1603 struct stm32_hash_dev *hdev = dev_get_drvdata(dev);
1606 ret = clk_prepare_enable(hdev->clk);
1608 dev_err(hdev->dev, "Failed to prepare_enable clock\n");
1616 static const struct dev_pm_ops stm32_hash_pm_ops = {
1617 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1618 pm_runtime_force_resume)
1619 SET_RUNTIME_PM_OPS(stm32_hash_runtime_suspend,
1620 stm32_hash_runtime_resume, NULL)
1623 static struct platform_driver stm32_hash_driver = {
1624 .probe = stm32_hash_probe,
1625 .remove = stm32_hash_remove,
1627 .name = "stm32-hash",
1628 .pm = &stm32_hash_pm_ops,
1629 .of_match_table = stm32_hash_of_match,
1633 module_platform_driver(stm32_hash_driver);
1635 MODULE_DESCRIPTION("STM32 SHA1/224/256 & MD5 (HMAC) hw accelerator driver");
1636 MODULE_AUTHOR("Lionel Debieve <lionel.debieve@st.com>");
1637 MODULE_LICENSE("GPL v2");