1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) STMicroelectronics SA 2017
4 * Author: Fabien Dessenne <fabien.dessenne@st.com>
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/iopoll.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/reset.h>
17 #include <crypto/aes.h>
18 #include <crypto/internal/des.h>
19 #include <crypto/engine.h>
20 #include <crypto/scatterwalk.h>
21 #include <crypto/internal/aead.h>
22 #include <crypto/internal/skcipher.h>
24 #define DRIVER_NAME "stm32-cryp"
26 /* Bit [0] encrypt / decrypt */
27 #define FLG_ENCRYPT BIT(0)
28 /* Bit [8..1] algo & operation mode */
29 #define FLG_AES BIT(1)
30 #define FLG_DES BIT(2)
31 #define FLG_TDES BIT(3)
32 #define FLG_ECB BIT(4)
33 #define FLG_CBC BIT(5)
34 #define FLG_CTR BIT(6)
35 #define FLG_GCM BIT(7)
36 #define FLG_CCM BIT(8)
37 /* Mode mask = bits [15..0] */
38 #define FLG_MODE_MASK GENMASK(15, 0)
39 /* Bit [31..16] status */
42 #define CRYP_CR 0x00000000
43 #define CRYP_SR 0x00000004
44 #define CRYP_DIN 0x00000008
45 #define CRYP_DOUT 0x0000000C
46 #define CRYP_DMACR 0x00000010
47 #define CRYP_IMSCR 0x00000014
48 #define CRYP_RISR 0x00000018
49 #define CRYP_MISR 0x0000001C
50 #define CRYP_K0LR 0x00000020
51 #define CRYP_K0RR 0x00000024
52 #define CRYP_K1LR 0x00000028
53 #define CRYP_K1RR 0x0000002C
54 #define CRYP_K2LR 0x00000030
55 #define CRYP_K2RR 0x00000034
56 #define CRYP_K3LR 0x00000038
57 #define CRYP_K3RR 0x0000003C
58 #define CRYP_IV0LR 0x00000040
59 #define CRYP_IV0RR 0x00000044
60 #define CRYP_IV1LR 0x00000048
61 #define CRYP_IV1RR 0x0000004C
62 #define CRYP_CSGCMCCM0R 0x00000050
63 #define CRYP_CSGCM0R 0x00000070
65 /* Registers values */
66 #define CR_DEC_NOT_ENC 0x00000004
67 #define CR_TDES_ECB 0x00000000
68 #define CR_TDES_CBC 0x00000008
69 #define CR_DES_ECB 0x00000010
70 #define CR_DES_CBC 0x00000018
71 #define CR_AES_ECB 0x00000020
72 #define CR_AES_CBC 0x00000028
73 #define CR_AES_CTR 0x00000030
74 #define CR_AES_KP 0x00000038
75 #define CR_AES_GCM 0x00080000
76 #define CR_AES_CCM 0x00080008
77 #define CR_AES_UNKNOWN 0xFFFFFFFF
78 #define CR_ALGO_MASK 0x00080038
79 #define CR_DATA32 0x00000000
80 #define CR_DATA16 0x00000040
81 #define CR_DATA8 0x00000080
82 #define CR_DATA1 0x000000C0
83 #define CR_KEY128 0x00000000
84 #define CR_KEY192 0x00000100
85 #define CR_KEY256 0x00000200
86 #define CR_FFLUSH 0x00004000
87 #define CR_CRYPEN 0x00008000
88 #define CR_PH_INIT 0x00000000
89 #define CR_PH_HEADER 0x00010000
90 #define CR_PH_PAYLOAD 0x00020000
91 #define CR_PH_FINAL 0x00030000
92 #define CR_PH_MASK 0x00030000
93 #define CR_NBPBL_SHIFT 20
95 #define SR_BUSY 0x00000010
96 #define SR_OFNE 0x00000004
98 #define IMSCR_IN BIT(0)
99 #define IMSCR_OUT BIT(1)
101 #define MISR_IN BIT(0)
102 #define MISR_OUT BIT(1)
105 #define AES_BLOCK_32 (AES_BLOCK_SIZE / sizeof(u32))
106 #define GCM_CTR_INIT 2
107 #define CRYP_AUTOSUSPEND_DELAY 50
109 struct stm32_cryp_caps {
114 struct stm32_cryp_ctx {
115 struct crypto_engine_ctx enginectx;
116 struct stm32_cryp *cryp;
118 __be32 key[AES_KEYSIZE_256 / sizeof(u32)];
122 struct stm32_cryp_reqctx {
127 struct list_head list;
133 const struct stm32_cryp_caps *caps;
134 struct stm32_cryp_ctx *ctx;
136 struct crypto_engine *engine;
138 struct skcipher_request *req;
139 struct aead_request *areq;
148 struct scatterlist *out_sg;
150 struct scatter_walk in_walk;
151 struct scatter_walk out_walk;
157 struct stm32_cryp_list {
158 struct list_head dev_list;
159 spinlock_t lock; /* protect dev_list */
162 static struct stm32_cryp_list cryp_list = {
163 .dev_list = LIST_HEAD_INIT(cryp_list.dev_list),
164 .lock = __SPIN_LOCK_UNLOCKED(cryp_list.lock),
167 static inline bool is_aes(struct stm32_cryp *cryp)
169 return cryp->flags & FLG_AES;
172 static inline bool is_des(struct stm32_cryp *cryp)
174 return cryp->flags & FLG_DES;
177 static inline bool is_tdes(struct stm32_cryp *cryp)
179 return cryp->flags & FLG_TDES;
182 static inline bool is_ecb(struct stm32_cryp *cryp)
184 return cryp->flags & FLG_ECB;
187 static inline bool is_cbc(struct stm32_cryp *cryp)
189 return cryp->flags & FLG_CBC;
192 static inline bool is_ctr(struct stm32_cryp *cryp)
194 return cryp->flags & FLG_CTR;
197 static inline bool is_gcm(struct stm32_cryp *cryp)
199 return cryp->flags & FLG_GCM;
202 static inline bool is_ccm(struct stm32_cryp *cryp)
204 return cryp->flags & FLG_CCM;
207 static inline bool is_encrypt(struct stm32_cryp *cryp)
209 return cryp->flags & FLG_ENCRYPT;
212 static inline bool is_decrypt(struct stm32_cryp *cryp)
214 return !is_encrypt(cryp);
217 static inline u32 stm32_cryp_read(struct stm32_cryp *cryp, u32 ofst)
219 return readl_relaxed(cryp->regs + ofst);
222 static inline void stm32_cryp_write(struct stm32_cryp *cryp, u32 ofst, u32 val)
224 writel_relaxed(val, cryp->regs + ofst);
227 static inline int stm32_cryp_wait_busy(struct stm32_cryp *cryp)
231 return readl_relaxed_poll_timeout(cryp->regs + CRYP_SR, status,
232 !(status & SR_BUSY), 10, 100000);
235 static inline int stm32_cryp_wait_enable(struct stm32_cryp *cryp)
239 return readl_relaxed_poll_timeout(cryp->regs + CRYP_CR, status,
240 !(status & CR_CRYPEN), 10, 100000);
243 static inline int stm32_cryp_wait_output(struct stm32_cryp *cryp)
247 return readl_relaxed_poll_timeout(cryp->regs + CRYP_SR, status,
248 status & SR_OFNE, 10, 100000);
251 static int stm32_cryp_read_auth_tag(struct stm32_cryp *cryp);
252 static void stm32_cryp_finish_req(struct stm32_cryp *cryp, int err);
254 static struct stm32_cryp *stm32_cryp_find_dev(struct stm32_cryp_ctx *ctx)
256 struct stm32_cryp *tmp, *cryp = NULL;
258 spin_lock_bh(&cryp_list.lock);
260 list_for_each_entry(tmp, &cryp_list.dev_list, list) {
269 spin_unlock_bh(&cryp_list.lock);
274 static void stm32_cryp_hw_write_iv(struct stm32_cryp *cryp, __be32 *iv)
279 stm32_cryp_write(cryp, CRYP_IV0LR, be32_to_cpu(*iv++));
280 stm32_cryp_write(cryp, CRYP_IV0RR, be32_to_cpu(*iv++));
283 stm32_cryp_write(cryp, CRYP_IV1LR, be32_to_cpu(*iv++));
284 stm32_cryp_write(cryp, CRYP_IV1RR, be32_to_cpu(*iv++));
288 static void stm32_cryp_get_iv(struct stm32_cryp *cryp)
290 struct skcipher_request *req = cryp->req;
291 __be32 *tmp = (void *)req->iv;
296 *tmp++ = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV0LR));
297 *tmp++ = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV0RR));
300 *tmp++ = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV1LR));
301 *tmp++ = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV1RR));
305 static void stm32_cryp_hw_write_key(struct stm32_cryp *c)
311 stm32_cryp_write(c, CRYP_K1LR, be32_to_cpu(c->ctx->key[0]));
312 stm32_cryp_write(c, CRYP_K1RR, be32_to_cpu(c->ctx->key[1]));
315 for (i = c->ctx->keylen / sizeof(u32); i > 0; i--, r_id -= 4)
316 stm32_cryp_write(c, r_id,
317 be32_to_cpu(c->ctx->key[i - 1]));
321 static u32 stm32_cryp_get_hw_mode(struct stm32_cryp *cryp)
323 if (is_aes(cryp) && is_ecb(cryp))
326 if (is_aes(cryp) && is_cbc(cryp))
329 if (is_aes(cryp) && is_ctr(cryp))
332 if (is_aes(cryp) && is_gcm(cryp))
335 if (is_aes(cryp) && is_ccm(cryp))
338 if (is_des(cryp) && is_ecb(cryp))
341 if (is_des(cryp) && is_cbc(cryp))
344 if (is_tdes(cryp) && is_ecb(cryp))
347 if (is_tdes(cryp) && is_cbc(cryp))
350 dev_err(cryp->dev, "Unknown mode\n");
351 return CR_AES_UNKNOWN;
354 static unsigned int stm32_cryp_get_input_text_len(struct stm32_cryp *cryp)
356 return is_encrypt(cryp) ? cryp->areq->cryptlen :
357 cryp->areq->cryptlen - cryp->authsize;
360 static int stm32_cryp_gcm_init(struct stm32_cryp *cryp, u32 cfg)
366 memcpy(iv, cryp->areq->iv, 12);
367 iv[3] = cpu_to_be32(GCM_CTR_INIT);
368 cryp->gcm_ctr = GCM_CTR_INIT;
369 stm32_cryp_hw_write_iv(cryp, iv);
371 stm32_cryp_write(cryp, CRYP_CR, cfg | CR_PH_INIT | CR_CRYPEN);
373 /* Wait for end of processing */
374 ret = stm32_cryp_wait_enable(cryp);
376 dev_err(cryp->dev, "Timeout (gcm init)\n");
380 /* Prepare next phase */
381 if (cryp->areq->assoclen) {
383 stm32_cryp_write(cryp, CRYP_CR, cfg);
384 } else if (stm32_cryp_get_input_text_len(cryp)) {
385 cfg |= CR_PH_PAYLOAD;
386 stm32_cryp_write(cryp, CRYP_CR, cfg);
392 static void stm32_crypt_gcmccm_end_header(struct stm32_cryp *cryp)
397 /* Check if whole header written */
398 if (!cryp->header_in) {
399 /* Wait for completion */
400 err = stm32_cryp_wait_busy(cryp);
402 dev_err(cryp->dev, "Timeout (gcm/ccm header)\n");
403 stm32_cryp_write(cryp, CRYP_IMSCR, 0);
404 stm32_cryp_finish_req(cryp, err);
408 if (stm32_cryp_get_input_text_len(cryp)) {
409 /* Phase 3 : payload */
410 cfg = stm32_cryp_read(cryp, CRYP_CR);
412 stm32_cryp_write(cryp, CRYP_CR, cfg);
415 cfg |= CR_PH_PAYLOAD | CR_CRYPEN;
416 stm32_cryp_write(cryp, CRYP_CR, cfg);
420 * Nothing to read, nothing to write, caller have to
427 static void stm32_cryp_write_ccm_first_header(struct stm32_cryp *cryp)
432 u32 alen = cryp->areq->assoclen;
433 u32 block[AES_BLOCK_32] = {0};
434 u8 *b8 = (u8 *)block;
437 /* Write first u32 of B1 */
438 b8[0] = (alen >> 8) & 0xFF;
442 /* Build the two first u32 of B1 */
445 b8[2] = (alen & 0xFF000000) >> 24;
446 b8[3] = (alen & 0x00FF0000) >> 16;
447 b8[4] = (alen & 0x0000FF00) >> 8;
448 b8[5] = alen & 0x000000FF;
452 written = min_t(size_t, AES_BLOCK_SIZE - len, alen);
454 scatterwalk_copychunks((char *)block + len, &cryp->in_walk, written, 0);
455 for (i = 0; i < AES_BLOCK_32; i++)
456 stm32_cryp_write(cryp, CRYP_DIN, block[i]);
458 cryp->header_in -= written;
460 stm32_crypt_gcmccm_end_header(cryp);
463 static int stm32_cryp_ccm_init(struct stm32_cryp *cryp, u32 cfg)
466 u32 iv_32[AES_BLOCK_32], b0_32[AES_BLOCK_32];
467 u8 *iv = (u8 *)iv_32, *b0 = (u8 *)b0_32;
470 unsigned int i, textlen;
472 /* Phase 1 : init. Firstly set the CTR value to 1 (not 0) */
473 memcpy(iv, cryp->areq->iv, AES_BLOCK_SIZE);
474 memset(iv + AES_BLOCK_SIZE - 1 - iv[0], 0, iv[0] + 1);
475 iv[AES_BLOCK_SIZE - 1] = 1;
476 stm32_cryp_hw_write_iv(cryp, (__be32 *)iv);
479 memcpy(b0, iv, AES_BLOCK_SIZE);
481 b0[0] |= (8 * ((cryp->authsize - 2) / 2));
483 if (cryp->areq->assoclen)
486 textlen = stm32_cryp_get_input_text_len(cryp);
488 b0[AES_BLOCK_SIZE - 2] = textlen >> 8;
489 b0[AES_BLOCK_SIZE - 1] = textlen & 0xFF;
492 stm32_cryp_write(cryp, CRYP_CR, cfg | CR_PH_INIT | CR_CRYPEN);
498 for (i = 0; i < AES_BLOCK_32; i++) {
501 if (!cryp->caps->padding_wa)
502 xd = be32_to_cpu(bd[i]);
503 stm32_cryp_write(cryp, CRYP_DIN, xd);
506 /* Wait for end of processing */
507 ret = stm32_cryp_wait_enable(cryp);
509 dev_err(cryp->dev, "Timeout (ccm init)\n");
513 /* Prepare next phase */
514 if (cryp->areq->assoclen) {
515 cfg |= CR_PH_HEADER | CR_CRYPEN;
516 stm32_cryp_write(cryp, CRYP_CR, cfg);
518 /* Write first (special) block (may move to next phase [payload]) */
519 stm32_cryp_write_ccm_first_header(cryp);
520 } else if (stm32_cryp_get_input_text_len(cryp)) {
521 cfg |= CR_PH_PAYLOAD;
522 stm32_cryp_write(cryp, CRYP_CR, cfg);
528 static int stm32_cryp_hw_init(struct stm32_cryp *cryp)
533 pm_runtime_get_sync(cryp->dev);
535 /* Disable interrupt */
536 stm32_cryp_write(cryp, CRYP_IMSCR, 0);
539 stm32_cryp_hw_write_key(cryp);
541 /* Set configuration */
542 cfg = CR_DATA8 | CR_FFLUSH;
544 switch (cryp->ctx->keylen) {
545 case AES_KEYSIZE_128:
549 case AES_KEYSIZE_192:
554 case AES_KEYSIZE_256:
559 hw_mode = stm32_cryp_get_hw_mode(cryp);
560 if (hw_mode == CR_AES_UNKNOWN)
563 /* AES ECB/CBC decrypt: run key preparation first */
564 if (is_decrypt(cryp) &&
565 ((hw_mode == CR_AES_ECB) || (hw_mode == CR_AES_CBC))) {
566 stm32_cryp_write(cryp, CRYP_CR, cfg | CR_AES_KP | CR_CRYPEN);
568 /* Wait for end of processing */
569 ret = stm32_cryp_wait_busy(cryp);
571 dev_err(cryp->dev, "Timeout (key preparation)\n");
578 if (is_decrypt(cryp))
579 cfg |= CR_DEC_NOT_ENC;
581 /* Apply config and flush (valid when CRYPEN = 0) */
582 stm32_cryp_write(cryp, CRYP_CR, cfg);
588 if (hw_mode == CR_AES_CCM)
589 ret = stm32_cryp_ccm_init(cryp, cfg);
591 ret = stm32_cryp_gcm_init(cryp, cfg);
602 stm32_cryp_hw_write_iv(cryp, (__be32 *)cryp->req->iv);
612 stm32_cryp_write(cryp, CRYP_CR, cfg);
617 static void stm32_cryp_finish_req(struct stm32_cryp *cryp, int err)
619 if (!err && (is_gcm(cryp) || is_ccm(cryp)))
620 /* Phase 4 : output tag */
621 err = stm32_cryp_read_auth_tag(cryp);
623 if (!err && (!(is_gcm(cryp) || is_ccm(cryp) || is_ecb(cryp))))
624 stm32_cryp_get_iv(cryp);
626 pm_runtime_mark_last_busy(cryp->dev);
627 pm_runtime_put_autosuspend(cryp->dev);
629 if (is_gcm(cryp) || is_ccm(cryp))
630 crypto_finalize_aead_request(cryp->engine, cryp->areq, err);
632 crypto_finalize_skcipher_request(cryp->engine, cryp->req,
636 static int stm32_cryp_cpu_start(struct stm32_cryp *cryp)
638 /* Enable interrupt and let the IRQ handler do everything */
639 stm32_cryp_write(cryp, CRYP_IMSCR, IMSCR_IN | IMSCR_OUT);
644 static int stm32_cryp_cipher_one_req(struct crypto_engine *engine, void *areq);
645 static int stm32_cryp_prepare_cipher_req(struct crypto_engine *engine,
648 static int stm32_cryp_init_tfm(struct crypto_skcipher *tfm)
650 struct stm32_cryp_ctx *ctx = crypto_skcipher_ctx(tfm);
652 crypto_skcipher_set_reqsize(tfm, sizeof(struct stm32_cryp_reqctx));
654 ctx->enginectx.op.do_one_request = stm32_cryp_cipher_one_req;
655 ctx->enginectx.op.prepare_request = stm32_cryp_prepare_cipher_req;
656 ctx->enginectx.op.unprepare_request = NULL;
660 static int stm32_cryp_aead_one_req(struct crypto_engine *engine, void *areq);
661 static int stm32_cryp_prepare_aead_req(struct crypto_engine *engine,
664 static int stm32_cryp_aes_aead_init(struct crypto_aead *tfm)
666 struct stm32_cryp_ctx *ctx = crypto_aead_ctx(tfm);
668 tfm->reqsize = sizeof(struct stm32_cryp_reqctx);
670 ctx->enginectx.op.do_one_request = stm32_cryp_aead_one_req;
671 ctx->enginectx.op.prepare_request = stm32_cryp_prepare_aead_req;
672 ctx->enginectx.op.unprepare_request = NULL;
677 static int stm32_cryp_crypt(struct skcipher_request *req, unsigned long mode)
679 struct stm32_cryp_ctx *ctx = crypto_skcipher_ctx(
680 crypto_skcipher_reqtfm(req));
681 struct stm32_cryp_reqctx *rctx = skcipher_request_ctx(req);
682 struct stm32_cryp *cryp = stm32_cryp_find_dev(ctx);
689 return crypto_transfer_skcipher_request_to_engine(cryp->engine, req);
692 static int stm32_cryp_aead_crypt(struct aead_request *req, unsigned long mode)
694 struct stm32_cryp_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req));
695 struct stm32_cryp_reqctx *rctx = aead_request_ctx(req);
696 struct stm32_cryp *cryp = stm32_cryp_find_dev(ctx);
703 return crypto_transfer_aead_request_to_engine(cryp->engine, req);
706 static int stm32_cryp_setkey(struct crypto_skcipher *tfm, const u8 *key,
709 struct stm32_cryp_ctx *ctx = crypto_skcipher_ctx(tfm);
711 memcpy(ctx->key, key, keylen);
712 ctx->keylen = keylen;
717 static int stm32_cryp_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
720 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
721 keylen != AES_KEYSIZE_256)
724 return stm32_cryp_setkey(tfm, key, keylen);
727 static int stm32_cryp_des_setkey(struct crypto_skcipher *tfm, const u8 *key,
730 return verify_skcipher_des_key(tfm, key) ?:
731 stm32_cryp_setkey(tfm, key, keylen);
734 static int stm32_cryp_tdes_setkey(struct crypto_skcipher *tfm, const u8 *key,
737 return verify_skcipher_des3_key(tfm, key) ?:
738 stm32_cryp_setkey(tfm, key, keylen);
741 static int stm32_cryp_aes_aead_setkey(struct crypto_aead *tfm, const u8 *key,
744 struct stm32_cryp_ctx *ctx = crypto_aead_ctx(tfm);
746 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
747 keylen != AES_KEYSIZE_256)
750 memcpy(ctx->key, key, keylen);
751 ctx->keylen = keylen;
756 static int stm32_cryp_aes_gcm_setauthsize(struct crypto_aead *tfm,
757 unsigned int authsize)
775 static int stm32_cryp_aes_ccm_setauthsize(struct crypto_aead *tfm,
776 unsigned int authsize)
794 static int stm32_cryp_aes_ecb_encrypt(struct skcipher_request *req)
796 if (req->cryptlen % AES_BLOCK_SIZE)
799 if (req->cryptlen == 0)
802 return stm32_cryp_crypt(req, FLG_AES | FLG_ECB | FLG_ENCRYPT);
805 static int stm32_cryp_aes_ecb_decrypt(struct skcipher_request *req)
807 if (req->cryptlen % AES_BLOCK_SIZE)
810 if (req->cryptlen == 0)
813 return stm32_cryp_crypt(req, FLG_AES | FLG_ECB);
816 static int stm32_cryp_aes_cbc_encrypt(struct skcipher_request *req)
818 if (req->cryptlen % AES_BLOCK_SIZE)
821 if (req->cryptlen == 0)
824 return stm32_cryp_crypt(req, FLG_AES | FLG_CBC | FLG_ENCRYPT);
827 static int stm32_cryp_aes_cbc_decrypt(struct skcipher_request *req)
829 if (req->cryptlen % AES_BLOCK_SIZE)
832 if (req->cryptlen == 0)
835 return stm32_cryp_crypt(req, FLG_AES | FLG_CBC);
838 static int stm32_cryp_aes_ctr_encrypt(struct skcipher_request *req)
840 if (req->cryptlen == 0)
843 return stm32_cryp_crypt(req, FLG_AES | FLG_CTR | FLG_ENCRYPT);
846 static int stm32_cryp_aes_ctr_decrypt(struct skcipher_request *req)
848 if (req->cryptlen == 0)
851 return stm32_cryp_crypt(req, FLG_AES | FLG_CTR);
854 static int stm32_cryp_aes_gcm_encrypt(struct aead_request *req)
856 return stm32_cryp_aead_crypt(req, FLG_AES | FLG_GCM | FLG_ENCRYPT);
859 static int stm32_cryp_aes_gcm_decrypt(struct aead_request *req)
861 return stm32_cryp_aead_crypt(req, FLG_AES | FLG_GCM);
864 static inline int crypto_ccm_check_iv(const u8 *iv)
866 /* 2 <= L <= 8, so 1 <= L' <= 7. */
867 if (iv[0] < 1 || iv[0] > 7)
873 static int stm32_cryp_aes_ccm_encrypt(struct aead_request *req)
877 err = crypto_ccm_check_iv(req->iv);
881 return stm32_cryp_aead_crypt(req, FLG_AES | FLG_CCM | FLG_ENCRYPT);
884 static int stm32_cryp_aes_ccm_decrypt(struct aead_request *req)
888 err = crypto_ccm_check_iv(req->iv);
892 return stm32_cryp_aead_crypt(req, FLG_AES | FLG_CCM);
895 static int stm32_cryp_des_ecb_encrypt(struct skcipher_request *req)
897 if (req->cryptlen % DES_BLOCK_SIZE)
900 if (req->cryptlen == 0)
903 return stm32_cryp_crypt(req, FLG_DES | FLG_ECB | FLG_ENCRYPT);
906 static int stm32_cryp_des_ecb_decrypt(struct skcipher_request *req)
908 if (req->cryptlen % DES_BLOCK_SIZE)
911 if (req->cryptlen == 0)
914 return stm32_cryp_crypt(req, FLG_DES | FLG_ECB);
917 static int stm32_cryp_des_cbc_encrypt(struct skcipher_request *req)
919 if (req->cryptlen % DES_BLOCK_SIZE)
922 if (req->cryptlen == 0)
925 return stm32_cryp_crypt(req, FLG_DES | FLG_CBC | FLG_ENCRYPT);
928 static int stm32_cryp_des_cbc_decrypt(struct skcipher_request *req)
930 if (req->cryptlen % DES_BLOCK_SIZE)
933 if (req->cryptlen == 0)
936 return stm32_cryp_crypt(req, FLG_DES | FLG_CBC);
939 static int stm32_cryp_tdes_ecb_encrypt(struct skcipher_request *req)
941 if (req->cryptlen % DES_BLOCK_SIZE)
944 if (req->cryptlen == 0)
947 return stm32_cryp_crypt(req, FLG_TDES | FLG_ECB | FLG_ENCRYPT);
950 static int stm32_cryp_tdes_ecb_decrypt(struct skcipher_request *req)
952 if (req->cryptlen % DES_BLOCK_SIZE)
955 if (req->cryptlen == 0)
958 return stm32_cryp_crypt(req, FLG_TDES | FLG_ECB);
961 static int stm32_cryp_tdes_cbc_encrypt(struct skcipher_request *req)
963 if (req->cryptlen % DES_BLOCK_SIZE)
966 if (req->cryptlen == 0)
969 return stm32_cryp_crypt(req, FLG_TDES | FLG_CBC | FLG_ENCRYPT);
972 static int stm32_cryp_tdes_cbc_decrypt(struct skcipher_request *req)
974 if (req->cryptlen % DES_BLOCK_SIZE)
977 if (req->cryptlen == 0)
980 return stm32_cryp_crypt(req, FLG_TDES | FLG_CBC);
983 static int stm32_cryp_prepare_req(struct skcipher_request *req,
984 struct aead_request *areq)
986 struct stm32_cryp_ctx *ctx;
987 struct stm32_cryp *cryp;
988 struct stm32_cryp_reqctx *rctx;
989 struct scatterlist *in_sg;
995 ctx = req ? crypto_skcipher_ctx(crypto_skcipher_reqtfm(req)) :
996 crypto_aead_ctx(crypto_aead_reqtfm(areq));
1003 rctx = req ? skcipher_request_ctx(req) : aead_request_ctx(areq);
1004 rctx->mode &= FLG_MODE_MASK;
1008 cryp->flags = (cryp->flags & ~FLG_MODE_MASK) | rctx->mode;
1009 cryp->hw_blocksize = is_aes(cryp) ? AES_BLOCK_SIZE : DES_BLOCK_SIZE;
1015 cryp->header_in = 0;
1016 cryp->payload_in = req->cryptlen;
1017 cryp->payload_out = req->cryptlen;
1021 * Length of input and output data:
1023 * INPUT = AssocData || PlainText
1024 * <- assoclen -> <- cryptlen ->
1026 * OUTPUT = AssocData || CipherText || AuthTag
1027 * <- assoclen -> <-- cryptlen --> <- authsize ->
1030 * INPUT = AssocData || CipherTex || AuthTag
1031 * <- assoclen ---> <---------- cryptlen ---------->
1033 * OUTPUT = AssocData || PlainText
1034 * <- assoclen -> <- cryptlen - authsize ->
1038 cryp->authsize = crypto_aead_authsize(crypto_aead_reqtfm(areq));
1039 if (is_encrypt(cryp)) {
1040 cryp->payload_in = areq->cryptlen;
1041 cryp->header_in = areq->assoclen;
1042 cryp->payload_out = areq->cryptlen;
1044 cryp->payload_in = areq->cryptlen - cryp->authsize;
1045 cryp->header_in = areq->assoclen;
1046 cryp->payload_out = cryp->payload_in;
1050 in_sg = req ? req->src : areq->src;
1051 scatterwalk_start(&cryp->in_walk, in_sg);
1053 cryp->out_sg = req ? req->dst : areq->dst;
1054 scatterwalk_start(&cryp->out_walk, cryp->out_sg);
1056 if (is_gcm(cryp) || is_ccm(cryp)) {
1057 /* In output, jump after assoc data */
1058 scatterwalk_copychunks(NULL, &cryp->out_walk, cryp->areq->assoclen, 2);
1062 memset(cryp->last_ctr, 0, sizeof(cryp->last_ctr));
1064 ret = stm32_cryp_hw_init(cryp);
1068 static int stm32_cryp_prepare_cipher_req(struct crypto_engine *engine,
1071 struct skcipher_request *req = container_of(areq,
1072 struct skcipher_request,
1075 return stm32_cryp_prepare_req(req, NULL);
1078 static int stm32_cryp_cipher_one_req(struct crypto_engine *engine, void *areq)
1080 struct skcipher_request *req = container_of(areq,
1081 struct skcipher_request,
1083 struct stm32_cryp_ctx *ctx = crypto_skcipher_ctx(
1084 crypto_skcipher_reqtfm(req));
1085 struct stm32_cryp *cryp = ctx->cryp;
1090 return stm32_cryp_cpu_start(cryp);
1093 static int stm32_cryp_prepare_aead_req(struct crypto_engine *engine, void *areq)
1095 struct aead_request *req = container_of(areq, struct aead_request,
1098 return stm32_cryp_prepare_req(NULL, req);
1101 static int stm32_cryp_aead_one_req(struct crypto_engine *engine, void *areq)
1103 struct aead_request *req = container_of(areq, struct aead_request,
1105 struct stm32_cryp_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req));
1106 struct stm32_cryp *cryp = ctx->cryp;
1111 if (unlikely(!cryp->payload_in && !cryp->header_in)) {
1112 /* No input data to process: get tag and finish */
1113 stm32_cryp_finish_req(cryp, 0);
1117 return stm32_cryp_cpu_start(cryp);
1120 static int stm32_cryp_read_auth_tag(struct stm32_cryp *cryp)
1127 cfg = stm32_cryp_read(cryp, CRYP_CR);
1131 cfg &= ~CR_DEC_NOT_ENC;
1134 stm32_cryp_write(cryp, CRYP_CR, cfg);
1137 /* GCM: write aad and payload size (in bits) */
1138 size_bit = cryp->areq->assoclen * 8;
1139 if (cryp->caps->swap_final)
1140 size_bit = (__force u32)cpu_to_be32(size_bit);
1142 stm32_cryp_write(cryp, CRYP_DIN, 0);
1143 stm32_cryp_write(cryp, CRYP_DIN, size_bit);
1145 size_bit = is_encrypt(cryp) ? cryp->areq->cryptlen :
1146 cryp->areq->cryptlen - cryp->authsize;
1148 if (cryp->caps->swap_final)
1149 size_bit = (__force u32)cpu_to_be32(size_bit);
1151 stm32_cryp_write(cryp, CRYP_DIN, 0);
1152 stm32_cryp_write(cryp, CRYP_DIN, size_bit);
1154 /* CCM: write CTR0 */
1155 u32 iv32[AES_BLOCK_32];
1156 u8 *iv = (u8 *)iv32;
1157 __be32 *biv = (__be32 *)iv32;
1159 memcpy(iv, cryp->areq->iv, AES_BLOCK_SIZE);
1160 memset(iv + AES_BLOCK_SIZE - 1 - iv[0], 0, iv[0] + 1);
1162 for (i = 0; i < AES_BLOCK_32; i++) {
1165 if (!cryp->caps->padding_wa)
1166 xiv = be32_to_cpu(biv[i]);
1167 stm32_cryp_write(cryp, CRYP_DIN, xiv);
1171 /* Wait for output data */
1172 ret = stm32_cryp_wait_output(cryp);
1174 dev_err(cryp->dev, "Timeout (read tag)\n");
1178 if (is_encrypt(cryp)) {
1179 u32 out_tag[AES_BLOCK_32];
1181 /* Get and write tag */
1182 for (i = 0; i < AES_BLOCK_32; i++)
1183 out_tag[i] = stm32_cryp_read(cryp, CRYP_DOUT);
1185 scatterwalk_copychunks(out_tag, &cryp->out_walk, cryp->authsize, 1);
1187 /* Get and check tag */
1188 u32 in_tag[AES_BLOCK_32], out_tag[AES_BLOCK_32];
1190 scatterwalk_copychunks(in_tag, &cryp->in_walk, cryp->authsize, 0);
1192 for (i = 0; i < AES_BLOCK_32; i++)
1193 out_tag[i] = stm32_cryp_read(cryp, CRYP_DOUT);
1195 if (crypto_memneq(in_tag, out_tag, cryp->authsize))
1201 stm32_cryp_write(cryp, CRYP_CR, cfg);
1206 static void stm32_cryp_check_ctr_counter(struct stm32_cryp *cryp)
1210 if (unlikely(cryp->last_ctr[3] == cpu_to_be32(0xFFFFFFFF))) {
1212 * In this case, we need to increment manually the ctr counter,
1213 * as HW doesn't handle the U32 carry.
1215 crypto_inc((u8 *)cryp->last_ctr, sizeof(cryp->last_ctr));
1217 cr = stm32_cryp_read(cryp, CRYP_CR);
1218 stm32_cryp_write(cryp, CRYP_CR, cr & ~CR_CRYPEN);
1220 stm32_cryp_hw_write_iv(cryp, cryp->last_ctr);
1222 stm32_cryp_write(cryp, CRYP_CR, cr);
1225 /* The IV registers are BE */
1226 cryp->last_ctr[0] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV0LR));
1227 cryp->last_ctr[1] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV0RR));
1228 cryp->last_ctr[2] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV1LR));
1229 cryp->last_ctr[3] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV1RR));
1232 static void stm32_cryp_irq_read_data(struct stm32_cryp *cryp)
1235 u32 block[AES_BLOCK_32];
1237 for (i = 0; i < cryp->hw_blocksize / sizeof(u32); i++)
1238 block[i] = stm32_cryp_read(cryp, CRYP_DOUT);
1240 scatterwalk_copychunks(block, &cryp->out_walk, min_t(size_t, cryp->hw_blocksize,
1241 cryp->payload_out), 1);
1242 cryp->payload_out -= min_t(size_t, cryp->hw_blocksize,
1246 static void stm32_cryp_irq_write_block(struct stm32_cryp *cryp)
1249 u32 block[AES_BLOCK_32] = {0};
1251 scatterwalk_copychunks(block, &cryp->in_walk, min_t(size_t, cryp->hw_blocksize,
1252 cryp->payload_in), 0);
1253 for (i = 0; i < cryp->hw_blocksize / sizeof(u32); i++)
1254 stm32_cryp_write(cryp, CRYP_DIN, block[i]);
1256 cryp->payload_in -= min_t(size_t, cryp->hw_blocksize, cryp->payload_in);
1259 static void stm32_cryp_irq_write_gcm_padded_data(struct stm32_cryp *cryp)
1262 u32 cfg, block[AES_BLOCK_32] = {0};
1265 /* 'Special workaround' procedure described in the datasheet */
1268 stm32_cryp_write(cryp, CRYP_IMSCR, 0);
1269 cfg = stm32_cryp_read(cryp, CRYP_CR);
1271 stm32_cryp_write(cryp, CRYP_CR, cfg);
1273 /* b) Update IV1R */
1274 stm32_cryp_write(cryp, CRYP_IV1RR, cryp->gcm_ctr - 2);
1276 /* c) change mode to CTR */
1277 cfg &= ~CR_ALGO_MASK;
1279 stm32_cryp_write(cryp, CRYP_CR, cfg);
1283 stm32_cryp_write(cryp, CRYP_CR, cfg);
1285 /* b) pad and write the last block */
1286 stm32_cryp_irq_write_block(cryp);
1287 /* wait end of process */
1288 err = stm32_cryp_wait_output(cryp);
1290 dev_err(cryp->dev, "Timeout (write gcm last data)\n");
1291 return stm32_cryp_finish_req(cryp, err);
1294 /* c) get and store encrypted data */
1296 * Same code as stm32_cryp_irq_read_data(), but we want to store
1299 for (i = 0; i < cryp->hw_blocksize / sizeof(u32); i++)
1300 block[i] = stm32_cryp_read(cryp, CRYP_DOUT);
1302 scatterwalk_copychunks(block, &cryp->out_walk, min_t(size_t, cryp->hw_blocksize,
1303 cryp->payload_out), 1);
1304 cryp->payload_out -= min_t(size_t, cryp->hw_blocksize,
1307 /* d) change mode back to AES GCM */
1308 cfg &= ~CR_ALGO_MASK;
1310 stm32_cryp_write(cryp, CRYP_CR, cfg);
1312 /* e) change phase to Final */
1315 stm32_cryp_write(cryp, CRYP_CR, cfg);
1317 /* f) write padded data */
1318 for (i = 0; i < AES_BLOCK_32; i++)
1319 stm32_cryp_write(cryp, CRYP_DIN, block[i]);
1321 /* g) Empty fifo out */
1322 err = stm32_cryp_wait_output(cryp);
1324 dev_err(cryp->dev, "Timeout (write gcm padded data)\n");
1325 return stm32_cryp_finish_req(cryp, err);
1328 for (i = 0; i < AES_BLOCK_32; i++)
1329 stm32_cryp_read(cryp, CRYP_DOUT);
1331 /* h) run the he normal Final phase */
1332 stm32_cryp_finish_req(cryp, 0);
1335 static void stm32_cryp_irq_set_npblb(struct stm32_cryp *cryp)
1339 /* disable ip, set NPBLB and reneable ip */
1340 cfg = stm32_cryp_read(cryp, CRYP_CR);
1342 stm32_cryp_write(cryp, CRYP_CR, cfg);
1344 cfg |= (cryp->hw_blocksize - cryp->payload_in) << CR_NBPBL_SHIFT;
1346 stm32_cryp_write(cryp, CRYP_CR, cfg);
1349 static void stm32_cryp_irq_write_ccm_padded_data(struct stm32_cryp *cryp)
1353 u32 cstmp1[AES_BLOCK_32], cstmp2[AES_BLOCK_32];
1354 u32 block[AES_BLOCK_32] = {0};
1357 /* 'Special workaround' procedure described in the datasheet */
1360 stm32_cryp_write(cryp, CRYP_IMSCR, 0);
1362 cfg = stm32_cryp_read(cryp, CRYP_CR);
1364 stm32_cryp_write(cryp, CRYP_CR, cfg);
1366 /* b) get IV1 from CRYP_CSGCMCCM7 */
1367 iv1tmp = stm32_cryp_read(cryp, CRYP_CSGCMCCM0R + 7 * 4);
1369 /* c) Load CRYP_CSGCMCCMxR */
1370 for (i = 0; i < ARRAY_SIZE(cstmp1); i++)
1371 cstmp1[i] = stm32_cryp_read(cryp, CRYP_CSGCMCCM0R + i * 4);
1374 stm32_cryp_write(cryp, CRYP_IV1RR, iv1tmp);
1376 /* e) change mode to CTR */
1377 cfg &= ~CR_ALGO_MASK;
1379 stm32_cryp_write(cryp, CRYP_CR, cfg);
1383 stm32_cryp_write(cryp, CRYP_CR, cfg);
1385 /* b) pad and write the last block */
1386 stm32_cryp_irq_write_block(cryp);
1387 /* wait end of process */
1388 err = stm32_cryp_wait_output(cryp);
1390 dev_err(cryp->dev, "Timeout (wite ccm padded data)\n");
1391 return stm32_cryp_finish_req(cryp, err);
1394 /* c) get and store decrypted data */
1396 * Same code as stm32_cryp_irq_read_data(), but we want to store
1399 for (i = 0; i < cryp->hw_blocksize / sizeof(u32); i++)
1400 block[i] = stm32_cryp_read(cryp, CRYP_DOUT);
1402 scatterwalk_copychunks(block, &cryp->out_walk, min_t(size_t, cryp->hw_blocksize,
1403 cryp->payload_out), 1);
1404 cryp->payload_out -= min_t(size_t, cryp->hw_blocksize, cryp->payload_out);
1406 /* d) Load again CRYP_CSGCMCCMxR */
1407 for (i = 0; i < ARRAY_SIZE(cstmp2); i++)
1408 cstmp2[i] = stm32_cryp_read(cryp, CRYP_CSGCMCCM0R + i * 4);
1410 /* e) change mode back to AES CCM */
1411 cfg &= ~CR_ALGO_MASK;
1413 stm32_cryp_write(cryp, CRYP_CR, cfg);
1415 /* f) change phase to header */
1417 cfg |= CR_PH_HEADER;
1418 stm32_cryp_write(cryp, CRYP_CR, cfg);
1420 /* g) XOR and write padded data */
1421 for (i = 0; i < ARRAY_SIZE(block); i++) {
1422 block[i] ^= cstmp1[i];
1423 block[i] ^= cstmp2[i];
1424 stm32_cryp_write(cryp, CRYP_DIN, block[i]);
1427 /* h) wait for completion */
1428 err = stm32_cryp_wait_busy(cryp);
1430 dev_err(cryp->dev, "Timeout (wite ccm padded data)\n");
1432 /* i) run the he normal Final phase */
1433 stm32_cryp_finish_req(cryp, err);
1436 static void stm32_cryp_irq_write_data(struct stm32_cryp *cryp)
1438 if (unlikely(!cryp->payload_in)) {
1439 dev_warn(cryp->dev, "No more data to process\n");
1443 if (unlikely(cryp->payload_in < AES_BLOCK_SIZE &&
1444 (stm32_cryp_get_hw_mode(cryp) == CR_AES_GCM) &&
1445 is_encrypt(cryp))) {
1446 /* Padding for AES GCM encryption */
1447 if (cryp->caps->padding_wa) {
1448 /* Special case 1 */
1449 stm32_cryp_irq_write_gcm_padded_data(cryp);
1453 /* Setting padding bytes (NBBLB) */
1454 stm32_cryp_irq_set_npblb(cryp);
1457 if (unlikely((cryp->payload_in < AES_BLOCK_SIZE) &&
1458 (stm32_cryp_get_hw_mode(cryp) == CR_AES_CCM) &&
1459 is_decrypt(cryp))) {
1460 /* Padding for AES CCM decryption */
1461 if (cryp->caps->padding_wa) {
1462 /* Special case 2 */
1463 stm32_cryp_irq_write_ccm_padded_data(cryp);
1467 /* Setting padding bytes (NBBLB) */
1468 stm32_cryp_irq_set_npblb(cryp);
1471 if (is_aes(cryp) && is_ctr(cryp))
1472 stm32_cryp_check_ctr_counter(cryp);
1474 stm32_cryp_irq_write_block(cryp);
1477 static void stm32_cryp_irq_write_gcmccm_header(struct stm32_cryp *cryp)
1480 u32 block[AES_BLOCK_32] = {0};
1483 written = min_t(size_t, AES_BLOCK_SIZE, cryp->header_in);
1485 scatterwalk_copychunks(block, &cryp->in_walk, written, 0);
1486 for (i = 0; i < AES_BLOCK_32; i++)
1487 stm32_cryp_write(cryp, CRYP_DIN, block[i]);
1489 cryp->header_in -= written;
1491 stm32_crypt_gcmccm_end_header(cryp);
1494 static irqreturn_t stm32_cryp_irq_thread(int irq, void *arg)
1496 struct stm32_cryp *cryp = arg;
1498 u32 it_mask = stm32_cryp_read(cryp, CRYP_IMSCR);
1500 if (cryp->irq_status & MISR_OUT)
1501 /* Output FIFO IRQ: read data */
1502 stm32_cryp_irq_read_data(cryp);
1504 if (cryp->irq_status & MISR_IN) {
1505 if (is_gcm(cryp) || is_ccm(cryp)) {
1506 ph = stm32_cryp_read(cryp, CRYP_CR) & CR_PH_MASK;
1507 if (unlikely(ph == CR_PH_HEADER))
1509 stm32_cryp_irq_write_gcmccm_header(cryp);
1511 /* Input FIFO IRQ: write data */
1512 stm32_cryp_irq_write_data(cryp);
1516 /* Input FIFO IRQ: write data */
1517 stm32_cryp_irq_write_data(cryp);
1521 /* Mask useless interrupts */
1522 if (!cryp->payload_in && !cryp->header_in)
1523 it_mask &= ~IMSCR_IN;
1524 if (!cryp->payload_out)
1525 it_mask &= ~IMSCR_OUT;
1526 stm32_cryp_write(cryp, CRYP_IMSCR, it_mask);
1528 if (!cryp->payload_in && !cryp->header_in && !cryp->payload_out)
1529 stm32_cryp_finish_req(cryp, 0);
1534 static irqreturn_t stm32_cryp_irq(int irq, void *arg)
1536 struct stm32_cryp *cryp = arg;
1538 cryp->irq_status = stm32_cryp_read(cryp, CRYP_MISR);
1540 return IRQ_WAKE_THREAD;
1543 static struct skcipher_alg crypto_algs[] = {
1545 .base.cra_name = "ecb(aes)",
1546 .base.cra_driver_name = "stm32-ecb-aes",
1547 .base.cra_priority = 200,
1548 .base.cra_flags = CRYPTO_ALG_ASYNC,
1549 .base.cra_blocksize = AES_BLOCK_SIZE,
1550 .base.cra_ctxsize = sizeof(struct stm32_cryp_ctx),
1551 .base.cra_alignmask = 0,
1552 .base.cra_module = THIS_MODULE,
1554 .init = stm32_cryp_init_tfm,
1555 .min_keysize = AES_MIN_KEY_SIZE,
1556 .max_keysize = AES_MAX_KEY_SIZE,
1557 .setkey = stm32_cryp_aes_setkey,
1558 .encrypt = stm32_cryp_aes_ecb_encrypt,
1559 .decrypt = stm32_cryp_aes_ecb_decrypt,
1562 .base.cra_name = "cbc(aes)",
1563 .base.cra_driver_name = "stm32-cbc-aes",
1564 .base.cra_priority = 200,
1565 .base.cra_flags = CRYPTO_ALG_ASYNC,
1566 .base.cra_blocksize = AES_BLOCK_SIZE,
1567 .base.cra_ctxsize = sizeof(struct stm32_cryp_ctx),
1568 .base.cra_alignmask = 0,
1569 .base.cra_module = THIS_MODULE,
1571 .init = stm32_cryp_init_tfm,
1572 .min_keysize = AES_MIN_KEY_SIZE,
1573 .max_keysize = AES_MAX_KEY_SIZE,
1574 .ivsize = AES_BLOCK_SIZE,
1575 .setkey = stm32_cryp_aes_setkey,
1576 .encrypt = stm32_cryp_aes_cbc_encrypt,
1577 .decrypt = stm32_cryp_aes_cbc_decrypt,
1580 .base.cra_name = "ctr(aes)",
1581 .base.cra_driver_name = "stm32-ctr-aes",
1582 .base.cra_priority = 200,
1583 .base.cra_flags = CRYPTO_ALG_ASYNC,
1584 .base.cra_blocksize = 1,
1585 .base.cra_ctxsize = sizeof(struct stm32_cryp_ctx),
1586 .base.cra_alignmask = 0,
1587 .base.cra_module = THIS_MODULE,
1589 .init = stm32_cryp_init_tfm,
1590 .min_keysize = AES_MIN_KEY_SIZE,
1591 .max_keysize = AES_MAX_KEY_SIZE,
1592 .ivsize = AES_BLOCK_SIZE,
1593 .setkey = stm32_cryp_aes_setkey,
1594 .encrypt = stm32_cryp_aes_ctr_encrypt,
1595 .decrypt = stm32_cryp_aes_ctr_decrypt,
1598 .base.cra_name = "ecb(des)",
1599 .base.cra_driver_name = "stm32-ecb-des",
1600 .base.cra_priority = 200,
1601 .base.cra_flags = CRYPTO_ALG_ASYNC,
1602 .base.cra_blocksize = DES_BLOCK_SIZE,
1603 .base.cra_ctxsize = sizeof(struct stm32_cryp_ctx),
1604 .base.cra_alignmask = 0,
1605 .base.cra_module = THIS_MODULE,
1607 .init = stm32_cryp_init_tfm,
1608 .min_keysize = DES_BLOCK_SIZE,
1609 .max_keysize = DES_BLOCK_SIZE,
1610 .setkey = stm32_cryp_des_setkey,
1611 .encrypt = stm32_cryp_des_ecb_encrypt,
1612 .decrypt = stm32_cryp_des_ecb_decrypt,
1615 .base.cra_name = "cbc(des)",
1616 .base.cra_driver_name = "stm32-cbc-des",
1617 .base.cra_priority = 200,
1618 .base.cra_flags = CRYPTO_ALG_ASYNC,
1619 .base.cra_blocksize = DES_BLOCK_SIZE,
1620 .base.cra_ctxsize = sizeof(struct stm32_cryp_ctx),
1621 .base.cra_alignmask = 0,
1622 .base.cra_module = THIS_MODULE,
1624 .init = stm32_cryp_init_tfm,
1625 .min_keysize = DES_BLOCK_SIZE,
1626 .max_keysize = DES_BLOCK_SIZE,
1627 .ivsize = DES_BLOCK_SIZE,
1628 .setkey = stm32_cryp_des_setkey,
1629 .encrypt = stm32_cryp_des_cbc_encrypt,
1630 .decrypt = stm32_cryp_des_cbc_decrypt,
1633 .base.cra_name = "ecb(des3_ede)",
1634 .base.cra_driver_name = "stm32-ecb-des3",
1635 .base.cra_priority = 200,
1636 .base.cra_flags = CRYPTO_ALG_ASYNC,
1637 .base.cra_blocksize = DES_BLOCK_SIZE,
1638 .base.cra_ctxsize = sizeof(struct stm32_cryp_ctx),
1639 .base.cra_alignmask = 0,
1640 .base.cra_module = THIS_MODULE,
1642 .init = stm32_cryp_init_tfm,
1643 .min_keysize = 3 * DES_BLOCK_SIZE,
1644 .max_keysize = 3 * DES_BLOCK_SIZE,
1645 .setkey = stm32_cryp_tdes_setkey,
1646 .encrypt = stm32_cryp_tdes_ecb_encrypt,
1647 .decrypt = stm32_cryp_tdes_ecb_decrypt,
1650 .base.cra_name = "cbc(des3_ede)",
1651 .base.cra_driver_name = "stm32-cbc-des3",
1652 .base.cra_priority = 200,
1653 .base.cra_flags = CRYPTO_ALG_ASYNC,
1654 .base.cra_blocksize = DES_BLOCK_SIZE,
1655 .base.cra_ctxsize = sizeof(struct stm32_cryp_ctx),
1656 .base.cra_alignmask = 0,
1657 .base.cra_module = THIS_MODULE,
1659 .init = stm32_cryp_init_tfm,
1660 .min_keysize = 3 * DES_BLOCK_SIZE,
1661 .max_keysize = 3 * DES_BLOCK_SIZE,
1662 .ivsize = DES_BLOCK_SIZE,
1663 .setkey = stm32_cryp_tdes_setkey,
1664 .encrypt = stm32_cryp_tdes_cbc_encrypt,
1665 .decrypt = stm32_cryp_tdes_cbc_decrypt,
1669 static struct aead_alg aead_algs[] = {
1671 .setkey = stm32_cryp_aes_aead_setkey,
1672 .setauthsize = stm32_cryp_aes_gcm_setauthsize,
1673 .encrypt = stm32_cryp_aes_gcm_encrypt,
1674 .decrypt = stm32_cryp_aes_gcm_decrypt,
1675 .init = stm32_cryp_aes_aead_init,
1677 .maxauthsize = AES_BLOCK_SIZE,
1680 .cra_name = "gcm(aes)",
1681 .cra_driver_name = "stm32-gcm-aes",
1682 .cra_priority = 200,
1683 .cra_flags = CRYPTO_ALG_ASYNC,
1685 .cra_ctxsize = sizeof(struct stm32_cryp_ctx),
1687 .cra_module = THIS_MODULE,
1691 .setkey = stm32_cryp_aes_aead_setkey,
1692 .setauthsize = stm32_cryp_aes_ccm_setauthsize,
1693 .encrypt = stm32_cryp_aes_ccm_encrypt,
1694 .decrypt = stm32_cryp_aes_ccm_decrypt,
1695 .init = stm32_cryp_aes_aead_init,
1696 .ivsize = AES_BLOCK_SIZE,
1697 .maxauthsize = AES_BLOCK_SIZE,
1700 .cra_name = "ccm(aes)",
1701 .cra_driver_name = "stm32-ccm-aes",
1702 .cra_priority = 200,
1703 .cra_flags = CRYPTO_ALG_ASYNC,
1705 .cra_ctxsize = sizeof(struct stm32_cryp_ctx),
1707 .cra_module = THIS_MODULE,
1712 static const struct stm32_cryp_caps f7_data = {
1717 static const struct stm32_cryp_caps mp1_data = {
1718 .swap_final = false,
1719 .padding_wa = false,
1722 static const struct of_device_id stm32_dt_ids[] = {
1723 { .compatible = "st,stm32f756-cryp", .data = &f7_data},
1724 { .compatible = "st,stm32mp1-cryp", .data = &mp1_data},
1727 MODULE_DEVICE_TABLE(of, stm32_dt_ids);
1729 static int stm32_cryp_probe(struct platform_device *pdev)
1731 struct device *dev = &pdev->dev;
1732 struct stm32_cryp *cryp;
1733 struct reset_control *rst;
1736 cryp = devm_kzalloc(dev, sizeof(*cryp), GFP_KERNEL);
1740 cryp->caps = of_device_get_match_data(dev);
1746 cryp->regs = devm_platform_ioremap_resource(pdev, 0);
1747 if (IS_ERR(cryp->regs))
1748 return PTR_ERR(cryp->regs);
1750 irq = platform_get_irq(pdev, 0);
1754 ret = devm_request_threaded_irq(dev, irq, stm32_cryp_irq,
1755 stm32_cryp_irq_thread, IRQF_ONESHOT,
1756 dev_name(dev), cryp);
1758 dev_err(dev, "Cannot grab IRQ\n");
1762 cryp->clk = devm_clk_get(dev, NULL);
1763 if (IS_ERR(cryp->clk)) {
1764 dev_err(dev, "Could not get clock\n");
1765 return PTR_ERR(cryp->clk);
1768 ret = clk_prepare_enable(cryp->clk);
1770 dev_err(cryp->dev, "Failed to enable clock\n");
1774 pm_runtime_set_autosuspend_delay(dev, CRYP_AUTOSUSPEND_DELAY);
1775 pm_runtime_use_autosuspend(dev);
1777 pm_runtime_get_noresume(dev);
1778 pm_runtime_set_active(dev);
1779 pm_runtime_enable(dev);
1781 rst = devm_reset_control_get(dev, NULL);
1783 reset_control_assert(rst);
1785 reset_control_deassert(rst);
1788 platform_set_drvdata(pdev, cryp);
1790 spin_lock(&cryp_list.lock);
1791 list_add(&cryp->list, &cryp_list.dev_list);
1792 spin_unlock(&cryp_list.lock);
1794 /* Initialize crypto engine */
1795 cryp->engine = crypto_engine_alloc_init(dev, 1);
1796 if (!cryp->engine) {
1797 dev_err(dev, "Could not init crypto engine\n");
1802 ret = crypto_engine_start(cryp->engine);
1804 dev_err(dev, "Could not start crypto engine\n");
1808 ret = crypto_register_skciphers(crypto_algs, ARRAY_SIZE(crypto_algs));
1810 dev_err(dev, "Could not register algs\n");
1814 ret = crypto_register_aeads(aead_algs, ARRAY_SIZE(aead_algs));
1818 dev_info(dev, "Initialized\n");
1820 pm_runtime_put_sync(dev);
1825 crypto_unregister_skciphers(crypto_algs, ARRAY_SIZE(crypto_algs));
1828 crypto_engine_exit(cryp->engine);
1830 spin_lock(&cryp_list.lock);
1831 list_del(&cryp->list);
1832 spin_unlock(&cryp_list.lock);
1834 pm_runtime_disable(dev);
1835 pm_runtime_put_noidle(dev);
1837 clk_disable_unprepare(cryp->clk);
1842 static int stm32_cryp_remove(struct platform_device *pdev)
1844 struct stm32_cryp *cryp = platform_get_drvdata(pdev);
1850 ret = pm_runtime_resume_and_get(cryp->dev);
1854 crypto_unregister_aeads(aead_algs, ARRAY_SIZE(aead_algs));
1855 crypto_unregister_skciphers(crypto_algs, ARRAY_SIZE(crypto_algs));
1857 crypto_engine_exit(cryp->engine);
1859 spin_lock(&cryp_list.lock);
1860 list_del(&cryp->list);
1861 spin_unlock(&cryp_list.lock);
1863 pm_runtime_disable(cryp->dev);
1864 pm_runtime_put_noidle(cryp->dev);
1866 clk_disable_unprepare(cryp->clk);
1872 static int stm32_cryp_runtime_suspend(struct device *dev)
1874 struct stm32_cryp *cryp = dev_get_drvdata(dev);
1876 clk_disable_unprepare(cryp->clk);
1881 static int stm32_cryp_runtime_resume(struct device *dev)
1883 struct stm32_cryp *cryp = dev_get_drvdata(dev);
1886 ret = clk_prepare_enable(cryp->clk);
1888 dev_err(cryp->dev, "Failed to prepare_enable clock\n");
1896 static const struct dev_pm_ops stm32_cryp_pm_ops = {
1897 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1898 pm_runtime_force_resume)
1899 SET_RUNTIME_PM_OPS(stm32_cryp_runtime_suspend,
1900 stm32_cryp_runtime_resume, NULL)
1903 static struct platform_driver stm32_cryp_driver = {
1904 .probe = stm32_cryp_probe,
1905 .remove = stm32_cryp_remove,
1907 .name = DRIVER_NAME,
1908 .pm = &stm32_cryp_pm_ops,
1909 .of_match_table = stm32_dt_ids,
1913 module_platform_driver(stm32_cryp_driver);
1915 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
1916 MODULE_DESCRIPTION("STMicrolectronics STM32 CRYP hardware driver");
1917 MODULE_LICENSE("GPL");