1 // SPDX-License-Identifier: GPL-2.0
5 * Support for StarFive hardware cryptographic engine.
6 * Copyright (c) 2022 StarFive Technology
10 #include <crypto/engine.h>
11 #include "jh7110-cryp.h"
12 #include <linux/clk.h>
13 #include <linux/completion.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/mod_devicetable.h>
19 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/reset.h>
23 #include <linux/spinlock.h>
25 #define DRIVER_NAME "jh7110-crypto"
27 struct starfive_dev_list {
28 struct list_head dev_list;
29 spinlock_t lock; /* protect dev_list */
32 static struct starfive_dev_list dev_list = {
33 .dev_list = LIST_HEAD_INIT(dev_list.dev_list),
34 .lock = __SPIN_LOCK_UNLOCKED(dev_list.lock),
37 struct starfive_cryp_dev *starfive_cryp_find_dev(struct starfive_cryp_ctx *ctx)
39 struct starfive_cryp_dev *cryp = NULL, *tmp;
41 spin_lock_bh(&dev_list.lock);
43 list_for_each_entry(tmp, &dev_list.dev_list, list) {
52 spin_unlock_bh(&dev_list.lock);
58 module_param(side_chan, ushort, 0);
59 MODULE_PARM_DESC(side_chan, "Enable side channel mitigation for AES module.\n"
60 "Enabling this feature will reduce speed performance.\n"
64 static int starfive_dma_init(struct starfive_cryp_dev *cryp)
69 dma_cap_set(DMA_SLAVE, mask);
71 cryp->tx = dma_request_chan(cryp->dev, "tx");
73 return dev_err_probe(cryp->dev, PTR_ERR(cryp->tx),
74 "Error requesting tx dma channel.\n");
76 cryp->rx = dma_request_chan(cryp->dev, "rx");
77 if (IS_ERR(cryp->rx)) {
78 dma_release_channel(cryp->tx);
79 return dev_err_probe(cryp->dev, PTR_ERR(cryp->rx),
80 "Error requesting rx dma channel.\n");
86 static void starfive_dma_cleanup(struct starfive_cryp_dev *cryp)
88 dma_release_channel(cryp->tx);
89 dma_release_channel(cryp->rx);
92 static irqreturn_t starfive_cryp_irq(int irq, void *priv)
96 struct starfive_cryp_dev *cryp = (struct starfive_cryp_dev *)priv;
98 mask = readl(cryp->base + STARFIVE_IE_MASK_OFFSET);
99 status = readl(cryp->base + STARFIVE_IE_FLAG_OFFSET);
100 if (status & STARFIVE_IE_FLAG_AES_DONE) {
101 mask |= STARFIVE_IE_MASK_AES_DONE;
102 writel(mask, cryp->base + STARFIVE_IE_MASK_OFFSET);
103 tasklet_schedule(&cryp->aes_done);
106 if (status & STARFIVE_IE_FLAG_HASH_DONE) {
107 mask |= STARFIVE_IE_MASK_HASH_DONE;
108 writel(mask, cryp->base + STARFIVE_IE_MASK_OFFSET);
109 tasklet_schedule(&cryp->hash_done);
115 static int starfive_cryp_probe(struct platform_device *pdev)
117 struct starfive_cryp_dev *cryp;
118 struct resource *res;
122 cryp = devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL);
126 platform_set_drvdata(pdev, cryp);
127 cryp->dev = &pdev->dev;
129 cryp->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
130 if (IS_ERR(cryp->base))
131 return dev_err_probe(&pdev->dev, PTR_ERR(cryp->base),
132 "Error remapping memory for platform device\n");
134 tasklet_init(&cryp->aes_done, starfive_aes_done_task, (unsigned long)cryp);
135 tasklet_init(&cryp->hash_done, starfive_hash_done_task, (unsigned long)cryp);
137 cryp->phys_base = res->start;
138 cryp->dma_maxburst = 32;
139 cryp->side_chan = side_chan;
141 cryp->hclk = devm_clk_get(&pdev->dev, "hclk");
142 if (IS_ERR(cryp->hclk))
143 return dev_err_probe(&pdev->dev, PTR_ERR(cryp->hclk),
144 "Error getting hardware reference clock\n");
146 cryp->ahb = devm_clk_get(&pdev->dev, "ahb");
147 if (IS_ERR(cryp->ahb))
148 return dev_err_probe(&pdev->dev, PTR_ERR(cryp->ahb),
149 "Error getting ahb reference clock\n");
151 cryp->rst = devm_reset_control_get_shared(cryp->dev, NULL);
152 if (IS_ERR(cryp->rst))
153 return dev_err_probe(&pdev->dev, PTR_ERR(cryp->rst),
154 "Error getting hardware reset line\n");
156 irq = platform_get_irq(pdev, 0);
160 ret = devm_request_irq(&pdev->dev, irq, starfive_cryp_irq, 0, pdev->name,
163 return dev_err_probe(&pdev->dev, ret,
164 "Failed to register interrupt handler\n");
166 clk_prepare_enable(cryp->hclk);
167 clk_prepare_enable(cryp->ahb);
168 reset_control_deassert(cryp->rst);
170 spin_lock(&dev_list.lock);
171 list_add(&cryp->list, &dev_list.dev_list);
172 spin_unlock(&dev_list.lock);
174 ret = starfive_dma_init(cryp);
178 /* Initialize crypto engine */
179 cryp->engine = crypto_engine_alloc_init(&pdev->dev, 1);
185 ret = crypto_engine_start(cryp->engine);
187 goto err_engine_start;
189 ret = starfive_aes_register_algs();
193 ret = starfive_hash_register_algs();
197 ret = starfive_rsa_register_algs();
204 starfive_hash_unregister_algs();
206 starfive_aes_unregister_algs();
208 crypto_engine_stop(cryp->engine);
210 crypto_engine_exit(cryp->engine);
212 starfive_dma_cleanup(cryp);
214 spin_lock(&dev_list.lock);
215 list_del(&cryp->list);
216 spin_unlock(&dev_list.lock);
218 clk_disable_unprepare(cryp->hclk);
219 clk_disable_unprepare(cryp->ahb);
220 reset_control_assert(cryp->rst);
222 tasklet_kill(&cryp->aes_done);
223 tasklet_kill(&cryp->hash_done);
228 static void starfive_cryp_remove(struct platform_device *pdev)
230 struct starfive_cryp_dev *cryp = platform_get_drvdata(pdev);
232 starfive_aes_unregister_algs();
233 starfive_hash_unregister_algs();
234 starfive_rsa_unregister_algs();
236 tasklet_kill(&cryp->aes_done);
237 tasklet_kill(&cryp->hash_done);
239 crypto_engine_stop(cryp->engine);
240 crypto_engine_exit(cryp->engine);
242 starfive_dma_cleanup(cryp);
244 spin_lock(&dev_list.lock);
245 list_del(&cryp->list);
246 spin_unlock(&dev_list.lock);
248 clk_disable_unprepare(cryp->hclk);
249 clk_disable_unprepare(cryp->ahb);
250 reset_control_assert(cryp->rst);
253 static const struct of_device_id starfive_dt_ids[] __maybe_unused = {
254 { .compatible = "starfive,jh7110-crypto", .data = NULL},
257 MODULE_DEVICE_TABLE(of, starfive_dt_ids);
259 static struct platform_driver starfive_cryp_driver = {
260 .probe = starfive_cryp_probe,
261 .remove_new = starfive_cryp_remove,
264 .of_match_table = starfive_dt_ids,
268 module_platform_driver(starfive_cryp_driver);
270 MODULE_LICENSE("GPL");
271 MODULE_DESCRIPTION("StarFive JH7110 Cryptographic Module");