drivers/crypto/qce/sha.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/device.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/interrupt.h>
   9 #include <crypto/internal/hash.h>
  10
  11 #include "common.h"
  12 #include "core.h"
  13 #include "sha.h"
  14
  15 /* crypto hw padding constant for first operation */
  16 #define SHA_PADDING             64
  17 #define SHA_PADDING_MASK        (SHA_PADDING - 1)
  18
  19 static LIST_HEAD(ahash_algs);
  20
  21 static const u32 std_iv_sha1[SHA256_DIGEST_SIZE / sizeof(u32)] = {
  22         SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4, 0, 0, 0
  23 };
  24
  25 static const u32 std_iv_sha256[SHA256_DIGEST_SIZE / sizeof(u32)] = {
  26         SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3,
  27         SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7
  28 };
  29
  30 static void qce_ahash_done(void *data)
  31 {
  32         struct crypto_async_request *async_req = data;
  33         struct ahash_request *req = ahash_request_cast(async_req);
  34         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
  35         struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  36         struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
  37         struct qce_device *qce = tmpl->qce;
  38         struct qce_result_dump *result = qce->dma.result_buf;
  39         unsigned int digestsize = crypto_ahash_digestsize(ahash);
  40         int error;
  41         u32 status;
  42
  43         error = qce_dma_terminate_all(&qce->dma);
  44         if (error)
  45                 dev_dbg(qce->dev, "ahash dma termination error (%d)\n", error);
  46
  47         dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
  48         dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
  49
  50         memcpy(rctx->digest, result->auth_iv, digestsize);
  51         if (req->result)
  52                 memcpy(req->result, result->auth_iv, digestsize);
  53
  54         rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]);
  55         rctx->byte_count[1] = cpu_to_be32(result->auth_byte_count[1]);
  56
  57         error = qce_check_status(qce, &status);
  58         if (error < 0)
  59                 dev_dbg(qce->dev, "ahash operation error (%x)\n", status);
  60
  61         req->src = rctx->src_orig;
  62         req->nbytes = rctx->nbytes_orig;
  63         rctx->last_blk = false;
  64         rctx->first_blk = false;
  65
  66         qce->async_req_done(tmpl->qce, error);
  67 }
  68
  69 static int qce_ahash_async_req_handle(struct crypto_async_request *async_req)
  70 {
  71         struct ahash_request *req = ahash_request_cast(async_req);
  72         struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
  73         struct qce_sha_ctx *ctx = crypto_tfm_ctx(async_req->tfm);
  74         struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
  75         struct qce_device *qce = tmpl->qce;
  76         unsigned long flags = rctx->flags;
  77         int ret;
  78
  79         if (IS_SHA_HMAC(flags)) {
  80                 rctx->authkey = ctx->authkey;
  81                 rctx->authklen = QCE_SHA_HMAC_KEY_SIZE;
  82         } else if (IS_CMAC(flags)) {
  83                 rctx->authkey = ctx->authkey;
  84                 rctx->authklen = AES_KEYSIZE_128;
  85         }
  86
  87         rctx->src_nents = sg_nents_for_len(req->src, req->nbytes);
  88         if (rctx->src_nents < 0) {
  89                 dev_err(qce->dev, "Invalid numbers of src SG.\n");
  90                 return rctx->src_nents;
  91         }
  92
  93         ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
  94         if (ret < 0)
  95                 return ret;
  96
  97         sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
  98
  99         ret = dma_map_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
 100         if (ret < 0)
 101                 goto error_unmap_src;
 102
 103         ret = qce_dma_prep_sgs(&qce->dma, req->src, rctx->src_nents,
 104                                &rctx->result_sg, 1, qce_ahash_done, async_req);
 105         if (ret)
 106                 goto error_unmap_dst;
 107
 108         qce_dma_issue_pending(&qce->dma);
 109
 110         ret = qce_start(async_req, tmpl->crypto_alg_type, 0, 0);
 111         if (ret)
 112                 goto error_terminate;
 113
 114         return 0;
 115
 116 error_terminate:
 117         qce_dma_terminate_all(&qce->dma);
 118 error_unmap_dst:
 119         dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
 120 error_unmap_src:
 121         dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
 122         return ret;
 123 }
 124
 125 static int qce_ahash_init(struct ahash_request *req)
 126 {
 127         struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
 128         struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
 129         const u32 *std_iv = tmpl->std_iv;
 130
 131         memset(rctx, 0, sizeof(*rctx));
 132         rctx->first_blk = true;
 133         rctx->last_blk = false;
 134         rctx->flags = tmpl->alg_flags;
 135         memcpy(rctx->digest, std_iv, sizeof(rctx->digest));
 136
 137         return 0;
 138 }
 139
 140 static int qce_ahash_export(struct ahash_request *req, void *out)
 141 {
 142         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 143         struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
 144         unsigned long flags = rctx->flags;
 145         unsigned int digestsize = crypto_ahash_digestsize(ahash);
 146         unsigned int blocksize =
 147                         crypto_tfm_alg_blocksize(crypto_ahash_tfm(ahash));
 148
 149         if (IS_SHA1(flags) || IS_SHA1_HMAC(flags)) {
 150                 struct sha1_state *out_state = out;
 151
 152                 out_state->count = rctx->count;
 153                 qce_cpu_to_be32p_array((__be32 *)out_state->state,
 154                                        rctx->digest, digestsize);
 155                 memcpy(out_state->buffer, rctx->buf, blocksize);
 156         } else if (IS_SHA256(flags) || IS_SHA256_HMAC(flags)) {
 157                 struct sha256_state *out_state = out;
 158
 159                 out_state->count = rctx->count;
 160                 qce_cpu_to_be32p_array((__be32 *)out_state->state,
 161                                        rctx->digest, digestsize);
 162                 memcpy(out_state->buf, rctx->buf, blocksize);
 163         } else {
 164                 return -EINVAL;
 165         }
 166
 167         return 0;
 168 }
 169
 170 static int qce_import_common(struct ahash_request *req, u64 in_count,
 171                              const u32 *state, const u8 *buffer, bool hmac)
 172 {
 173         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 174         struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
 175         unsigned int digestsize = crypto_ahash_digestsize(ahash);
 176         unsigned int blocksize;
 177         u64 count = in_count;
 178
 179         blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(ahash));
 180         rctx->count = in_count;
 181         memcpy(rctx->buf, buffer, blocksize);
 182
 183         if (in_count <= blocksize) {
 184                 rctx->first_blk = 1;
 185         } else {
 186                 rctx->first_blk = 0;
 187                 /*
 188                  * For HMAC, there is a hardware padding done when first block
 189                  * is set. Therefore the byte_count must be incremened by 64
 190                  * after the first block operation.
 191                  */
 192                 if (hmac)
 193                         count += SHA_PADDING;
 194         }
 195
 196         rctx->byte_count[0] = (__force __be32)(count & ~SHA_PADDING_MASK);
 197         rctx->byte_count[1] = (__force __be32)(count >> 32);
 198         qce_cpu_to_be32p_array((__be32 *)rctx->digest, (const u8 *)state,
 199                                digestsize);
 200         rctx->buflen = (unsigned int)(in_count & (blocksize - 1));
 201
 202         return 0;
 203 }
 204
 205 static int qce_ahash_import(struct ahash_request *req, const void *in)
 206 {
 207         struct qce_sha_reqctx *rctx;
 208         unsigned long flags;
 209         bool hmac;
 210         int ret;
 211
 212         ret = qce_ahash_init(req);
 213         if (ret)
 214                 return ret;
 215
 216         rctx = ahash_request_ctx(req);
 217         flags = rctx->flags;
 218         hmac = IS_SHA_HMAC(flags);
 219
 220         if (IS_SHA1(flags) || IS_SHA1_HMAC(flags)) {
 221                 const struct sha1_state *state = in;
 222
 223                 ret = qce_import_common(req, state->count, state->state,
 224                                         state->buffer, hmac);
 225         } else if (IS_SHA256(flags) || IS_SHA256_HMAC(flags)) {
 226                 const struct sha256_state *state = in;
 227
 228                 ret = qce_import_common(req, state->count, state->state,
 229                                         state->buf, hmac);
 230         }
 231
 232         return ret;
 233 }
 234
 235 static int qce_ahash_update(struct ahash_request *req)
 236 {
 237         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 238         struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
 239         struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
 240         struct qce_device *qce = tmpl->qce;
 241         struct scatterlist *sg_last, *sg;
 242         unsigned int total, len;
 243         unsigned int hash_later;
 244         unsigned int nbytes;
 245         unsigned int blocksize;
 246
 247         blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
 248         rctx->count += req->nbytes;
 249
 250         /* check for buffer from previous updates and append it */
 251         total = req->nbytes + rctx->buflen;
 252
 253         if (total <= blocksize) {
 254                 scatterwalk_map_and_copy(rctx->buf + rctx->buflen, req->src,
 255                                          0, req->nbytes, 0);
 256                 rctx->buflen += req->nbytes;
 257                 return 0;
 258         }
 259
 260         /* save the original req structure fields */
 261         rctx->src_orig = req->src;
 262         rctx->nbytes_orig = req->nbytes;
 263
 264         /*
 265          * if we have data from previous update copy them on buffer. The old
 266          * data will be combined with current request bytes.
 267          */
 268         if (rctx->buflen)
 269                 memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen);
 270
 271         /* calculate how many bytes will be hashed later */
 272         hash_later = total % blocksize;
 273         if (hash_later) {
 274                 unsigned int src_offset = req->nbytes - hash_later;
 275                 scatterwalk_map_and_copy(rctx->buf, req->src, src_offset,
 276                                          hash_later, 0);
 277         }
 278
 279         /* here nbytes is multiple of blocksize */
 280         nbytes = total - hash_later;
 281
 282         len = rctx->buflen;
 283         sg = sg_last = req->src;
 284
 285         while (len < nbytes && sg) {
 286                 if (len + sg_dma_len(sg) > nbytes)
 287                         break;
 288                 len += sg_dma_len(sg);
 289                 sg_last = sg;
 290                 sg = sg_next(sg);
 291         }
 292
 293         if (!sg_last)
 294                 return -EINVAL;
 295
 296         if (rctx->buflen) {
 297                 sg_init_table(rctx->sg, 2);
 298                 sg_set_buf(rctx->sg, rctx->tmpbuf, rctx->buflen);
 299                 sg_chain(rctx->sg, 2, req->src);
 300                 req->src = rctx->sg;
 301         }
 302
 303         req->nbytes = nbytes;
 304         rctx->buflen = hash_later;
 305
 306         return qce->async_req_enqueue(tmpl->qce, &req->base);
 307 }
 308
 309 static int qce_ahash_final(struct ahash_request *req)
 310 {
 311         struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
 312         struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
 313         struct qce_device *qce = tmpl->qce;
 314
 315         if (!rctx->buflen) {
 316                 if (tmpl->hash_zero)
 317                         memcpy(req->result, tmpl->hash_zero,
 318                                         tmpl->alg.ahash.halg.digestsize);
 319                 return 0;
 320         }
 321
 322         rctx->last_blk = true;
 323
 324         rctx->src_orig = req->src;
 325         rctx->nbytes_orig = req->nbytes;
 326
 327         memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen);
 328         sg_init_one(rctx->sg, rctx->tmpbuf, rctx->buflen);
 329
 330         req->src = rctx->sg;
 331         req->nbytes = rctx->buflen;
 332
 333         return qce->async_req_enqueue(tmpl->qce, &req->base);
 334 }
 335
 336 static int qce_ahash_digest(struct ahash_request *req)
 337 {
 338         struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
 339         struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
 340         struct qce_device *qce = tmpl->qce;
 341         int ret;
 342
 343         ret = qce_ahash_init(req);
 344         if (ret)
 345                 return ret;
 346
 347         rctx->src_orig = req->src;
 348         rctx->nbytes_orig = req->nbytes;
 349         rctx->first_blk = true;
 350         rctx->last_blk = true;
 351
 352         if (!rctx->nbytes_orig) {
 353                 if (tmpl->hash_zero)
 354                         memcpy(req->result, tmpl->hash_zero,
 355                                         tmpl->alg.ahash.halg.digestsize);
 356                 return 0;
 357         }
 358
 359         return qce->async_req_enqueue(tmpl->qce, &req->base);
 360 }
 361
 362 static int qce_ahash_hmac_setkey(struct crypto_ahash *tfm, const u8 *key,
 363                                  unsigned int keylen)
 364 {
 365         unsigned int digestsize = crypto_ahash_digestsize(tfm);
 366         struct qce_sha_ctx *ctx = crypto_tfm_ctx(&tfm->base);
 367         struct crypto_wait wait;
 368         struct ahash_request *req;
 369         struct scatterlist sg;
 370         unsigned int blocksize;
 371         struct crypto_ahash *ahash_tfm;
 372         u8 *buf;
 373         int ret;
 374         const char *alg_name;
 375
 376         blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
 377         memset(ctx->authkey, 0, sizeof(ctx->authkey));
 378
 379         if (keylen <= blocksize) {
 380                 memcpy(ctx->authkey, key, keylen);
 381                 return 0;
 382         }
 383
 384         if (digestsize == SHA1_DIGEST_SIZE)
 385                 alg_name = "sha1-qce";
 386         else if (digestsize == SHA256_DIGEST_SIZE)
 387                 alg_name = "sha256-qce";
 388         else
 389                 return -EINVAL;
 390
 391         ahash_tfm = crypto_alloc_ahash(alg_name, 0, 0);
 392         if (IS_ERR(ahash_tfm))
 393                 return PTR_ERR(ahash_tfm);
 394
 395         req = ahash_request_alloc(ahash_tfm, GFP_KERNEL);
 396         if (!req) {
 397                 ret = -ENOMEM;
 398                 goto err_free_ahash;
 399         }
 400
 401         crypto_init_wait(&wait);
 402         ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
 403                                    crypto_req_done, &wait);
 404         crypto_ahash_clear_flags(ahash_tfm, ~0);
 405
 406         buf = kzalloc(keylen + QCE_MAX_ALIGN_SIZE, GFP_KERNEL);
 407         if (!buf) {
 408                 ret = -ENOMEM;
 409                 goto err_free_req;
 410         }
 411
 412         memcpy(buf, key, keylen);
 413         sg_init_one(&sg, buf, keylen);
 414         ahash_request_set_crypt(req, &sg, ctx->authkey, keylen);
 415
 416         ret = crypto_wait_req(crypto_ahash_digest(req), &wait);
 417
 418         kfree(buf);
 419 err_free_req:
 420         ahash_request_free(req);
 421 err_free_ahash:
 422         crypto_free_ahash(ahash_tfm);
 423         return ret;
 424 }
 425
 426 static int qce_ahash_cra_init(struct crypto_tfm *tfm)
 427 {
 428         struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
 429         struct qce_sha_ctx *ctx = crypto_tfm_ctx(tfm);
 430
 431         crypto_ahash_set_reqsize(ahash, sizeof(struct qce_sha_reqctx));
 432         memset(ctx, 0, sizeof(*ctx));
 433         return 0;
 434 }
 435
 436 struct qce_ahash_def {
 437         unsigned long flags;
 438         const char *name;
 439         const char *drv_name;
 440         unsigned int digestsize;
 441         unsigned int blocksize;
 442         unsigned int statesize;
 443         const u32 *std_iv;
 444 };
 445
 446 static const struct qce_ahash_def ahash_def[] = {
 447         {
 448                 .flags          = QCE_HASH_SHA1,
 449                 .name           = "sha1",
 450                 .drv_name       = "sha1-qce",
 451                 .digestsize     = SHA1_DIGEST_SIZE,
 452                 .blocksize      = SHA1_BLOCK_SIZE,
 453                 .statesize      = sizeof(struct sha1_state),
 454                 .std_iv         = std_iv_sha1,
 455         },
 456         {
 457                 .flags          = QCE_HASH_SHA256,
 458                 .name           = "sha256",
 459                 .drv_name       = "sha256-qce",
 460                 .digestsize     = SHA256_DIGEST_SIZE,
 461                 .blocksize      = SHA256_BLOCK_SIZE,
 462                 .statesize      = sizeof(struct sha256_state),
 463                 .std_iv         = std_iv_sha256,
 464         },
 465         {
 466                 .flags          = QCE_HASH_SHA1_HMAC,
 467                 .name           = "hmac(sha1)",
 468                 .drv_name       = "hmac-sha1-qce",
 469                 .digestsize     = SHA1_DIGEST_SIZE,
 470                 .blocksize      = SHA1_BLOCK_SIZE,
 471                 .statesize      = sizeof(struct sha1_state),
 472                 .std_iv         = std_iv_sha1,
 473         },
 474         {
 475                 .flags          = QCE_HASH_SHA256_HMAC,
 476                 .name           = "hmac(sha256)",
 477                 .drv_name       = "hmac-sha256-qce",
 478                 .digestsize     = SHA256_DIGEST_SIZE,
 479                 .blocksize      = SHA256_BLOCK_SIZE,
 480                 .statesize      = sizeof(struct sha256_state),
 481                 .std_iv         = std_iv_sha256,
 482         },
 483 };
 484
 485 static int qce_ahash_register_one(const struct qce_ahash_def *def,
 486                                   struct qce_device *qce)
 487 {
 488         struct qce_alg_template *tmpl;
 489         struct ahash_alg *alg;
 490         struct crypto_alg *base;
 491         int ret;
 492
 493         tmpl = kzalloc(sizeof(*tmpl), GFP_KERNEL);
 494         if (!tmpl)
 495                 return -ENOMEM;
 496
 497         tmpl->std_iv = def->std_iv;
 498
 499         alg = &tmpl->alg.ahash;
 500         alg->init = qce_ahash_init;
 501         alg->update = qce_ahash_update;
 502         alg->final = qce_ahash_final;
 503         alg->digest = qce_ahash_digest;
 504         alg->export = qce_ahash_export;
 505         alg->import = qce_ahash_import;
 506         if (IS_SHA_HMAC(def->flags))
 507                 alg->setkey = qce_ahash_hmac_setkey;
 508         alg->halg.digestsize = def->digestsize;
 509         alg->halg.statesize = def->statesize;
 510
 511         if (IS_SHA1(def->flags))
 512                 tmpl->hash_zero = sha1_zero_message_hash;
 513         else if (IS_SHA256(def->flags))
 514                 tmpl->hash_zero = sha256_zero_message_hash;
 515
 516         base = &alg->halg.base;
 517         base->cra_blocksize = def->blocksize;
 518         base->cra_priority = 300;
 519         base->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
 520         base->cra_ctxsize = sizeof(struct qce_sha_ctx);
 521         base->cra_alignmask = 0;
 522         base->cra_module = THIS_MODULE;
 523         base->cra_init = qce_ahash_cra_init;
 524
 525         snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name);
 526         snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
 527                  def->drv_name);
 528
 529         INIT_LIST_HEAD(&tmpl->entry);
 530         tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_AHASH;
 531         tmpl->alg_flags = def->flags;
 532         tmpl->qce = qce;
 533
 534         ret = crypto_register_ahash(alg);
 535         if (ret) {
 536                 dev_err(qce->dev, "%s registration failed\n", base->cra_name);
 537                 kfree(tmpl);
 538                 return ret;
 539         }
 540
 541         list_add_tail(&tmpl->entry, &ahash_algs);
 542         dev_dbg(qce->dev, "%s is registered\n", base->cra_name);
 543         return 0;
 544 }
 545
 546 static void qce_ahash_unregister(struct qce_device *qce)
 547 {
 548         struct qce_alg_template *tmpl, *n;
 549
 550         list_for_each_entry_safe(tmpl, n, &ahash_algs, entry) {
 551                 crypto_unregister_ahash(&tmpl->alg.ahash);
 552                 list_del(&tmpl->entry);
 553                 kfree(tmpl);
 554         }
 555 }
 556
 557 static int qce_ahash_register(struct qce_device *qce)
 558 {
 559         int ret, i;
 560
 561         for (i = 0; i < ARRAY_SIZE(ahash_def); i++) {
 562                 ret = qce_ahash_register_one(&ahash_def[i], qce);
 563                 if (ret)
 564                         goto err;
 565         }
 566
 567         return 0;
 568 err:
 569         qce_ahash_unregister(qce);
 570         return ret;
 571 }
 572
 573 const struct qce_algo_ops ahash_ops = {
 574         .type = CRYPTO_ALG_TYPE_AHASH,
 575         .register_algs = qce_ahash_register,
 576         .unregister_algs = qce_ahash_unregister,
 577         .async_req_handle = qce_ahash_async_req_handle,
 578 };