1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #ifndef ADF_DH895x_HW_DATA_H_
4 #define ADF_DH895x_HW_DATA_H_
6 /* PCIe configuration space */
7 #define ADF_DH895XCC_SRAM_BAR 0
8 #define ADF_DH895XCC_PMISC_BAR 1
9 #define ADF_DH895XCC_ETR_BAR 2
10 #define ADF_DH895XCC_FUSECTL_SKU_MASK 0x300000
11 #define ADF_DH895XCC_FUSECTL_SKU_SHIFT 20
12 #define ADF_DH895XCC_FUSECTL_SKU_1 0x0
13 #define ADF_DH895XCC_FUSECTL_SKU_2 0x1
14 #define ADF_DH895XCC_FUSECTL_SKU_3 0x2
15 #define ADF_DH895XCC_FUSECTL_SKU_4 0x3
16 #define ADF_DH895XCC_MAX_ACCELERATORS 6
17 #define ADF_DH895XCC_MAX_ACCELENGINES 12
18 #define ADF_DH895XCC_ACCELERATORS_REG_OFFSET 13
19 #define ADF_DH895XCC_ACCELERATORS_MASK 0x3F
20 #define ADF_DH895XCC_ACCELENGINES_MASK 0xFFF
21 #define ADF_DH895XCC_ETR_MAX_BANKS 32
22 #define ADF_DH895XCC_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
23 #define ADF_DH895XCC_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
24 #define ADF_DH895XCC_SMIA0_MASK 0xFFFFFFFF
25 #define ADF_DH895XCC_SMIA1_MASK 0x1
27 /* Masks for VF2PF interrupts */
28 #define ADF_DH895XCC_ERR_REG_VF2PF_U(vf_src) (((vf_src) & 0x0000FFFF) << 16)
29 #define ADF_DH895XCC_ERR_MSK_VF2PF_U(vf_mask) ((vf_mask) >> 16)
31 /* AE to function mapping */
32 #define ADF_DH895XCC_AE2FUNC_MAP_GRP_A_NUM_REGS 96
33 #define ADF_DH895XCC_AE2FUNC_MAP_GRP_B_NUM_REGS 12
36 #define ADF_DH895XCC_FW "/*(DEBLOBBED)*/"
37 #define ADF_DH895XCC_MMP "/*(DEBLOBBED)*/"
39 void adf_init_hw_data_dh895xcc(struct adf_hw_device_data *hw_data);
40 void adf_clean_hw_data_dh895xcc(struct adf_hw_device_data *hw_data);