1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
6 enum icp_qat_hw_ae_id {
17 ICP_QAT_HW_AE_10 = 10,
18 ICP_QAT_HW_AE_11 = 11,
19 ICP_QAT_HW_AE_DELIMITER = 12
22 enum icp_qat_hw_qat_id {
29 ICP_QAT_HW_QAT_DELIMITER = 6
32 enum icp_qat_hw_auth_algo {
33 ICP_QAT_HW_AUTH_ALGO_NULL = 0,
34 ICP_QAT_HW_AUTH_ALGO_SHA1 = 1,
35 ICP_QAT_HW_AUTH_ALGO_MD5 = 2,
36 ICP_QAT_HW_AUTH_ALGO_SHA224 = 3,
37 ICP_QAT_HW_AUTH_ALGO_SHA256 = 4,
38 ICP_QAT_HW_AUTH_ALGO_SHA384 = 5,
39 ICP_QAT_HW_AUTH_ALGO_SHA512 = 6,
40 ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7,
41 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8,
42 ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9,
43 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10,
44 ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11,
45 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12,
46 ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13,
47 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14,
48 ICP_QAT_HW_AUTH_RESERVED_1 = 15,
49 ICP_QAT_HW_AUTH_RESERVED_2 = 16,
50 ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,
51 ICP_QAT_HW_AUTH_RESERVED_3 = 18,
52 ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19,
53 ICP_QAT_HW_AUTH_ALGO_DELIMITER = 20
56 enum icp_qat_hw_auth_mode {
57 ICP_QAT_HW_AUTH_MODE0 = 0,
58 ICP_QAT_HW_AUTH_MODE1 = 1,
59 ICP_QAT_HW_AUTH_MODE2 = 2,
60 ICP_QAT_HW_AUTH_MODE_DELIMITER = 3
63 struct icp_qat_hw_auth_config {
68 #define QAT_AUTH_MODE_BITPOS 4
69 #define QAT_AUTH_MODE_MASK 0xF
70 #define QAT_AUTH_ALGO_BITPOS 0
71 #define QAT_AUTH_ALGO_MASK 0xF
72 #define QAT_AUTH_CMP_BITPOS 8
73 #define QAT_AUTH_CMP_MASK 0x7F
74 #define QAT_AUTH_SHA3_PADDING_BITPOS 16
75 #define QAT_AUTH_SHA3_PADDING_MASK 0x1
76 #define QAT_AUTH_ALGO_SHA3_BITPOS 22
77 #define QAT_AUTH_ALGO_SHA3_MASK 0x3
78 #define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
79 (((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
80 ((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
81 (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
82 QAT_AUTH_ALGO_SHA3_BITPOS) | \
83 (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
84 (algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
85 & QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
86 ((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
88 struct icp_qat_hw_auth_counter {
93 #define QAT_AUTH_COUNT_MASK 0xFFFFFFFF
94 #define QAT_AUTH_COUNT_BITPOS 0
95 #define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \
96 (((val) & QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS)
98 struct icp_qat_hw_auth_setup {
99 struct icp_qat_hw_auth_config auth_config;
100 struct icp_qat_hw_auth_counter auth_counter;
103 #define QAT_HW_DEFAULT_ALIGNMENT 8
104 #define QAT_HW_ROUND_UP(val, n) (((val) + ((n) - 1)) & (~(n - 1)))
105 #define ICP_QAT_HW_NULL_STATE1_SZ 32
106 #define ICP_QAT_HW_MD5_STATE1_SZ 16
107 #define ICP_QAT_HW_SHA1_STATE1_SZ 20
108 #define ICP_QAT_HW_SHA224_STATE1_SZ 32
109 #define ICP_QAT_HW_SHA256_STATE1_SZ 32
110 #define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
111 #define ICP_QAT_HW_SHA384_STATE1_SZ 64
112 #define ICP_QAT_HW_SHA512_STATE1_SZ 64
113 #define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
114 #define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
115 #define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
116 #define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
117 #define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
118 #define ICP_QAT_HW_AES_F9_STATE1_SZ 32
119 #define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16
120 #define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
121 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
122 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
123 #define ICP_QAT_HW_NULL_STATE2_SZ 32
124 #define ICP_QAT_HW_MD5_STATE2_SZ 16
125 #define ICP_QAT_HW_SHA1_STATE2_SZ 20
126 #define ICP_QAT_HW_SHA224_STATE2_SZ 32
127 #define ICP_QAT_HW_SHA256_STATE2_SZ 32
128 #define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
129 #define ICP_QAT_HW_SHA384_STATE2_SZ 64
130 #define ICP_QAT_HW_SHA512_STATE2_SZ 64
131 #define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
132 #define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
133 #define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
134 #define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
135 #define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
136 #define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16
137 #define ICP_QAT_HW_F9_IK_SZ 16
138 #define ICP_QAT_HW_F9_FK_SZ 16
139 #define ICP_QAT_HW_KASUMI_F9_STATE2_SZ (ICP_QAT_HW_F9_IK_SZ + \
141 #define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ
142 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24
143 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32
144 #define ICP_QAT_HW_GALOIS_H_SZ 16
145 #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8
146 #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16
148 struct icp_qat_hw_auth_sha512 {
149 struct icp_qat_hw_auth_setup inner_setup;
150 __u8 state1[ICP_QAT_HW_SHA512_STATE1_SZ];
151 struct icp_qat_hw_auth_setup outer_setup;
152 __u8 state2[ICP_QAT_HW_SHA512_STATE2_SZ];
155 struct icp_qat_hw_auth_algo_blk {
156 struct icp_qat_hw_auth_sha512 sha;
159 #define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0
160 #define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF
162 enum icp_qat_hw_cipher_algo {
163 ICP_QAT_HW_CIPHER_ALGO_NULL = 0,
164 ICP_QAT_HW_CIPHER_ALGO_DES = 1,
165 ICP_QAT_HW_CIPHER_ALGO_3DES = 2,
166 ICP_QAT_HW_CIPHER_ALGO_AES128 = 3,
167 ICP_QAT_HW_CIPHER_ALGO_AES192 = 4,
168 ICP_QAT_HW_CIPHER_ALGO_AES256 = 5,
169 ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6,
170 ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7,
171 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8,
172 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9,
173 ICP_QAT_HW_CIPHER_DELIMITER = 10
176 enum icp_qat_hw_cipher_mode {
177 ICP_QAT_HW_CIPHER_ECB_MODE = 0,
178 ICP_QAT_HW_CIPHER_CBC_MODE = 1,
179 ICP_QAT_HW_CIPHER_CTR_MODE = 2,
180 ICP_QAT_HW_CIPHER_F8_MODE = 3,
181 ICP_QAT_HW_CIPHER_XTS_MODE = 6,
182 ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7
185 struct icp_qat_hw_cipher_config {
190 enum icp_qat_hw_cipher_dir {
191 ICP_QAT_HW_CIPHER_ENCRYPT = 0,
192 ICP_QAT_HW_CIPHER_DECRYPT = 1,
195 enum icp_qat_hw_cipher_convert {
196 ICP_QAT_HW_CIPHER_NO_CONVERT = 0,
197 ICP_QAT_HW_CIPHER_KEY_CONVERT = 1,
200 #define QAT_CIPHER_MODE_BITPOS 4
201 #define QAT_CIPHER_MODE_MASK 0xF
202 #define QAT_CIPHER_ALGO_BITPOS 0
203 #define QAT_CIPHER_ALGO_MASK 0xF
204 #define QAT_CIPHER_CONVERT_BITPOS 9
205 #define QAT_CIPHER_CONVERT_MASK 0x1
206 #define QAT_CIPHER_DIR_BITPOS 8
207 #define QAT_CIPHER_DIR_MASK 0x1
208 #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2
209 #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2
210 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \
211 (((mode & QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \
212 ((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \
213 ((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \
214 ((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS))
215 #define ICP_QAT_HW_DES_BLK_SZ 8
216 #define ICP_QAT_HW_3DES_BLK_SZ 8
217 #define ICP_QAT_HW_NULL_BLK_SZ 8
218 #define ICP_QAT_HW_AES_BLK_SZ 16
219 #define ICP_QAT_HW_KASUMI_BLK_SZ 8
220 #define ICP_QAT_HW_SNOW_3G_BLK_SZ 8
221 #define ICP_QAT_HW_ZUC_3G_BLK_SZ 8
222 #define ICP_QAT_HW_NULL_KEY_SZ 256
223 #define ICP_QAT_HW_DES_KEY_SZ 8
224 #define ICP_QAT_HW_3DES_KEY_SZ 24
225 #define ICP_QAT_HW_AES_128_KEY_SZ 16
226 #define ICP_QAT_HW_AES_192_KEY_SZ 24
227 #define ICP_QAT_HW_AES_256_KEY_SZ 32
228 #define ICP_QAT_HW_AES_128_F8_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
229 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
230 #define ICP_QAT_HW_AES_192_F8_KEY_SZ (ICP_QAT_HW_AES_192_KEY_SZ * \
231 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
232 #define ICP_QAT_HW_AES_256_F8_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
233 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
234 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
235 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
236 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
237 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
238 #define ICP_QAT_HW_KASUMI_KEY_SZ 16
239 #define ICP_QAT_HW_KASUMI_F8_KEY_SZ (ICP_QAT_HW_KASUMI_KEY_SZ * \
240 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
241 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
242 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
243 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
244 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
245 #define ICP_QAT_HW_ARC4_KEY_SZ 256
246 #define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16
247 #define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16
248 #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16
249 #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16
250 #define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2
251 #define INIT_SHRAM_CONSTANTS_TABLE_SZ 1024
253 struct icp_qat_hw_cipher_aes256_f8 {
254 struct icp_qat_hw_cipher_config cipher_config;
255 __u8 key[ICP_QAT_HW_AES_256_F8_KEY_SZ];
258 struct icp_qat_hw_cipher_algo_blk {
259 struct icp_qat_hw_cipher_aes256_f8 aes;