drivers/crypto/qat/qat_common/icp_qat_fw_loader_handle.h

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
   2 /* Copyright(c) 2014 - 2020 Intel Corporation */
   3 #ifndef __ICP_QAT_FW_LOADER_HANDLE_H__
   4 #define __ICP_QAT_FW_LOADER_HANDLE_H__
   5 #include "icp_qat_uclo.h"
   6
   7 struct icp_qat_fw_loader_ae_data {
   8         unsigned int state;
   9         unsigned int ustore_size;
  10         unsigned int free_addr;
  11         unsigned int free_size;
  12         unsigned int live_ctx_mask;
  13 };
  14
  15 struct icp_qat_fw_loader_hal_handle {
  16         struct icp_qat_fw_loader_ae_data aes[ICP_QAT_UCLO_MAX_AE];
  17         unsigned int ae_mask;
  18         unsigned int slice_mask;
  19         unsigned int revision_id;
  20         unsigned int ae_max_num;
  21         unsigned int upc_mask;
  22         unsigned int max_ustore;
  23 };
  24
  25 struct icp_qat_fw_loader_handle {
  26         struct icp_qat_fw_loader_hal_handle *hal_handle;
  27         struct pci_dev *pci_dev;
  28         void *obj_handle;
  29         void *sobj_handle;
  30         bool fw_auth;
  31         void __iomem *hal_sram_addr_v;
  32         void __iomem *hal_cap_g_ctl_csr_addr_v;
  33         void __iomem *hal_cap_ae_xfer_csr_addr_v;
  34         void __iomem *hal_cap_ae_local_csr_addr_v;
  35         void __iomem *hal_ep_csr_addr_v;
  36 };
  37
  38 struct icp_firml_dram_desc {
  39         void __iomem *dram_base_addr;
  40         void *dram_base_addr_v;
  41         dma_addr_t dram_bus_addr;
  42         u64 dram_size;
  43 };
  44 #endif