1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #ifndef _ICP_QAT_FW_LA_H_
4 #define _ICP_QAT_FW_LA_H_
5 #include "icp_qat_fw.h"
7 enum icp_qat_fw_la_cmd_id {
8 ICP_QAT_FW_LA_CMD_CIPHER = 0,
9 ICP_QAT_FW_LA_CMD_AUTH = 1,
10 ICP_QAT_FW_LA_CMD_CIPHER_HASH = 2,
11 ICP_QAT_FW_LA_CMD_HASH_CIPHER = 3,
12 ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM = 4,
13 ICP_QAT_FW_LA_CMD_TRNG_TEST = 5,
14 ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE = 6,
15 ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE = 7,
16 ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE = 8,
17 ICP_QAT_FW_LA_CMD_MGF1 = 9,
18 ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP = 10,
19 ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP = 11,
20 ICP_QAT_FW_LA_CMD_DELIMITER = 12
23 #define ICP_QAT_FW_LA_ICV_VER_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK
24 #define ICP_QAT_FW_LA_ICV_VER_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR
25 #define ICP_QAT_FW_LA_TRNG_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK
26 #define ICP_QAT_FW_LA_TRNG_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR
28 struct icp_qat_fw_la_bulk_req {
29 struct icp_qat_fw_comn_req_hdr comn_hdr;
30 struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
31 struct icp_qat_fw_comn_req_mid comn_mid;
32 struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;
33 struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
36 #define ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS 1
37 #define ICP_QAT_FW_LA_GCM_IV_LEN_NOT_12_OCTETS 0
38 #define QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS 12
39 #define ICP_QAT_FW_LA_ZUC_3G_PROTO 1
40 #define QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK 0x1
41 #define QAT_LA_GCM_IV_LEN_FLAG_BITPOS 11
42 #define QAT_LA_GCM_IV_LEN_FLAG_MASK 0x1
43 #define ICP_QAT_FW_LA_DIGEST_IN_BUFFER 1
44 #define ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER 0
45 #define QAT_LA_DIGEST_IN_BUFFER_BITPOS 10
46 #define QAT_LA_DIGEST_IN_BUFFER_MASK 0x1
47 #define ICP_QAT_FW_LA_SNOW_3G_PROTO 4
48 #define ICP_QAT_FW_LA_GCM_PROTO 2
49 #define ICP_QAT_FW_LA_CCM_PROTO 1
50 #define ICP_QAT_FW_LA_NO_PROTO 0
51 #define QAT_LA_PROTO_BITPOS 7
52 #define QAT_LA_PROTO_MASK 0x7
53 #define ICP_QAT_FW_LA_CMP_AUTH_RES 1
54 #define ICP_QAT_FW_LA_NO_CMP_AUTH_RES 0
55 #define QAT_LA_CMP_AUTH_RES_BITPOS 6
56 #define QAT_LA_CMP_AUTH_RES_MASK 0x1
57 #define ICP_QAT_FW_LA_RET_AUTH_RES 1
58 #define ICP_QAT_FW_LA_NO_RET_AUTH_RES 0
59 #define QAT_LA_RET_AUTH_RES_BITPOS 5
60 #define QAT_LA_RET_AUTH_RES_MASK 0x1
61 #define ICP_QAT_FW_LA_UPDATE_STATE 1
62 #define ICP_QAT_FW_LA_NO_UPDATE_STATE 0
63 #define QAT_LA_UPDATE_STATE_BITPOS 4
64 #define QAT_LA_UPDATE_STATE_MASK 0x1
65 #define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_CD_SETUP 0
66 #define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_SHRAM_CP 1
67 #define QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS 3
68 #define QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK 0x1
69 #define ICP_QAT_FW_CIPH_IV_64BIT_PTR 0
70 #define ICP_QAT_FW_CIPH_IV_16BYTE_DATA 1
71 #define QAT_LA_CIPH_IV_FLD_BITPOS 2
72 #define QAT_LA_CIPH_IV_FLD_MASK 0x1
73 #define ICP_QAT_FW_LA_PARTIAL_NONE 0
74 #define ICP_QAT_FW_LA_PARTIAL_START 1
75 #define ICP_QAT_FW_LA_PARTIAL_MID 3
76 #define ICP_QAT_FW_LA_PARTIAL_END 2
77 #define QAT_LA_PARTIAL_BITPOS 0
78 #define QAT_LA_PARTIAL_MASK 0x3
79 #define ICP_QAT_FW_LA_FLAGS_BUILD(zuc_proto, gcm_iv_len, auth_rslt, proto, \
80 cmp_auth, ret_auth, update_state, \
81 ciph_iv, ciphcfg, partial) \
82 (((zuc_proto & QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK) << \
83 QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS) | \
84 ((gcm_iv_len & QAT_LA_GCM_IV_LEN_FLAG_MASK) << \
85 QAT_LA_GCM_IV_LEN_FLAG_BITPOS) | \
86 ((auth_rslt & QAT_LA_DIGEST_IN_BUFFER_MASK) << \
87 QAT_LA_DIGEST_IN_BUFFER_BITPOS) | \
88 ((proto & QAT_LA_PROTO_MASK) << \
89 QAT_LA_PROTO_BITPOS) | \
90 ((cmp_auth & QAT_LA_CMP_AUTH_RES_MASK) << \
91 QAT_LA_CMP_AUTH_RES_BITPOS) | \
92 ((ret_auth & QAT_LA_RET_AUTH_RES_MASK) << \
93 QAT_LA_RET_AUTH_RES_BITPOS) | \
94 ((update_state & QAT_LA_UPDATE_STATE_MASK) << \
95 QAT_LA_UPDATE_STATE_BITPOS) | \
96 ((ciph_iv & QAT_LA_CIPH_IV_FLD_MASK) << \
97 QAT_LA_CIPH_IV_FLD_BITPOS) | \
98 ((ciphcfg & QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK) << \
99 QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS) | \
100 ((partial & QAT_LA_PARTIAL_MASK) << \
101 QAT_LA_PARTIAL_BITPOS))
103 #define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_GET(flags) \
104 QAT_FIELD_GET(flags, QAT_LA_CIPH_IV_FLD_BITPOS, \
105 QAT_LA_CIPH_IV_FLD_MASK)
107 #define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_GET(flags) \
108 QAT_FIELD_GET(flags, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \
109 QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK)
111 #define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_GET(flags) \
112 QAT_FIELD_GET(flags, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \
113 QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK)
115 #define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_GET(flags) \
116 QAT_FIELD_GET(flags, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \
117 QAT_LA_GCM_IV_LEN_FLAG_MASK)
119 #define ICP_QAT_FW_LA_PROTO_GET(flags) \
120 QAT_FIELD_GET(flags, QAT_LA_PROTO_BITPOS, QAT_LA_PROTO_MASK)
122 #define ICP_QAT_FW_LA_CMP_AUTH_GET(flags) \
123 QAT_FIELD_GET(flags, QAT_LA_CMP_AUTH_RES_BITPOS, \
124 QAT_LA_CMP_AUTH_RES_MASK)
126 #define ICP_QAT_FW_LA_RET_AUTH_GET(flags) \
127 QAT_FIELD_GET(flags, QAT_LA_RET_AUTH_RES_BITPOS, \
128 QAT_LA_RET_AUTH_RES_MASK)
130 #define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_GET(flags) \
131 QAT_FIELD_GET(flags, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \
132 QAT_LA_DIGEST_IN_BUFFER_MASK)
134 #define ICP_QAT_FW_LA_UPDATE_STATE_GET(flags) \
135 QAT_FIELD_GET(flags, QAT_LA_UPDATE_STATE_BITPOS, \
136 QAT_LA_UPDATE_STATE_MASK)
138 #define ICP_QAT_FW_LA_PARTIAL_GET(flags) \
139 QAT_FIELD_GET(flags, QAT_LA_PARTIAL_BITPOS, \
142 #define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(flags, val) \
143 QAT_FIELD_SET(flags, val, QAT_LA_CIPH_IV_FLD_BITPOS, \
144 QAT_LA_CIPH_IV_FLD_MASK)
146 #define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_SET(flags, val) \
147 QAT_FIELD_SET(flags, val, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \
148 QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK)
150 #define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(flags, val) \
151 QAT_FIELD_SET(flags, val, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \
152 QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK)
154 #define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(flags, val) \
155 QAT_FIELD_SET(flags, val, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \
156 QAT_LA_GCM_IV_LEN_FLAG_MASK)
158 #define ICP_QAT_FW_LA_PROTO_SET(flags, val) \
159 QAT_FIELD_SET(flags, val, QAT_LA_PROTO_BITPOS, \
162 #define ICP_QAT_FW_LA_CMP_AUTH_SET(flags, val) \
163 QAT_FIELD_SET(flags, val, QAT_LA_CMP_AUTH_RES_BITPOS, \
164 QAT_LA_CMP_AUTH_RES_MASK)
166 #define ICP_QAT_FW_LA_RET_AUTH_SET(flags, val) \
167 QAT_FIELD_SET(flags, val, QAT_LA_RET_AUTH_RES_BITPOS, \
168 QAT_LA_RET_AUTH_RES_MASK)
170 #define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(flags, val) \
171 QAT_FIELD_SET(flags, val, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \
172 QAT_LA_DIGEST_IN_BUFFER_MASK)
174 #define ICP_QAT_FW_LA_UPDATE_STATE_SET(flags, val) \
175 QAT_FIELD_SET(flags, val, QAT_LA_UPDATE_STATE_BITPOS, \
176 QAT_LA_UPDATE_STATE_MASK)
178 #define ICP_QAT_FW_LA_PARTIAL_SET(flags, val) \
179 QAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \
182 struct icp_qat_fw_cipher_req_hdr_cd_pars {
185 __u64 content_desc_addr;
186 __u16 content_desc_resrvd1;
187 __u8 content_desc_params_sz;
188 __u8 content_desc_hdr_resrvd2;
189 __u32 content_desc_resrvd3;
192 __u32 cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
197 struct icp_qat_fw_cipher_auth_req_hdr_cd_pars {
200 __u64 content_desc_addr;
201 __u16 content_desc_resrvd1;
202 __u8 content_desc_params_sz;
203 __u8 content_desc_hdr_resrvd2;
204 __u32 content_desc_resrvd3;
207 __u32 cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
212 struct icp_qat_fw_cipher_cd_ctrl_hdr {
213 __u8 cipher_state_sz;
215 __u8 cipher_cfg_offset;
217 __u8 cipher_padding_sz;
220 __u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_3];
223 struct icp_qat_fw_auth_cd_ctrl_hdr {
227 __u8 hash_cfg_offset;
230 __u8 outer_prefix_sz;
234 __u8 inner_state1_sz;
235 __u8 inner_state2_offset;
236 __u8 inner_state2_sz;
237 __u8 outer_config_offset;
238 __u8 outer_state1_sz;
240 __u8 outer_prefix_offset;
243 struct icp_qat_fw_cipher_auth_cd_ctrl_hdr {
244 __u8 cipher_state_sz;
246 __u8 cipher_cfg_offset;
247 __u8 next_curr_id_cipher;
248 __u8 cipher_padding_sz;
250 __u8 hash_cfg_offset;
251 __u8 next_curr_id_auth;
253 __u8 outer_prefix_sz;
257 __u8 inner_state1_sz;
258 __u8 inner_state2_offset;
259 __u8 inner_state2_sz;
260 __u8 outer_config_offset;
261 __u8 outer_state1_sz;
263 __u8 outer_prefix_offset;
266 #define ICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED 1
267 #define ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED 0
268 #define ICP_QAT_FW_CCM_GCM_AAD_SZ_MAX 240
269 #define ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET \
270 (sizeof(struct icp_qat_fw_la_cipher_req_params_t))
271 #define ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0)
273 struct icp_qat_fw_la_cipher_req_params {
277 __u32 cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];
285 struct icp_qat_fw_la_auth_req_params {
289 __u64 auth_partial_st_prefix;
294 __u8 inner_prefix_sz;
302 struct icp_qat_fw_la_auth_req_params_resrvd_flds {
303 __u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_6];
305 __u8 inner_prefix_sz;
312 struct icp_qat_fw_la_resp {
313 struct icp_qat_fw_comn_resp_hdr comn_resp;
315 __u32 resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
318 #define ICP_QAT_FW_CIPHER_NEXT_ID_GET(cd_ctrl_hdr_t) \
319 ((((cd_ctrl_hdr_t)->next_curr_id_cipher) & \
320 ICP_QAT_FW_COMN_NEXT_ID_MASK) >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
322 #define ICP_QAT_FW_CIPHER_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
323 { (cd_ctrl_hdr_t)->next_curr_id_cipher = \
324 ((((cd_ctrl_hdr_t)->next_curr_id_cipher) \
325 & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
326 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
327 & ICP_QAT_FW_COMN_NEXT_ID_MASK)) }
329 #define ICP_QAT_FW_CIPHER_CURR_ID_GET(cd_ctrl_hdr_t) \
330 (((cd_ctrl_hdr_t)->next_curr_id_cipher) \
331 & ICP_QAT_FW_COMN_CURR_ID_MASK)
333 #define ICP_QAT_FW_CIPHER_CURR_ID_SET(cd_ctrl_hdr_t, val) \
334 { (cd_ctrl_hdr_t)->next_curr_id_cipher = \
335 ((((cd_ctrl_hdr_t)->next_curr_id_cipher) \
336 & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
337 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }
339 #define ICP_QAT_FW_AUTH_NEXT_ID_GET(cd_ctrl_hdr_t) \
340 ((((cd_ctrl_hdr_t)->next_curr_id_auth) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \
341 >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
343 #define ICP_QAT_FW_AUTH_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
344 { (cd_ctrl_hdr_t)->next_curr_id_auth = \
345 ((((cd_ctrl_hdr_t)->next_curr_id_auth) \
346 & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
347 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
348 & ICP_QAT_FW_COMN_NEXT_ID_MASK)) }
350 #define ICP_QAT_FW_AUTH_CURR_ID_GET(cd_ctrl_hdr_t) \
351 (((cd_ctrl_hdr_t)->next_curr_id_auth) \
352 & ICP_QAT_FW_COMN_CURR_ID_MASK)
354 #define ICP_QAT_FW_AUTH_CURR_ID_SET(cd_ctrl_hdr_t, val) \
355 { (cd_ctrl_hdr_t)->next_curr_id_auth = \
356 ((((cd_ctrl_hdr_t)->next_curr_id_auth) \
357 & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
358 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }