1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #ifndef ADF_TRANSPORT_ACCESS_MACROS_H
4 #define ADF_TRANSPORT_ACCESS_MACROS_H
6 #include "adf_accel_devices.h"
7 #define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
8 #define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
9 #define ADF_BANK_INT_FLAG_CLEAR_MASK 0xFFFF
10 #define ADF_RING_CSR_RING_CONFIG 0x000
11 #define ADF_RING_CSR_RING_LBASE 0x040
12 #define ADF_RING_CSR_RING_UBASE 0x080
13 #define ADF_RING_CSR_RING_HEAD 0x0C0
14 #define ADF_RING_CSR_RING_TAIL 0x100
15 #define ADF_RING_CSR_E_STAT 0x14C
16 #define ADF_RING_CSR_INT_FLAG 0x170
17 #define ADF_RING_CSR_INT_SRCSEL 0x174
18 #define ADF_RING_CSR_INT_SRCSEL_2 0x178
19 #define ADF_RING_CSR_INT_COL_EN 0x17C
20 #define ADF_RING_CSR_INT_COL_CTL 0x180
21 #define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
22 #define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
23 #define ADF_RING_BUNDLE_SIZE 0x1000
24 #define ADF_RING_CONFIG_NEAR_FULL_WM 0x0A
25 #define ADF_RING_CONFIG_NEAR_EMPTY_WM 0x05
26 #define ADF_COALESCING_MIN_TIME 0x1FF
27 #define ADF_COALESCING_MAX_TIME 0xFFFFF
28 #define ADF_COALESCING_DEF_TIME 0x27FF
29 #define ADF_RING_NEAR_WATERMARK_512 0x08
30 #define ADF_RING_NEAR_WATERMARK_0 0x00
31 #define ADF_RING_EMPTY_SIG 0x7F7F7F7F
33 /* Valid internal ring size values */
34 #define ADF_RING_SIZE_128 0x01
35 #define ADF_RING_SIZE_256 0x02
36 #define ADF_RING_SIZE_512 0x03
37 #define ADF_RING_SIZE_4K 0x06
38 #define ADF_RING_SIZE_16K 0x08
39 #define ADF_RING_SIZE_4M 0x10
40 #define ADF_MIN_RING_SIZE ADF_RING_SIZE_128
41 #define ADF_MAX_RING_SIZE ADF_RING_SIZE_4M
42 #define ADF_DEFAULT_RING_SIZE ADF_RING_SIZE_16K
44 /* Valid internal msg size values */
45 #define ADF_MSG_SIZE_32 0x01
46 #define ADF_MSG_SIZE_64 0x02
47 #define ADF_MSG_SIZE_128 0x04
48 #define ADF_MIN_MSG_SIZE ADF_MSG_SIZE_32
49 #define ADF_MAX_MSG_SIZE ADF_MSG_SIZE_128
51 /* Size to bytes conversion macros for ring and msg size values */
52 #define ADF_MSG_SIZE_TO_BYTES(SIZE) (SIZE << 5)
53 #define ADF_BYTES_TO_MSG_SIZE(SIZE) (SIZE >> 5)
54 #define ADF_SIZE_TO_RING_SIZE_IN_BYTES(SIZE) ((1 << (SIZE - 1)) << 7)
55 #define ADF_RING_SIZE_IN_BYTES_TO_SIZE(SIZE) ((1 << (SIZE - 1)) >> 7)
57 /* Minimum ring bufer size for memory allocation */
58 #define ADF_RING_SIZE_BYTES_MIN(SIZE) \
59 ((SIZE < ADF_SIZE_TO_RING_SIZE_IN_BYTES(ADF_RING_SIZE_4K)) ? \
60 ADF_SIZE_TO_RING_SIZE_IN_BYTES(ADF_RING_SIZE_4K) : SIZE)
61 #define ADF_RING_SIZE_MODULO(SIZE) (SIZE + 0x6)
62 #define ADF_SIZE_TO_POW(SIZE) ((((SIZE & 0x4) >> 1) | ((SIZE & 0x4) >> 2) | \
64 /* Max outstanding requests */
65 #define ADF_MAX_INFLIGHTS(RING_SIZE, MSG_SIZE) \
66 ((((1 << (RING_SIZE - 1)) << 3) >> ADF_SIZE_TO_POW(MSG_SIZE)) - 1)
67 #define BUILD_RING_CONFIG(size) \
68 ((ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_FULL_WM) \
69 | (ADF_RING_NEAR_WATERMARK_0 << ADF_RING_CONFIG_NEAR_EMPTY_WM) \
71 #define BUILD_RESP_RING_CONFIG(size, watermark_nf, watermark_ne) \
72 ((watermark_nf << ADF_RING_CONFIG_NEAR_FULL_WM) \
73 | (watermark_ne << ADF_RING_CONFIG_NEAR_EMPTY_WM) \
75 #define BUILD_RING_BASE_ADDR(addr, size) \
76 ((addr >> 6) & (0xFFFFFFFFFFFFFFFFULL << size))
77 #define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
78 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
79 ADF_RING_CSR_RING_HEAD + (ring << 2))
80 #define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
81 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
82 ADF_RING_CSR_RING_TAIL + (ring << 2))
83 #define READ_CSR_E_STAT(csr_base_addr, bank) \
84 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
86 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
87 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
88 ADF_RING_CSR_RING_CONFIG + (ring << 2), value)
89 #define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
91 u32 l_base = 0, u_base = 0; \
92 l_base = (u32)(value & 0xFFFFFFFF); \
93 u_base = (u32)((value & 0xFFFFFFFF00000000ULL) >> 32); \
94 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
95 ADF_RING_CSR_RING_LBASE + (ring << 2), l_base); \
96 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
97 ADF_RING_CSR_RING_UBASE + (ring << 2), u_base); \
99 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
100 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
101 ADF_RING_CSR_RING_HEAD + (ring << 2), value)
102 #define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
103 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
104 ADF_RING_CSR_RING_TAIL + (ring << 2), value)
105 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
106 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
107 ADF_RING_CSR_INT_FLAG, value)
108 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
110 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
111 ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \
112 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
113 ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \
115 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
116 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
117 ADF_RING_CSR_INT_COL_EN, value)
118 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
119 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
120 ADF_RING_CSR_INT_COL_CTL, \
121 ADF_RING_CSR_INT_COL_CTL_ENABLE | value)
122 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
123 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
124 ADF_RING_CSR_INT_FLAG_AND_COL, value)