1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2015 - 2020 Intel Corporation */
3 #ifndef ADF_PF2VF_MSG_H
4 #define ADF_PF2VF_MSG_H
8 * The PF has an array of 32-bit PF2VF registers, one for each VF. The
9 * PF can access all these registers; each VF can access only the one
10 * register associated with that particular VF.
12 * The register functionally is split into two parts:
13 * The bottom half is for PF->VF messages. In particular when the first
14 * bit of this register (bit 0) gets set an interrupt will be triggered
15 * in the respective VF.
16 * The top half is for VF->PF messages. In particular when the first bit
17 * of this half of register (bit 16) gets set an interrupt will be triggered
20 * The remaining bits within this register are available to encode messages.
21 * and implement a collision control mechanism to prevent concurrent use of
22 * the PF2VF register by both the PF and VF.
24 * 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
25 * _______________________________________________
26 * | | | | | | | | | | | | | | | | |
27 * +-----------------------------------------------+
28 * \___________________________/ \_________/ ^ ^
33 * Message-specific Data/Reserved
35 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
36 * _______________________________________________
37 * | | | | | | | | | | | | | | | | |
38 * +-----------------------------------------------+
39 * \___________________________/ \_________/ ^ ^
44 * Message-specific Data/Reserved
46 * Message Origin (Should always be 1)
47 * A legacy out-of-tree QAT driver allowed for a set of messages not supported
48 * by this driver; these had a Msg Origin of 0 and are ignored by this driver.
50 * When a PF or VF attempts to send a message in the lower or upper 16 bits,
51 * respectively, the other 16 bits are written to first with a defined
52 * IN_USE_BY pattern as part of a collision control scheme (see adf_iov_putmsg).
55 #define ADF_PFVF_COMPATIBILITY_VERSION 0x1 /* PF<->VF compat */
58 #define ADF_PF2VF_INT BIT(0)
59 #define ADF_PF2VF_MSGORIGIN_SYSTEM BIT(1)
60 #define ADF_PF2VF_MSGTYPE_MASK 0x0000003C
61 #define ADF_PF2VF_MSGTYPE_SHIFT 2
62 #define ADF_PF2VF_MSGTYPE_RESTARTING 0x01
63 #define ADF_PF2VF_MSGTYPE_VERSION_RESP 0x02
64 #define ADF_PF2VF_IN_USE_BY_PF 0x6AC20000
65 #define ADF_PF2VF_IN_USE_BY_PF_MASK 0xFFFE0000
67 /* PF->VF Version Response */
68 #define ADF_PF2VF_VERSION_RESP_VERS_MASK 0x00003FC0
69 #define ADF_PF2VF_VERSION_RESP_VERS_SHIFT 6
70 #define ADF_PF2VF_VERSION_RESP_RESULT_MASK 0x0000C000
71 #define ADF_PF2VF_VERSION_RESP_RESULT_SHIFT 14
72 #define ADF_PF2VF_MINORVERSION_SHIFT 6
73 #define ADF_PF2VF_MAJORVERSION_SHIFT 10
74 #define ADF_PF2VF_VF_COMPATIBLE 1
75 #define ADF_PF2VF_VF_INCOMPATIBLE 2
76 #define ADF_PF2VF_VF_COMPAT_UNKNOWN 3
79 #define ADF_VF2PF_IN_USE_BY_VF 0x00006AC2
80 #define ADF_VF2PF_IN_USE_BY_VF_MASK 0x0000FFFE
81 #define ADF_VF2PF_INT BIT(16)
82 #define ADF_VF2PF_MSGORIGIN_SYSTEM BIT(17)
83 #define ADF_VF2PF_MSGTYPE_MASK 0x003C0000
84 #define ADF_VF2PF_MSGTYPE_SHIFT 18
85 #define ADF_VF2PF_MSGTYPE_INIT 0x3
86 #define ADF_VF2PF_MSGTYPE_SHUTDOWN 0x4
87 #define ADF_VF2PF_MSGTYPE_VERSION_REQ 0x5
88 #define ADF_VF2PF_MSGTYPE_COMPAT_VER_REQ 0x6
90 /* VF->PF Compatible Version Request */
91 #define ADF_VF2PF_COMPAT_VER_REQ_SHIFT 22
93 /* Collision detection */
94 #define ADF_IOV_MSG_COLLISION_DETECT_DELAY 10
95 #define ADF_IOV_MSG_ACK_DELAY 2
96 #define ADF_IOV_MSG_ACK_MAX_RETRY 100
97 #define ADF_IOV_MSG_RETRY_DELAY 5
98 #define ADF_IOV_MSG_MAX_RETRIES 3
99 #define ADF_IOV_MSG_RESP_TIMEOUT (ADF_IOV_MSG_ACK_DELAY * \
100 ADF_IOV_MSG_ACK_MAX_RETRY + \
101 ADF_IOV_MSG_COLLISION_DETECT_DELAY)
102 #endif /* ADF_IOV_MSG_H */