1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #ifndef ADF_C3XXX_HW_DATA_H_
4 #define ADF_C3XXX_HW_DATA_H_
6 /* PCIe configuration space */
7 #define ADF_C3XXX_PMISC_BAR 0
8 #define ADF_C3XXX_ETR_BAR 1
9 #define ADF_C3XXX_RX_RINGS_OFFSET 8
10 #define ADF_C3XXX_TX_RINGS_MASK 0xFF
11 #define ADF_C3XXX_MAX_ACCELERATORS 3
12 #define ADF_C3XXX_MAX_ACCELENGINES 6
13 #define ADF_C3XXX_ACCELERATORS_REG_OFFSET 16
14 #define ADF_C3XXX_ACCELERATORS_MASK 0x7
15 #define ADF_C3XXX_ACCELENGINES_MASK 0x3F
16 #define ADF_C3XXX_ETR_MAX_BANKS 16
17 #define ADF_C3XXX_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
18 #define ADF_C3XXX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
19 #define ADF_C3XXX_SMIA0_MASK 0xFFFF
20 #define ADF_C3XXX_SMIA1_MASK 0x1
21 #define ADF_C3XXX_SOFTSTRAP_CSR_OFFSET 0x2EC
22 /* Error detection and correction */
23 #define ADF_C3XXX_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
24 #define ADF_C3XXX_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960)
25 #define ADF_C3XXX_ENABLE_AE_ECC_ERR BIT(28)
26 #define ADF_C3XXX_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
27 #define ADF_C3XXX_UERRSSMSH(i) (i * 0x4000 + 0x18)
28 #define ADF_C3XXX_CERRSSMSH(i) (i * 0x4000 + 0x10)
29 #define ADF_C3XXX_ERRSSMSH_EN BIT(3)
31 #define ADF_C3XXX_PF2VF_OFFSET(i) (0x3A000 + 0x280 + ((i) * 0x04))
32 #define ADF_C3XXX_VINTMSK_OFFSET(i) (0x3A000 + 0x200 + ((i) * 0x04))
35 #define ADF_C3XXX_FW "/*(DEBLOBBED)*/"
36 #define ADF_C3XXX_MMP "/*(DEBLOBBED)*/"
38 void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data);
39 void adf_clean_hw_data_c3xxx(struct adf_hw_device_data *hw_data);