1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #include <adf_accel_devices.h>
4 #include <adf_common_drv.h>
5 #include <adf_pf2vf_msg.h>
6 #include "adf_c3xxx_hw_data.h"
8 /* Worker thread to service arbiter mappings based on dev SKUs */
9 static const u32 thrd_to_arb_map_6_me_sku[] = {
10 0x12222AAA, 0x11222AAA, 0x12222AAA,
11 0x11222AAA, 0x12222AAA, 0x11222AAA
14 static struct adf_hw_device_class c3xxx_class = {
15 .name = ADF_C3XXX_DEVICE_NAME,
20 static u32 get_accel_mask(struct adf_hw_device_data *self)
22 u32 straps = self->straps;
23 u32 fuses = self->fuses;
26 accel = ~(fuses | straps) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET;
27 accel &= ADF_C3XXX_ACCELERATORS_MASK;
32 static u32 get_ae_mask(struct adf_hw_device_data *self)
34 u32 straps = self->straps;
35 u32 fuses = self->fuses;
36 unsigned long disabled;
40 /* If an accel is disabled, then disable the corresponding two AEs */
41 disabled = ~get_accel_mask(self) & ADF_C3XXX_ACCELERATORS_MASK;
42 ae_disable = BIT(1) | BIT(0);
43 for_each_set_bit(accel, &disabled, ADF_C3XXX_MAX_ACCELERATORS)
44 straps |= ae_disable << (accel << 1);
46 return ~(fuses | straps) & ADF_C3XXX_ACCELENGINES_MASK;
49 static u32 get_num_accels(struct adf_hw_device_data *self)
53 if (!self || !self->accel_mask)
56 for (i = 0; i < ADF_C3XXX_MAX_ACCELERATORS; i++) {
57 if (self->accel_mask & (1 << i))
63 static u32 get_num_aes(struct adf_hw_device_data *self)
67 if (!self || !self->ae_mask)
70 for (i = 0; i < ADF_C3XXX_MAX_ACCELENGINES; i++) {
71 if (self->ae_mask & (1 << i))
77 static u32 get_misc_bar_id(struct adf_hw_device_data *self)
79 return ADF_C3XXX_PMISC_BAR;
82 static u32 get_etr_bar_id(struct adf_hw_device_data *self)
84 return ADF_C3XXX_ETR_BAR;
87 static u32 get_sram_bar_id(struct adf_hw_device_data *self)
92 static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
94 int aes = get_num_aes(self);
99 return DEV_SKU_UNKNOWN;
102 static void adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev,
103 u32 const **arb_map_config)
105 switch (accel_dev->accel_pci_dev.sku) {
107 *arb_map_config = thrd_to_arb_map_6_me_sku;
110 dev_err(&GET_DEV(accel_dev),
111 "The configuration doesn't match any SKU");
112 *arb_map_config = NULL;
116 static u32 get_pf2vf_offset(u32 i)
118 return ADF_C3XXX_PF2VF_OFFSET(i);
121 static u32 get_vintmsk_offset(u32 i)
123 return ADF_C3XXX_VINTMSK_OFFSET(i);
126 static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
128 struct adf_hw_device_data *hw_device = accel_dev->hw_device;
129 struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_C3XXX_PMISC_BAR];
130 unsigned long accel_mask = hw_device->accel_mask;
131 unsigned long ae_mask = hw_device->ae_mask;
132 void __iomem *csr = misc_bar->virt_addr;
135 /* Enable Accel Engine error detection & correction */
136 for_each_set_bit(i, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) {
137 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_CTX_ENABLES(i));
138 val |= ADF_C3XXX_ENABLE_AE_ECC_ERR;
139 ADF_CSR_WR(csr, ADF_C3XXX_AE_CTX_ENABLES(i), val);
140 val = ADF_CSR_RD(csr, ADF_C3XXX_AE_MISC_CONTROL(i));
141 val |= ADF_C3XXX_ENABLE_AE_ECC_PARITY_CORR;
142 ADF_CSR_WR(csr, ADF_C3XXX_AE_MISC_CONTROL(i), val);
145 /* Enable shared memory error detection & correction */
146 for_each_set_bit(i, &accel_mask, ADF_C3XXX_MAX_ACCELERATORS) {
147 val = ADF_CSR_RD(csr, ADF_C3XXX_UERRSSMSH(i));
148 val |= ADF_C3XXX_ERRSSMSH_EN;
149 ADF_CSR_WR(csr, ADF_C3XXX_UERRSSMSH(i), val);
150 val = ADF_CSR_RD(csr, ADF_C3XXX_CERRSSMSH(i));
151 val |= ADF_C3XXX_ERRSSMSH_EN;
152 ADF_CSR_WR(csr, ADF_C3XXX_CERRSSMSH(i), val);
156 static void adf_enable_ints(struct adf_accel_dev *accel_dev)
160 addr = (&GET_BARS(accel_dev)[ADF_C3XXX_PMISC_BAR])->virt_addr;
162 /* Enable bundle and misc interrupts */
163 ADF_CSR_WR(addr, ADF_C3XXX_SMIAPF0_MASK_OFFSET,
164 ADF_C3XXX_SMIA0_MASK);
165 ADF_CSR_WR(addr, ADF_C3XXX_SMIAPF1_MASK_OFFSET,
166 ADF_C3XXX_SMIA1_MASK);
169 static int adf_pf_enable_vf2pf_comms(struct adf_accel_dev *accel_dev)
174 void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
176 hw_data->dev_class = &c3xxx_class;
177 hw_data->instance_id = c3xxx_class.instances++;
178 hw_data->num_banks = ADF_C3XXX_ETR_MAX_BANKS;
179 hw_data->num_accel = ADF_C3XXX_MAX_ACCELERATORS;
180 hw_data->num_logical_accel = 1;
181 hw_data->num_engines = ADF_C3XXX_MAX_ACCELENGINES;
182 hw_data->tx_rx_gap = ADF_C3XXX_RX_RINGS_OFFSET;
183 hw_data->tx_rings_mask = ADF_C3XXX_TX_RINGS_MASK;
184 hw_data->alloc_irq = adf_isr_resource_alloc;
185 hw_data->free_irq = adf_isr_resource_free;
186 hw_data->enable_error_correction = adf_enable_error_correction;
187 hw_data->get_accel_mask = get_accel_mask;
188 hw_data->get_ae_mask = get_ae_mask;
189 hw_data->get_num_accels = get_num_accels;
190 hw_data->get_num_aes = get_num_aes;
191 hw_data->get_sram_bar_id = get_sram_bar_id;
192 hw_data->get_etr_bar_id = get_etr_bar_id;
193 hw_data->get_misc_bar_id = get_misc_bar_id;
194 hw_data->get_pf2vf_offset = get_pf2vf_offset;
195 hw_data->get_vintmsk_offset = get_vintmsk_offset;
196 hw_data->get_sku = get_sku;
197 hw_data->fw_name = ADF_C3XXX_FW;
198 hw_data->fw_mmp_name = ADF_C3XXX_MMP;
199 hw_data->init_admin_comms = adf_init_admin_comms;
200 hw_data->exit_admin_comms = adf_exit_admin_comms;
201 hw_data->disable_iov = adf_disable_sriov;
202 hw_data->send_admin_init = adf_send_admin_init;
203 hw_data->init_arb = adf_init_arb;
204 hw_data->exit_arb = adf_exit_arb;
205 hw_data->get_arb_mapping = adf_get_arbiter_mapping;
206 hw_data->enable_ints = adf_enable_ints;
207 hw_data->enable_vf2pf_comms = adf_pf_enable_vf2pf_comms;
208 hw_data->reset_device = adf_reset_flr;
209 hw_data->min_iov_compat_ver = ADF_PFVF_COMPATIBILITY_VERSION;
212 void adf_clean_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
214 hw_data->dev_class->instances--;