4 * Support for OMAP SHA1/MD5 HW acceleration.
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
8 * Copyright (c) 2011 Texas Instruments Incorporated
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
14 * Some ideas are from old omap-sha1-md5.c driver.
17 #define pr_fmt(fmt) "%s: " fmt, __func__
19 #include <linux/err.h>
20 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/irq.h>
28 #include <linux/platform_device.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/of_device.h>
35 #include <linux/of_address.h>
36 #include <linux/of_irq.h>
37 #include <linux/delay.h>
38 #include <linux/crypto.h>
39 #include <linux/cryptohash.h>
40 #include <crypto/scatterwalk.h>
41 #include <crypto/algapi.h>
42 #include <crypto/sha.h>
43 #include <crypto/hash.h>
44 #include <crypto/internal/hash.h>
46 #define MD5_DIGEST_SIZE 16
48 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04))
49 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04))
50 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs)
52 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04))
54 #define SHA_REG_CTRL 0x18
55 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
56 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
57 #define SHA_REG_CTRL_ALGO_CONST (1 << 3)
58 #define SHA_REG_CTRL_ALGO (1 << 2)
59 #define SHA_REG_CTRL_INPUT_READY (1 << 1)
60 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
62 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs)
64 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs)
65 #define SHA_REG_MASK_DMA_EN (1 << 3)
66 #define SHA_REG_MASK_IT_EN (1 << 2)
67 #define SHA_REG_MASK_SOFTRESET (1 << 1)
68 #define SHA_REG_AUTOIDLE (1 << 0)
70 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs)
71 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
73 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs)
74 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7)
75 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5)
76 #define SHA_REG_MODE_CLOSE_HASH (1 << 4)
77 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3)
79 #define SHA_REG_MODE_ALGO_MASK (7 << 0)
80 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1)
81 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1)
82 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1)
83 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1)
84 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0)
85 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0)
87 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs)
89 #define SHA_REG_IRQSTATUS 0x118
90 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3)
91 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
92 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1)
93 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0)
95 #define SHA_REG_IRQENA 0x11C
96 #define SHA_REG_IRQENA_CTX_RDY (1 << 3)
97 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2)
98 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1)
99 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0)
101 #define DEFAULT_TIMEOUT_INTERVAL HZ
103 #define DEFAULT_AUTOSUSPEND_DELAY 1000
105 /* mostly device flags */
107 #define FLAGS_FINAL 1
108 #define FLAGS_DMA_ACTIVE 2
109 #define FLAGS_OUTPUT_READY 3
112 #define FLAGS_DMA_READY 6
113 #define FLAGS_AUTO_XOR 7
114 #define FLAGS_BE32_SHA1 8
115 #define FLAGS_SGS_COPIED 9
116 #define FLAGS_SGS_ALLOCED 10
118 #define FLAGS_FINUP 16
120 #define FLAGS_MODE_SHIFT 18
121 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
122 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
123 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
124 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
125 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
126 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
127 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
129 #define FLAGS_HMAC 21
130 #define FLAGS_ERROR 22
135 #define OMAP_ALIGN_MASK (sizeof(u32)-1)
136 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
138 #define BUFLEN SHA512_BLOCK_SIZE
139 #define OMAP_SHA_DMA_THRESHOLD 256
141 struct omap_sham_dev;
143 struct omap_sham_reqctx {
144 struct omap_sham_dev *dd;
148 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
154 struct scatterlist *sg;
155 struct scatterlist sgl[2];
156 int offset; /* offset in current sg */
158 unsigned int total; /* total request */
160 u8 buffer[0] OMAP_ALIGNED;
163 struct omap_sham_hmac_ctx {
164 struct crypto_shash *shash;
165 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
166 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
169 struct omap_sham_ctx {
173 struct crypto_shash *fallback;
175 struct omap_sham_hmac_ctx base[0];
178 #define OMAP_SHAM_QUEUE_LENGTH 10
180 struct omap_sham_algs_info {
181 struct ahash_alg *algs_list;
183 unsigned int registered;
186 struct omap_sham_pdata {
187 struct omap_sham_algs_info *algs_info;
188 unsigned int algs_info_size;
192 void (*copy_hash)(struct ahash_request *req, int out);
193 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
195 void (*trigger)(struct omap_sham_dev *dd, size_t length);
196 int (*poll_irq)(struct omap_sham_dev *dd);
197 irqreturn_t (*intr_hdlr)(int irq, void *dev_id);
215 struct omap_sham_dev {
216 struct list_head list;
217 unsigned long phys_base;
219 void __iomem *io_base;
223 struct dma_chan *dma_lch;
224 struct tasklet_struct done_task;
229 struct crypto_queue queue;
230 struct ahash_request *req;
232 const struct omap_sham_pdata *pdata;
235 struct omap_sham_drv {
236 struct list_head dev_list;
241 static struct omap_sham_drv sham = {
242 .dev_list = LIST_HEAD_INIT(sham.dev_list),
243 .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
246 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
248 return __raw_readl(dd->io_base + offset);
251 static inline void omap_sham_write(struct omap_sham_dev *dd,
252 u32 offset, u32 value)
254 __raw_writel(value, dd->io_base + offset);
257 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
262 val = omap_sham_read(dd, address);
265 omap_sham_write(dd, address, val);
268 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
270 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
272 while (!(omap_sham_read(dd, offset) & bit)) {
273 if (time_is_before_jiffies(timeout))
280 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
282 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
283 struct omap_sham_dev *dd = ctx->dd;
284 u32 *hash = (u32 *)ctx->digest;
287 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
289 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
291 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
295 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
297 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
298 struct omap_sham_dev *dd = ctx->dd;
301 if (ctx->flags & BIT(FLAGS_HMAC)) {
302 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
303 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
304 struct omap_sham_hmac_ctx *bctx = tctx->base;
305 u32 *opad = (u32 *)bctx->opad;
307 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
309 opad[i] = omap_sham_read(dd,
310 SHA_REG_ODIGEST(dd, i));
312 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
317 omap_sham_copy_hash_omap2(req, out);
320 static void omap_sham_copy_ready_hash(struct ahash_request *req)
322 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
323 u32 *in = (u32 *)ctx->digest;
324 u32 *hash = (u32 *)req->result;
325 int i, d, big_endian = 0;
330 switch (ctx->flags & FLAGS_MODE_MASK) {
332 d = MD5_DIGEST_SIZE / sizeof(u32);
334 case FLAGS_MODE_SHA1:
335 /* OMAP2 SHA1 is big endian */
336 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
338 d = SHA1_DIGEST_SIZE / sizeof(u32);
340 case FLAGS_MODE_SHA224:
341 d = SHA224_DIGEST_SIZE / sizeof(u32);
343 case FLAGS_MODE_SHA256:
344 d = SHA256_DIGEST_SIZE / sizeof(u32);
346 case FLAGS_MODE_SHA384:
347 d = SHA384_DIGEST_SIZE / sizeof(u32);
349 case FLAGS_MODE_SHA512:
350 d = SHA512_DIGEST_SIZE / sizeof(u32);
357 for (i = 0; i < d; i++)
358 hash[i] = be32_to_cpu(in[i]);
360 for (i = 0; i < d; i++)
361 hash[i] = le32_to_cpu(in[i]);
364 static int omap_sham_hw_init(struct omap_sham_dev *dd)
368 err = pm_runtime_get_sync(dd->dev);
370 dev_err(dd->dev, "failed to get sync: %d\n", err);
374 if (!test_bit(FLAGS_INIT, &dd->flags)) {
375 set_bit(FLAGS_INIT, &dd->flags);
382 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
385 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
386 u32 val = length << 5, mask;
388 if (likely(ctx->digcnt))
389 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
391 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
392 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
393 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
395 * Setting ALGO_CONST only for the first iteration
396 * and CLOSE_HASH only for the last one.
398 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
399 val |= SHA_REG_CTRL_ALGO;
401 val |= SHA_REG_CTRL_ALGO_CONST;
403 val |= SHA_REG_CTRL_CLOSE_HASH;
405 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
406 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
408 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
411 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
415 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
417 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
420 static int get_block_size(struct omap_sham_reqctx *ctx)
424 switch (ctx->flags & FLAGS_MODE_MASK) {
426 case FLAGS_MODE_SHA1:
429 case FLAGS_MODE_SHA224:
430 case FLAGS_MODE_SHA256:
431 d = SHA256_BLOCK_SIZE;
433 case FLAGS_MODE_SHA384:
434 case FLAGS_MODE_SHA512:
435 d = SHA512_BLOCK_SIZE;
444 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
445 u32 *value, int count)
447 for (; count--; value++, offset += 4)
448 omap_sham_write(dd, offset, *value);
451 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
454 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
457 if (likely(ctx->digcnt))
458 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
461 * Setting ALGO_CONST only for the first iteration and
462 * CLOSE_HASH only for the last one. Note that flags mode bits
463 * correspond to algorithm encoding in mode register.
465 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
467 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
468 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
469 struct omap_sham_hmac_ctx *bctx = tctx->base;
472 val |= SHA_REG_MODE_ALGO_CONSTANT;
474 if (ctx->flags & BIT(FLAGS_HMAC)) {
475 bs = get_block_size(ctx);
476 nr_dr = bs / (2 * sizeof(u32));
477 val |= SHA_REG_MODE_HMAC_KEY_PROC;
478 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
479 (u32 *)bctx->ipad, nr_dr);
480 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
481 (u32 *)bctx->ipad + nr_dr, nr_dr);
487 val |= SHA_REG_MODE_CLOSE_HASH;
489 if (ctx->flags & BIT(FLAGS_HMAC))
490 val |= SHA_REG_MODE_HMAC_OUTER_HASH;
493 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
494 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
495 SHA_REG_MODE_HMAC_KEY_PROC;
497 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
498 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
499 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
500 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
502 (dma ? SHA_REG_MASK_DMA_EN : 0),
503 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
506 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
508 omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
511 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
513 return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
514 SHA_REG_IRQSTATUS_INPUT_RDY);
517 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
520 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
521 int count, len32, bs32, offset = 0;
524 struct sg_mapping_iter mi;
526 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
527 ctx->digcnt, length, final);
529 dd->pdata->write_ctrl(dd, length, final, 0);
530 dd->pdata->trigger(dd, length);
532 /* should be non-zero before next lines to disable clocks later */
533 ctx->digcnt += length;
534 ctx->total -= length;
537 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
539 set_bit(FLAGS_CPU, &dd->flags);
541 len32 = DIV_ROUND_UP(length, sizeof(u32));
542 bs32 = get_block_size(ctx) / sizeof(u32);
544 sg_miter_start(&mi, ctx->sg, ctx->sg_len,
545 SG_MITER_FROM_SG | SG_MITER_ATOMIC);
550 if (dd->pdata->poll_irq(dd))
553 for (count = 0; count < min(len32, bs32); count++, offset++) {
558 pr_err("sg miter failure.\n");
564 omap_sham_write(dd, SHA_REG_DIN(dd, count),
568 len32 -= min(len32, bs32);
576 static void omap_sham_dma_callback(void *param)
578 struct omap_sham_dev *dd = param;
580 set_bit(FLAGS_DMA_READY, &dd->flags);
581 tasklet_schedule(&dd->done_task);
584 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
587 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
588 struct dma_async_tx_descriptor *tx;
589 struct dma_slave_config cfg;
592 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
593 ctx->digcnt, length, final);
595 if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
596 dev_err(dd->dev, "dma_map_sg error\n");
600 memset(&cfg, 0, sizeof(cfg));
602 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
603 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
604 cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
606 ret = dmaengine_slave_config(dd->dma_lch, &cfg);
608 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
612 tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
614 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
617 dev_err(dd->dev, "prep_slave_sg failed\n");
621 tx->callback = omap_sham_dma_callback;
622 tx->callback_param = dd;
624 dd->pdata->write_ctrl(dd, length, final, 1);
626 ctx->digcnt += length;
627 ctx->total -= length;
630 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
632 set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
634 dmaengine_submit(tx);
635 dma_async_issue_pending(dd->dma_lch);
637 dd->pdata->trigger(dd, length);
642 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
643 struct scatterlist *sg, int bs, int new_len)
645 int n = sg_nents(sg);
646 struct scatterlist *tmp;
647 int offset = ctx->offset;
652 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
656 sg_init_table(ctx->sg, n);
663 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
668 while (sg && new_len) {
669 int len = sg->length - offset;
672 offset -= sg->length;
682 sg_set_page(tmp, sg_page(sg), len, sg->offset);
692 set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
699 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
700 struct scatterlist *sg, int bs, int new_len)
706 len = new_len + ctx->bufcnt;
708 pages = get_order(ctx->total);
710 buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
712 pr_err("Couldn't allocate pages for unaligned cases.\n");
717 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
719 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
720 ctx->total - ctx->bufcnt, 0);
721 sg_init_table(ctx->sgl, 1);
722 sg_set_buf(ctx->sgl, buf, len);
724 set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
732 static int omap_sham_align_sgs(struct scatterlist *sg,
733 int nbytes, int bs, bool final,
734 struct omap_sham_reqctx *rctx)
739 struct scatterlist *sg_tmp = sg;
741 int offset = rctx->offset;
743 if (!sg || !sg->length || !nbytes)
752 new_len = DIV_ROUND_UP(new_len, bs) * bs;
754 new_len = (new_len - 1) / bs * bs;
756 if (nbytes != new_len)
759 while (nbytes > 0 && sg_tmp) {
762 if (offset < sg_tmp->length) {
763 if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
768 if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
775 offset -= sg_tmp->length;
781 nbytes -= sg_tmp->length;
784 sg_tmp = sg_next(sg_tmp);
793 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
795 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
803 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
805 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
809 bool final = rctx->flags & BIT(FLAGS_FINUP);
810 int xmit_len, hash_later;
815 bs = get_block_size(rctx);
818 nbytes = req->nbytes;
822 rctx->total = nbytes + rctx->bufcnt;
827 if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
828 int len = bs - rctx->bufcnt % bs;
832 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
840 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
842 ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
846 xmit_len = rctx->total;
848 if (!IS_ALIGNED(xmit_len, bs)) {
850 xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs;
852 xmit_len = xmit_len / bs * bs;
857 hash_later = rctx->total - xmit_len;
861 if (rctx->bufcnt && nbytes) {
862 /* have data from previous operation and current */
863 sg_init_table(rctx->sgl, 2);
864 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
866 sg_chain(rctx->sgl, 2, req->src);
868 rctx->sg = rctx->sgl;
871 } else if (rctx->bufcnt) {
872 /* have buffered data only */
873 sg_init_table(rctx->sgl, 1);
874 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len);
876 rctx->sg = rctx->sgl;
884 if (hash_later > req->nbytes) {
885 memcpy(rctx->buffer, rctx->buffer + xmit_len,
886 hash_later - req->nbytes);
887 offset = hash_later - req->nbytes;
891 scatterwalk_map_and_copy(rctx->buffer + offset,
893 offset + req->nbytes -
894 hash_later, hash_later, 0);
897 rctx->bufcnt = hash_later;
903 rctx->total = xmit_len;
908 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
910 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
912 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
914 clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
919 struct omap_sham_dev *omap_sham_find_dev(struct omap_sham_reqctx *ctx)
921 struct omap_sham_dev *dd;
926 spin_lock_bh(&sham.lock);
927 dd = list_first_entry(&sham.dev_list, struct omap_sham_dev, list);
928 list_move_tail(&dd->list, &sham.dev_list);
930 spin_unlock_bh(&sham.lock);
935 static int omap_sham_init(struct ahash_request *req)
937 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
938 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
939 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
940 struct omap_sham_dev *dd;
945 dd = omap_sham_find_dev(ctx);
951 dev_dbg(dd->dev, "init: digest size: %d\n",
952 crypto_ahash_digestsize(tfm));
954 switch (crypto_ahash_digestsize(tfm)) {
955 case MD5_DIGEST_SIZE:
956 ctx->flags |= FLAGS_MODE_MD5;
957 bs = SHA1_BLOCK_SIZE;
959 case SHA1_DIGEST_SIZE:
960 ctx->flags |= FLAGS_MODE_SHA1;
961 bs = SHA1_BLOCK_SIZE;
963 case SHA224_DIGEST_SIZE:
964 ctx->flags |= FLAGS_MODE_SHA224;
965 bs = SHA224_BLOCK_SIZE;
967 case SHA256_DIGEST_SIZE:
968 ctx->flags |= FLAGS_MODE_SHA256;
969 bs = SHA256_BLOCK_SIZE;
971 case SHA384_DIGEST_SIZE:
972 ctx->flags |= FLAGS_MODE_SHA384;
973 bs = SHA384_BLOCK_SIZE;
975 case SHA512_DIGEST_SIZE:
976 ctx->flags |= FLAGS_MODE_SHA512;
977 bs = SHA512_BLOCK_SIZE;
985 ctx->buflen = BUFLEN;
987 if (tctx->flags & BIT(FLAGS_HMAC)) {
988 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
989 struct omap_sham_hmac_ctx *bctx = tctx->base;
991 memcpy(ctx->buffer, bctx->ipad, bs);
995 ctx->flags |= BIT(FLAGS_HMAC);
1002 static int omap_sham_update_req(struct omap_sham_dev *dd)
1004 struct ahash_request *req = dd->req;
1005 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1007 bool final = ctx->flags & BIT(FLAGS_FINUP);
1009 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
1010 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
1012 if (ctx->total < get_block_size(ctx) ||
1013 ctx->total < OMAP_SHA_DMA_THRESHOLD)
1014 ctx->flags |= BIT(FLAGS_CPU);
1016 if (ctx->flags & BIT(FLAGS_CPU))
1017 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1019 err = omap_sham_xmit_dma(dd, ctx->total, final);
1021 /* wait for dma completion before can take more data */
1022 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1027 static int omap_sham_final_req(struct omap_sham_dev *dd)
1029 struct ahash_request *req = dd->req;
1030 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1031 int err = 0, use_dma = 1;
1033 if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1035 * faster to handle last block with cpu or
1036 * use cpu when dma is not present.
1041 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1043 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1047 dev_dbg(dd->dev, "final_req: err: %d\n", err);
1052 static int omap_sham_finish_hmac(struct ahash_request *req)
1054 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1055 struct omap_sham_hmac_ctx *bctx = tctx->base;
1056 int bs = crypto_shash_blocksize(bctx->shash);
1057 int ds = crypto_shash_digestsize(bctx->shash);
1058 SHASH_DESC_ON_STACK(shash, bctx->shash);
1060 shash->tfm = bctx->shash;
1061 shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
1063 return crypto_shash_init(shash) ?:
1064 crypto_shash_update(shash, bctx->opad, bs) ?:
1065 crypto_shash_finup(shash, req->result, ds, req->result);
1068 static int omap_sham_finish(struct ahash_request *req)
1070 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1071 struct omap_sham_dev *dd = ctx->dd;
1075 omap_sham_copy_ready_hash(req);
1076 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1077 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1078 err = omap_sham_finish_hmac(req);
1081 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1086 static void omap_sham_finish_req(struct ahash_request *req, int err)
1088 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1089 struct omap_sham_dev *dd = ctx->dd;
1091 if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1092 free_pages((unsigned long)sg_virt(ctx->sg),
1093 get_order(ctx->sg->length + ctx->bufcnt));
1095 if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1100 dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1103 dd->pdata->copy_hash(req, 1);
1104 if (test_bit(FLAGS_FINAL, &dd->flags))
1105 err = omap_sham_finish(req);
1107 ctx->flags |= BIT(FLAGS_ERROR);
1110 /* atomic operation is not needed here */
1111 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1112 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1114 pm_runtime_mark_last_busy(dd->dev);
1115 pm_runtime_put_autosuspend(dd->dev);
1117 if (req->base.complete)
1118 req->base.complete(&req->base, err);
1121 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1122 struct ahash_request *req)
1124 struct crypto_async_request *async_req, *backlog;
1125 struct omap_sham_reqctx *ctx;
1126 unsigned long flags;
1127 int err = 0, ret = 0;
1130 spin_lock_irqsave(&dd->lock, flags);
1132 ret = ahash_enqueue_request(&dd->queue, req);
1133 if (test_bit(FLAGS_BUSY, &dd->flags)) {
1134 spin_unlock_irqrestore(&dd->lock, flags);
1137 backlog = crypto_get_backlog(&dd->queue);
1138 async_req = crypto_dequeue_request(&dd->queue);
1140 set_bit(FLAGS_BUSY, &dd->flags);
1141 spin_unlock_irqrestore(&dd->lock, flags);
1147 backlog->complete(backlog, -EINPROGRESS);
1149 req = ahash_request_cast(async_req);
1151 ctx = ahash_request_ctx(req);
1153 err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1154 if (err || !ctx->total)
1157 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1158 ctx->op, req->nbytes);
1160 err = omap_sham_hw_init(dd);
1165 /* request has changed - restore hash */
1166 dd->pdata->copy_hash(req, 0);
1168 if (ctx->op == OP_UPDATE) {
1169 err = omap_sham_update_req(dd);
1170 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1171 /* no final() after finup() */
1172 err = omap_sham_final_req(dd);
1173 } else if (ctx->op == OP_FINAL) {
1174 err = omap_sham_final_req(dd);
1177 dev_dbg(dd->dev, "exit, err: %d\n", err);
1179 if (err != -EINPROGRESS) {
1180 /* done_task will not finish it, so do it here */
1181 omap_sham_finish_req(req, err);
1185 * Execute next request immediately if there is anything
1194 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1196 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1197 struct omap_sham_dev *dd = ctx->dd;
1201 return omap_sham_handle_queue(dd, req);
1204 static int omap_sham_update(struct ahash_request *req)
1206 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1207 struct omap_sham_dev *dd = omap_sham_find_dev(ctx);
1212 if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1213 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1215 ctx->bufcnt += req->nbytes;
1219 if (dd->polling_mode)
1220 ctx->flags |= BIT(FLAGS_CPU);
1222 return omap_sham_enqueue(req, OP_UPDATE);
1225 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1226 const u8 *data, unsigned int len, u8 *out)
1228 SHASH_DESC_ON_STACK(shash, tfm);
1231 shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1233 return crypto_shash_digest(shash, data, len, out);
1236 static int omap_sham_final_shash(struct ahash_request *req)
1238 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1239 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1243 * If we are running HMAC on limited hardware support, skip
1244 * the ipad in the beginning of the buffer if we are going for
1245 * software fallback algorithm.
1247 if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1248 !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1249 offset = get_block_size(ctx);
1251 return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1252 ctx->buffer + offset,
1253 ctx->bufcnt - offset, req->result);
1256 static int omap_sham_final(struct ahash_request *req)
1258 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1260 ctx->flags |= BIT(FLAGS_FINUP);
1262 if (ctx->flags & BIT(FLAGS_ERROR))
1263 return 0; /* uncompleted hash is not needed */
1266 * OMAP HW accel works only with buffers >= 9.
1267 * HMAC is always >= 9 because ipad == block size.
1268 * If buffersize is less than DMA_THRESHOLD, we use fallback
1269 * SW encoding, as using DMA + HW in this case doesn't provide
1272 if (!ctx->digcnt && ctx->bufcnt < OMAP_SHA_DMA_THRESHOLD)
1273 return omap_sham_final_shash(req);
1274 else if (ctx->bufcnt)
1275 return omap_sham_enqueue(req, OP_FINAL);
1277 /* copy ready hash (+ finalize hmac) */
1278 return omap_sham_finish(req);
1281 static int omap_sham_finup(struct ahash_request *req)
1283 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1286 ctx->flags |= BIT(FLAGS_FINUP);
1288 err1 = omap_sham_update(req);
1289 if (err1 == -EINPROGRESS || err1 == -EBUSY)
1292 * final() has to be always called to cleanup resources
1293 * even if udpate() failed, except EINPROGRESS
1295 err2 = omap_sham_final(req);
1297 return err1 ?: err2;
1300 static int omap_sham_digest(struct ahash_request *req)
1302 return omap_sham_init(req) ?: omap_sham_finup(req);
1305 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1306 unsigned int keylen)
1308 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1309 struct omap_sham_hmac_ctx *bctx = tctx->base;
1310 int bs = crypto_shash_blocksize(bctx->shash);
1311 int ds = crypto_shash_digestsize(bctx->shash);
1314 err = crypto_shash_setkey(tctx->fallback, key, keylen);
1319 err = omap_sham_shash_digest(bctx->shash,
1320 crypto_shash_get_flags(bctx->shash),
1321 key, keylen, bctx->ipad);
1326 memcpy(bctx->ipad, key, keylen);
1329 memset(bctx->ipad + keylen, 0, bs - keylen);
1331 if (!test_bit(FLAGS_AUTO_XOR, &sham.flags)) {
1332 memcpy(bctx->opad, bctx->ipad, bs);
1334 for (i = 0; i < bs; i++) {
1335 bctx->ipad[i] ^= 0x36;
1336 bctx->opad[i] ^= 0x5c;
1343 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1345 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1346 const char *alg_name = crypto_tfm_alg_name(tfm);
1348 /* Allocate a fallback and abort if it failed. */
1349 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1350 CRYPTO_ALG_NEED_FALLBACK);
1351 if (IS_ERR(tctx->fallback)) {
1352 pr_err("omap-sham: fallback driver '%s' "
1353 "could not be loaded.\n", alg_name);
1354 return PTR_ERR(tctx->fallback);
1357 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1358 sizeof(struct omap_sham_reqctx) + BUFLEN);
1361 struct omap_sham_hmac_ctx *bctx = tctx->base;
1362 tctx->flags |= BIT(FLAGS_HMAC);
1363 bctx->shash = crypto_alloc_shash(alg_base, 0,
1364 CRYPTO_ALG_NEED_FALLBACK);
1365 if (IS_ERR(bctx->shash)) {
1366 pr_err("omap-sham: base driver '%s' "
1367 "could not be loaded.\n", alg_base);
1368 crypto_free_shash(tctx->fallback);
1369 return PTR_ERR(bctx->shash);
1377 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1379 return omap_sham_cra_init_alg(tfm, NULL);
1382 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1384 return omap_sham_cra_init_alg(tfm, "sha1");
1387 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1389 return omap_sham_cra_init_alg(tfm, "sha224");
1392 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1394 return omap_sham_cra_init_alg(tfm, "sha256");
1397 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1399 return omap_sham_cra_init_alg(tfm, "md5");
1402 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1404 return omap_sham_cra_init_alg(tfm, "sha384");
1407 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1409 return omap_sham_cra_init_alg(tfm, "sha512");
1412 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1414 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1416 crypto_free_shash(tctx->fallback);
1417 tctx->fallback = NULL;
1419 if (tctx->flags & BIT(FLAGS_HMAC)) {
1420 struct omap_sham_hmac_ctx *bctx = tctx->base;
1421 crypto_free_shash(bctx->shash);
1425 static int omap_sham_export(struct ahash_request *req, void *out)
1427 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1429 memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1434 static int omap_sham_import(struct ahash_request *req, const void *in)
1436 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1437 const struct omap_sham_reqctx *ctx_in = in;
1439 memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1444 static struct ahash_alg algs_sha1_md5[] = {
1446 .init = omap_sham_init,
1447 .update = omap_sham_update,
1448 .final = omap_sham_final,
1449 .finup = omap_sham_finup,
1450 .digest = omap_sham_digest,
1451 .halg.digestsize = SHA1_DIGEST_SIZE,
1454 .cra_driver_name = "omap-sha1",
1455 .cra_priority = 400,
1456 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1457 CRYPTO_ALG_KERN_DRIVER_ONLY |
1459 CRYPTO_ALG_NEED_FALLBACK,
1460 .cra_blocksize = SHA1_BLOCK_SIZE,
1461 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1462 .cra_alignmask = OMAP_ALIGN_MASK,
1463 .cra_module = THIS_MODULE,
1464 .cra_init = omap_sham_cra_init,
1465 .cra_exit = omap_sham_cra_exit,
1469 .init = omap_sham_init,
1470 .update = omap_sham_update,
1471 .final = omap_sham_final,
1472 .finup = omap_sham_finup,
1473 .digest = omap_sham_digest,
1474 .halg.digestsize = MD5_DIGEST_SIZE,
1477 .cra_driver_name = "omap-md5",
1478 .cra_priority = 400,
1479 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1480 CRYPTO_ALG_KERN_DRIVER_ONLY |
1482 CRYPTO_ALG_NEED_FALLBACK,
1483 .cra_blocksize = SHA1_BLOCK_SIZE,
1484 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1485 .cra_alignmask = OMAP_ALIGN_MASK,
1486 .cra_module = THIS_MODULE,
1487 .cra_init = omap_sham_cra_init,
1488 .cra_exit = omap_sham_cra_exit,
1492 .init = omap_sham_init,
1493 .update = omap_sham_update,
1494 .final = omap_sham_final,
1495 .finup = omap_sham_finup,
1496 .digest = omap_sham_digest,
1497 .setkey = omap_sham_setkey,
1498 .halg.digestsize = SHA1_DIGEST_SIZE,
1500 .cra_name = "hmac(sha1)",
1501 .cra_driver_name = "omap-hmac-sha1",
1502 .cra_priority = 400,
1503 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1504 CRYPTO_ALG_KERN_DRIVER_ONLY |
1506 CRYPTO_ALG_NEED_FALLBACK,
1507 .cra_blocksize = SHA1_BLOCK_SIZE,
1508 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1509 sizeof(struct omap_sham_hmac_ctx),
1510 .cra_alignmask = OMAP_ALIGN_MASK,
1511 .cra_module = THIS_MODULE,
1512 .cra_init = omap_sham_cra_sha1_init,
1513 .cra_exit = omap_sham_cra_exit,
1517 .init = omap_sham_init,
1518 .update = omap_sham_update,
1519 .final = omap_sham_final,
1520 .finup = omap_sham_finup,
1521 .digest = omap_sham_digest,
1522 .setkey = omap_sham_setkey,
1523 .halg.digestsize = MD5_DIGEST_SIZE,
1525 .cra_name = "hmac(md5)",
1526 .cra_driver_name = "omap-hmac-md5",
1527 .cra_priority = 400,
1528 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1529 CRYPTO_ALG_KERN_DRIVER_ONLY |
1531 CRYPTO_ALG_NEED_FALLBACK,
1532 .cra_blocksize = SHA1_BLOCK_SIZE,
1533 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1534 sizeof(struct omap_sham_hmac_ctx),
1535 .cra_alignmask = OMAP_ALIGN_MASK,
1536 .cra_module = THIS_MODULE,
1537 .cra_init = omap_sham_cra_md5_init,
1538 .cra_exit = omap_sham_cra_exit,
1543 /* OMAP4 has some algs in addition to what OMAP2 has */
1544 static struct ahash_alg algs_sha224_sha256[] = {
1546 .init = omap_sham_init,
1547 .update = omap_sham_update,
1548 .final = omap_sham_final,
1549 .finup = omap_sham_finup,
1550 .digest = omap_sham_digest,
1551 .halg.digestsize = SHA224_DIGEST_SIZE,
1553 .cra_name = "sha224",
1554 .cra_driver_name = "omap-sha224",
1555 .cra_priority = 400,
1556 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1558 CRYPTO_ALG_NEED_FALLBACK,
1559 .cra_blocksize = SHA224_BLOCK_SIZE,
1560 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1561 .cra_alignmask = OMAP_ALIGN_MASK,
1562 .cra_module = THIS_MODULE,
1563 .cra_init = omap_sham_cra_init,
1564 .cra_exit = omap_sham_cra_exit,
1568 .init = omap_sham_init,
1569 .update = omap_sham_update,
1570 .final = omap_sham_final,
1571 .finup = omap_sham_finup,
1572 .digest = omap_sham_digest,
1573 .halg.digestsize = SHA256_DIGEST_SIZE,
1575 .cra_name = "sha256",
1576 .cra_driver_name = "omap-sha256",
1577 .cra_priority = 400,
1578 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1580 CRYPTO_ALG_NEED_FALLBACK,
1581 .cra_blocksize = SHA256_BLOCK_SIZE,
1582 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1583 .cra_alignmask = OMAP_ALIGN_MASK,
1584 .cra_module = THIS_MODULE,
1585 .cra_init = omap_sham_cra_init,
1586 .cra_exit = omap_sham_cra_exit,
1590 .init = omap_sham_init,
1591 .update = omap_sham_update,
1592 .final = omap_sham_final,
1593 .finup = omap_sham_finup,
1594 .digest = omap_sham_digest,
1595 .setkey = omap_sham_setkey,
1596 .halg.digestsize = SHA224_DIGEST_SIZE,
1598 .cra_name = "hmac(sha224)",
1599 .cra_driver_name = "omap-hmac-sha224",
1600 .cra_priority = 400,
1601 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1603 CRYPTO_ALG_NEED_FALLBACK,
1604 .cra_blocksize = SHA224_BLOCK_SIZE,
1605 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1606 sizeof(struct omap_sham_hmac_ctx),
1607 .cra_alignmask = OMAP_ALIGN_MASK,
1608 .cra_module = THIS_MODULE,
1609 .cra_init = omap_sham_cra_sha224_init,
1610 .cra_exit = omap_sham_cra_exit,
1614 .init = omap_sham_init,
1615 .update = omap_sham_update,
1616 .final = omap_sham_final,
1617 .finup = omap_sham_finup,
1618 .digest = omap_sham_digest,
1619 .setkey = omap_sham_setkey,
1620 .halg.digestsize = SHA256_DIGEST_SIZE,
1622 .cra_name = "hmac(sha256)",
1623 .cra_driver_name = "omap-hmac-sha256",
1624 .cra_priority = 400,
1625 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1627 CRYPTO_ALG_NEED_FALLBACK,
1628 .cra_blocksize = SHA256_BLOCK_SIZE,
1629 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1630 sizeof(struct omap_sham_hmac_ctx),
1631 .cra_alignmask = OMAP_ALIGN_MASK,
1632 .cra_module = THIS_MODULE,
1633 .cra_init = omap_sham_cra_sha256_init,
1634 .cra_exit = omap_sham_cra_exit,
1639 static struct ahash_alg algs_sha384_sha512[] = {
1641 .init = omap_sham_init,
1642 .update = omap_sham_update,
1643 .final = omap_sham_final,
1644 .finup = omap_sham_finup,
1645 .digest = omap_sham_digest,
1646 .halg.digestsize = SHA384_DIGEST_SIZE,
1648 .cra_name = "sha384",
1649 .cra_driver_name = "omap-sha384",
1650 .cra_priority = 400,
1651 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1653 CRYPTO_ALG_NEED_FALLBACK,
1654 .cra_blocksize = SHA384_BLOCK_SIZE,
1655 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1656 .cra_alignmask = OMAP_ALIGN_MASK,
1657 .cra_module = THIS_MODULE,
1658 .cra_init = omap_sham_cra_init,
1659 .cra_exit = omap_sham_cra_exit,
1663 .init = omap_sham_init,
1664 .update = omap_sham_update,
1665 .final = omap_sham_final,
1666 .finup = omap_sham_finup,
1667 .digest = omap_sham_digest,
1668 .halg.digestsize = SHA512_DIGEST_SIZE,
1670 .cra_name = "sha512",
1671 .cra_driver_name = "omap-sha512",
1672 .cra_priority = 400,
1673 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1675 CRYPTO_ALG_NEED_FALLBACK,
1676 .cra_blocksize = SHA512_BLOCK_SIZE,
1677 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1678 .cra_alignmask = OMAP_ALIGN_MASK,
1679 .cra_module = THIS_MODULE,
1680 .cra_init = omap_sham_cra_init,
1681 .cra_exit = omap_sham_cra_exit,
1685 .init = omap_sham_init,
1686 .update = omap_sham_update,
1687 .final = omap_sham_final,
1688 .finup = omap_sham_finup,
1689 .digest = omap_sham_digest,
1690 .setkey = omap_sham_setkey,
1691 .halg.digestsize = SHA384_DIGEST_SIZE,
1693 .cra_name = "hmac(sha384)",
1694 .cra_driver_name = "omap-hmac-sha384",
1695 .cra_priority = 400,
1696 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1698 CRYPTO_ALG_NEED_FALLBACK,
1699 .cra_blocksize = SHA384_BLOCK_SIZE,
1700 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1701 sizeof(struct omap_sham_hmac_ctx),
1702 .cra_alignmask = OMAP_ALIGN_MASK,
1703 .cra_module = THIS_MODULE,
1704 .cra_init = omap_sham_cra_sha384_init,
1705 .cra_exit = omap_sham_cra_exit,
1709 .init = omap_sham_init,
1710 .update = omap_sham_update,
1711 .final = omap_sham_final,
1712 .finup = omap_sham_finup,
1713 .digest = omap_sham_digest,
1714 .setkey = omap_sham_setkey,
1715 .halg.digestsize = SHA512_DIGEST_SIZE,
1717 .cra_name = "hmac(sha512)",
1718 .cra_driver_name = "omap-hmac-sha512",
1719 .cra_priority = 400,
1720 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1722 CRYPTO_ALG_NEED_FALLBACK,
1723 .cra_blocksize = SHA512_BLOCK_SIZE,
1724 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1725 sizeof(struct omap_sham_hmac_ctx),
1726 .cra_alignmask = OMAP_ALIGN_MASK,
1727 .cra_module = THIS_MODULE,
1728 .cra_init = omap_sham_cra_sha512_init,
1729 .cra_exit = omap_sham_cra_exit,
1734 static void omap_sham_done_task(unsigned long data)
1736 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1739 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1740 omap_sham_handle_queue(dd, NULL);
1744 if (test_bit(FLAGS_CPU, &dd->flags)) {
1745 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1747 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1748 if (test_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1749 omap_sham_update_dma_stop(dd);
1755 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1756 /* hash or semi-hash ready */
1757 clear_bit(FLAGS_DMA_READY, &dd->flags);
1765 dev_dbg(dd->dev, "update done: err: %d\n", err);
1766 /* finish curent request */
1767 omap_sham_finish_req(dd->req, err);
1769 /* If we are not busy, process next req */
1770 if (!test_bit(FLAGS_BUSY, &dd->flags))
1771 omap_sham_handle_queue(dd, NULL);
1774 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1776 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1777 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1779 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1780 tasklet_schedule(&dd->done_task);
1786 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1788 struct omap_sham_dev *dd = dev_id;
1790 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1791 /* final -> allow device to go to power-saving mode */
1792 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1794 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1795 SHA_REG_CTRL_OUTPUT_READY);
1796 omap_sham_read(dd, SHA_REG_CTRL);
1798 return omap_sham_irq_common(dd);
1801 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1803 struct omap_sham_dev *dd = dev_id;
1805 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1807 return omap_sham_irq_common(dd);
1810 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1812 .algs_list = algs_sha1_md5,
1813 .size = ARRAY_SIZE(algs_sha1_md5),
1817 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1818 .algs_info = omap_sham_algs_info_omap2,
1819 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1820 .flags = BIT(FLAGS_BE32_SHA1),
1821 .digest_size = SHA1_DIGEST_SIZE,
1822 .copy_hash = omap_sham_copy_hash_omap2,
1823 .write_ctrl = omap_sham_write_ctrl_omap2,
1824 .trigger = omap_sham_trigger_omap2,
1825 .poll_irq = omap_sham_poll_irq_omap2,
1826 .intr_hdlr = omap_sham_irq_omap2,
1827 .idigest_ofs = 0x00,
1832 .sysstatus_ofs = 0x64,
1840 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1842 .algs_list = algs_sha1_md5,
1843 .size = ARRAY_SIZE(algs_sha1_md5),
1846 .algs_list = algs_sha224_sha256,
1847 .size = ARRAY_SIZE(algs_sha224_sha256),
1851 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1852 .algs_info = omap_sham_algs_info_omap4,
1853 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1854 .flags = BIT(FLAGS_AUTO_XOR),
1855 .digest_size = SHA256_DIGEST_SIZE,
1856 .copy_hash = omap_sham_copy_hash_omap4,
1857 .write_ctrl = omap_sham_write_ctrl_omap4,
1858 .trigger = omap_sham_trigger_omap4,
1859 .poll_irq = omap_sham_poll_irq_omap4,
1860 .intr_hdlr = omap_sham_irq_omap4,
1861 .idigest_ofs = 0x020,
1864 .digcnt_ofs = 0x040,
1867 .sysstatus_ofs = 0x114,
1870 .major_mask = 0x0700,
1872 .minor_mask = 0x003f,
1876 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1878 .algs_list = algs_sha1_md5,
1879 .size = ARRAY_SIZE(algs_sha1_md5),
1882 .algs_list = algs_sha224_sha256,
1883 .size = ARRAY_SIZE(algs_sha224_sha256),
1886 .algs_list = algs_sha384_sha512,
1887 .size = ARRAY_SIZE(algs_sha384_sha512),
1891 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1892 .algs_info = omap_sham_algs_info_omap5,
1893 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1894 .flags = BIT(FLAGS_AUTO_XOR),
1895 .digest_size = SHA512_DIGEST_SIZE,
1896 .copy_hash = omap_sham_copy_hash_omap4,
1897 .write_ctrl = omap_sham_write_ctrl_omap4,
1898 .trigger = omap_sham_trigger_omap4,
1899 .poll_irq = omap_sham_poll_irq_omap4,
1900 .intr_hdlr = omap_sham_irq_omap4,
1901 .idigest_ofs = 0x240,
1902 .odigest_ofs = 0x200,
1904 .digcnt_ofs = 0x280,
1907 .sysstatus_ofs = 0x114,
1909 .length_ofs = 0x288,
1910 .major_mask = 0x0700,
1912 .minor_mask = 0x003f,
1916 static const struct of_device_id omap_sham_of_match[] = {
1918 .compatible = "ti,omap2-sham",
1919 .data = &omap_sham_pdata_omap2,
1922 .compatible = "ti,omap3-sham",
1923 .data = &omap_sham_pdata_omap2,
1926 .compatible = "ti,omap4-sham",
1927 .data = &omap_sham_pdata_omap4,
1930 .compatible = "ti,omap5-sham",
1931 .data = &omap_sham_pdata_omap5,
1935 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1937 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1938 struct device *dev, struct resource *res)
1940 struct device_node *node = dev->of_node;
1941 const struct of_device_id *match;
1944 match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
1946 dev_err(dev, "no compatible OF match\n");
1951 err = of_address_to_resource(node, 0, res);
1953 dev_err(dev, "can't translate OF node address\n");
1958 dd->irq = irq_of_parse_and_map(node, 0);
1960 dev_err(dev, "can't translate OF irq value\n");
1965 dd->pdata = match->data;
1971 static const struct of_device_id omap_sham_of_match[] = {
1975 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1976 struct device *dev, struct resource *res)
1982 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1983 struct platform_device *pdev, struct resource *res)
1985 struct device *dev = &pdev->dev;
1989 /* Get the base address */
1990 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1992 dev_err(dev, "no MEM resource info\n");
1996 memcpy(res, r, sizeof(*res));
1999 dd->irq = platform_get_irq(pdev, 0);
2001 dev_err(dev, "no IRQ resource info\n");
2006 /* Only OMAP2/3 can be non-DT */
2007 dd->pdata = &omap_sham_pdata_omap2;
2013 static int omap_sham_probe(struct platform_device *pdev)
2015 struct omap_sham_dev *dd;
2016 struct device *dev = &pdev->dev;
2017 struct resource res;
2018 dma_cap_mask_t mask;
2022 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2024 dev_err(dev, "unable to alloc data struct.\n");
2029 platform_set_drvdata(pdev, dd);
2031 INIT_LIST_HEAD(&dd->list);
2032 spin_lock_init(&dd->lock);
2033 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2034 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2036 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2037 omap_sham_get_res_pdev(dd, pdev, &res);
2041 dd->io_base = devm_ioremap_resource(dev, &res);
2042 if (IS_ERR(dd->io_base)) {
2043 err = PTR_ERR(dd->io_base);
2046 dd->phys_base = res.start;
2048 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2049 IRQF_TRIGGER_NONE, dev_name(dev), dd);
2051 dev_err(dev, "unable to request irq %d, err = %d\n",
2057 dma_cap_set(DMA_SLAVE, mask);
2059 dd->dma_lch = dma_request_chan(dev, "rx");
2060 if (IS_ERR(dd->dma_lch)) {
2061 err = PTR_ERR(dd->dma_lch);
2062 if (err == -EPROBE_DEFER)
2065 dd->polling_mode = 1;
2066 dev_dbg(dev, "using polling mode instead of dma\n");
2069 dd->flags |= dd->pdata->flags;
2070 sham.flags |= dd->pdata->flags;
2072 pm_runtime_use_autosuspend(dev);
2073 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2075 pm_runtime_enable(dev);
2076 pm_runtime_irq_safe(dev);
2078 err = pm_runtime_get_sync(dev);
2080 dev_err(dev, "failed to get sync: %d\n", err);
2084 rev = omap_sham_read(dd, SHA_REG_REV(dd));
2085 pm_runtime_put_sync(&pdev->dev);
2087 dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2088 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2089 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2091 spin_lock(&sham.lock);
2092 list_add_tail(&dd->list, &sham.dev_list);
2093 spin_unlock(&sham.lock);
2095 for (i = 0; i < dd->pdata->algs_info_size; i++) {
2096 if (dd->pdata->algs_info[i].registered)
2099 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2100 struct ahash_alg *alg;
2102 alg = &dd->pdata->algs_info[i].algs_list[j];
2103 alg->export = omap_sham_export;
2104 alg->import = omap_sham_import;
2105 alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2107 err = crypto_register_ahash(alg);
2111 dd->pdata->algs_info[i].registered++;
2118 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2119 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2120 crypto_unregister_ahash(
2121 &dd->pdata->algs_info[i].algs_list[j]);
2123 pm_runtime_disable(dev);
2124 if (!dd->polling_mode)
2125 dma_release_channel(dd->dma_lch);
2127 dev_err(dev, "initialization failed.\n");
2132 static int omap_sham_remove(struct platform_device *pdev)
2134 static struct omap_sham_dev *dd;
2137 dd = platform_get_drvdata(pdev);
2140 spin_lock(&sham.lock);
2141 list_del(&dd->list);
2142 spin_unlock(&sham.lock);
2143 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2144 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
2145 crypto_unregister_ahash(
2146 &dd->pdata->algs_info[i].algs_list[j]);
2147 dd->pdata->algs_info[i].registered--;
2149 tasklet_kill(&dd->done_task);
2150 pm_runtime_disable(&pdev->dev);
2152 if (!dd->polling_mode)
2153 dma_release_channel(dd->dma_lch);
2158 #ifdef CONFIG_PM_SLEEP
2159 static int omap_sham_suspend(struct device *dev)
2161 pm_runtime_put_sync(dev);
2165 static int omap_sham_resume(struct device *dev)
2167 int err = pm_runtime_get_sync(dev);
2169 dev_err(dev, "failed to get sync: %d\n", err);
2176 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2178 static struct platform_driver omap_sham_driver = {
2179 .probe = omap_sham_probe,
2180 .remove = omap_sham_remove,
2182 .name = "omap-sham",
2183 .pm = &omap_sham_pm_ops,
2184 .of_match_table = omap_sham_of_match,
2188 module_platform_driver(omap_sham_driver);
2190 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2191 MODULE_LICENSE("GPL v2");
2192 MODULE_AUTHOR("Dmitry Kasatkin");
2193 MODULE_ALIAS("platform:omap-sham");