4 * Support for OMAP SHA1/MD5 HW acceleration.
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
8 * Copyright (c) 2011 Texas Instruments Incorporated
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
14 * Some ideas are from old omap-sha1-md5.c driver.
17 #define pr_fmt(fmt) "%s: " fmt, __func__
19 #include <linux/err.h>
20 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/irq.h>
28 #include <linux/platform_device.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/of_device.h>
35 #include <linux/of_address.h>
36 #include <linux/of_irq.h>
37 #include <linux/delay.h>
38 #include <linux/crypto.h>
39 #include <linux/cryptohash.h>
40 #include <crypto/scatterwalk.h>
41 #include <crypto/algapi.h>
42 #include <crypto/sha.h>
43 #include <crypto/hash.h>
44 #include <crypto/hmac.h>
45 #include <crypto/internal/hash.h>
47 #define MD5_DIGEST_SIZE 16
49 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04))
50 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04))
51 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs)
53 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04))
55 #define SHA_REG_CTRL 0x18
56 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
57 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
58 #define SHA_REG_CTRL_ALGO_CONST (1 << 3)
59 #define SHA_REG_CTRL_ALGO (1 << 2)
60 #define SHA_REG_CTRL_INPUT_READY (1 << 1)
61 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
63 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs)
65 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs)
66 #define SHA_REG_MASK_DMA_EN (1 << 3)
67 #define SHA_REG_MASK_IT_EN (1 << 2)
68 #define SHA_REG_MASK_SOFTRESET (1 << 1)
69 #define SHA_REG_AUTOIDLE (1 << 0)
71 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs)
72 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
74 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs)
75 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7)
76 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5)
77 #define SHA_REG_MODE_CLOSE_HASH (1 << 4)
78 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3)
80 #define SHA_REG_MODE_ALGO_MASK (7 << 0)
81 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1)
82 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1)
83 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1)
84 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1)
85 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0)
86 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0)
88 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs)
90 #define SHA_REG_IRQSTATUS 0x118
91 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3)
92 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
93 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1)
94 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0)
96 #define SHA_REG_IRQENA 0x11C
97 #define SHA_REG_IRQENA_CTX_RDY (1 << 3)
98 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2)
99 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1)
100 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0)
102 #define DEFAULT_TIMEOUT_INTERVAL HZ
104 #define DEFAULT_AUTOSUSPEND_DELAY 1000
106 /* mostly device flags */
108 #define FLAGS_FINAL 1
109 #define FLAGS_DMA_ACTIVE 2
110 #define FLAGS_OUTPUT_READY 3
113 #define FLAGS_DMA_READY 6
114 #define FLAGS_AUTO_XOR 7
115 #define FLAGS_BE32_SHA1 8
116 #define FLAGS_SGS_COPIED 9
117 #define FLAGS_SGS_ALLOCED 10
119 #define FLAGS_FINUP 16
121 #define FLAGS_MODE_SHIFT 18
122 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
123 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
124 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
125 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
126 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
127 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
128 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
130 #define FLAGS_HMAC 21
131 #define FLAGS_ERROR 22
136 #define OMAP_ALIGN_MASK (sizeof(u32)-1)
137 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
139 #define BUFLEN SHA512_BLOCK_SIZE
140 #define OMAP_SHA_DMA_THRESHOLD 256
142 struct omap_sham_dev;
144 struct omap_sham_reqctx {
145 struct omap_sham_dev *dd;
149 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
155 struct scatterlist *sg;
156 struct scatterlist sgl[2];
157 int offset; /* offset in current sg */
159 unsigned int total; /* total request */
161 u8 buffer[0] OMAP_ALIGNED;
164 struct omap_sham_hmac_ctx {
165 struct crypto_shash *shash;
166 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
167 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
170 struct omap_sham_ctx {
174 struct crypto_shash *fallback;
176 struct omap_sham_hmac_ctx base[0];
179 #define OMAP_SHAM_QUEUE_LENGTH 10
181 struct omap_sham_algs_info {
182 struct ahash_alg *algs_list;
184 unsigned int registered;
187 struct omap_sham_pdata {
188 struct omap_sham_algs_info *algs_info;
189 unsigned int algs_info_size;
193 void (*copy_hash)(struct ahash_request *req, int out);
194 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
196 void (*trigger)(struct omap_sham_dev *dd, size_t length);
197 int (*poll_irq)(struct omap_sham_dev *dd);
198 irqreturn_t (*intr_hdlr)(int irq, void *dev_id);
216 struct omap_sham_dev {
217 struct list_head list;
218 unsigned long phys_base;
220 void __iomem *io_base;
224 struct dma_chan *dma_lch;
225 struct tasklet_struct done_task;
227 u8 xmit_buf[BUFLEN] OMAP_ALIGNED;
230 struct crypto_queue queue;
231 struct ahash_request *req;
233 const struct omap_sham_pdata *pdata;
236 struct omap_sham_drv {
237 struct list_head dev_list;
242 static struct omap_sham_drv sham = {
243 .dev_list = LIST_HEAD_INIT(sham.dev_list),
244 .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
247 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
249 return __raw_readl(dd->io_base + offset);
252 static inline void omap_sham_write(struct omap_sham_dev *dd,
253 u32 offset, u32 value)
255 __raw_writel(value, dd->io_base + offset);
258 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
263 val = omap_sham_read(dd, address);
266 omap_sham_write(dd, address, val);
269 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
271 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
273 while (!(omap_sham_read(dd, offset) & bit)) {
274 if (time_is_before_jiffies(timeout))
281 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
283 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
284 struct omap_sham_dev *dd = ctx->dd;
285 u32 *hash = (u32 *)ctx->digest;
288 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
290 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
292 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
296 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
298 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
299 struct omap_sham_dev *dd = ctx->dd;
302 if (ctx->flags & BIT(FLAGS_HMAC)) {
303 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
304 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
305 struct omap_sham_hmac_ctx *bctx = tctx->base;
306 u32 *opad = (u32 *)bctx->opad;
308 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
310 opad[i] = omap_sham_read(dd,
311 SHA_REG_ODIGEST(dd, i));
313 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
318 omap_sham_copy_hash_omap2(req, out);
321 static void omap_sham_copy_ready_hash(struct ahash_request *req)
323 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
324 u32 *in = (u32 *)ctx->digest;
325 u32 *hash = (u32 *)req->result;
326 int i, d, big_endian = 0;
331 switch (ctx->flags & FLAGS_MODE_MASK) {
333 d = MD5_DIGEST_SIZE / sizeof(u32);
335 case FLAGS_MODE_SHA1:
336 /* OMAP2 SHA1 is big endian */
337 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
339 d = SHA1_DIGEST_SIZE / sizeof(u32);
341 case FLAGS_MODE_SHA224:
342 d = SHA224_DIGEST_SIZE / sizeof(u32);
344 case FLAGS_MODE_SHA256:
345 d = SHA256_DIGEST_SIZE / sizeof(u32);
347 case FLAGS_MODE_SHA384:
348 d = SHA384_DIGEST_SIZE / sizeof(u32);
350 case FLAGS_MODE_SHA512:
351 d = SHA512_DIGEST_SIZE / sizeof(u32);
358 for (i = 0; i < d; i++)
359 hash[i] = be32_to_cpu(in[i]);
361 for (i = 0; i < d; i++)
362 hash[i] = le32_to_cpu(in[i]);
365 static int omap_sham_hw_init(struct omap_sham_dev *dd)
369 err = pm_runtime_get_sync(dd->dev);
371 dev_err(dd->dev, "failed to get sync: %d\n", err);
375 if (!test_bit(FLAGS_INIT, &dd->flags)) {
376 set_bit(FLAGS_INIT, &dd->flags);
383 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
386 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
387 u32 val = length << 5, mask;
389 if (likely(ctx->digcnt))
390 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
392 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
393 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
394 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
396 * Setting ALGO_CONST only for the first iteration
397 * and CLOSE_HASH only for the last one.
399 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
400 val |= SHA_REG_CTRL_ALGO;
402 val |= SHA_REG_CTRL_ALGO_CONST;
404 val |= SHA_REG_CTRL_CLOSE_HASH;
406 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
407 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
409 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
412 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
416 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
418 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
421 static int get_block_size(struct omap_sham_reqctx *ctx)
425 switch (ctx->flags & FLAGS_MODE_MASK) {
427 case FLAGS_MODE_SHA1:
430 case FLAGS_MODE_SHA224:
431 case FLAGS_MODE_SHA256:
432 d = SHA256_BLOCK_SIZE;
434 case FLAGS_MODE_SHA384:
435 case FLAGS_MODE_SHA512:
436 d = SHA512_BLOCK_SIZE;
445 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
446 u32 *value, int count)
448 for (; count--; value++, offset += 4)
449 omap_sham_write(dd, offset, *value);
452 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
455 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
458 if (likely(ctx->digcnt))
459 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
462 * Setting ALGO_CONST only for the first iteration and
463 * CLOSE_HASH only for the last one. Note that flags mode bits
464 * correspond to algorithm encoding in mode register.
466 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
468 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
469 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
470 struct omap_sham_hmac_ctx *bctx = tctx->base;
473 val |= SHA_REG_MODE_ALGO_CONSTANT;
475 if (ctx->flags & BIT(FLAGS_HMAC)) {
476 bs = get_block_size(ctx);
477 nr_dr = bs / (2 * sizeof(u32));
478 val |= SHA_REG_MODE_HMAC_KEY_PROC;
479 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
480 (u32 *)bctx->ipad, nr_dr);
481 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
482 (u32 *)bctx->ipad + nr_dr, nr_dr);
488 val |= SHA_REG_MODE_CLOSE_HASH;
490 if (ctx->flags & BIT(FLAGS_HMAC))
491 val |= SHA_REG_MODE_HMAC_OUTER_HASH;
494 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
495 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
496 SHA_REG_MODE_HMAC_KEY_PROC;
498 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
499 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
500 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
501 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
503 (dma ? SHA_REG_MASK_DMA_EN : 0),
504 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
507 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
509 omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
512 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
514 return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
515 SHA_REG_IRQSTATUS_INPUT_RDY);
518 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
521 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
522 int count, len32, bs32, offset = 0;
525 struct sg_mapping_iter mi;
527 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
528 ctx->digcnt, length, final);
530 dd->pdata->write_ctrl(dd, length, final, 0);
531 dd->pdata->trigger(dd, length);
533 /* should be non-zero before next lines to disable clocks later */
534 ctx->digcnt += length;
535 ctx->total -= length;
538 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
540 set_bit(FLAGS_CPU, &dd->flags);
542 len32 = DIV_ROUND_UP(length, sizeof(u32));
543 bs32 = get_block_size(ctx) / sizeof(u32);
545 sg_miter_start(&mi, ctx->sg, ctx->sg_len,
546 SG_MITER_FROM_SG | SG_MITER_ATOMIC);
551 if (dd->pdata->poll_irq(dd))
554 for (count = 0; count < min(len32, bs32); count++, offset++) {
559 pr_err("sg miter failure.\n");
565 omap_sham_write(dd, SHA_REG_DIN(dd, count),
569 len32 -= min(len32, bs32);
577 static void omap_sham_dma_callback(void *param)
579 struct omap_sham_dev *dd = param;
581 set_bit(FLAGS_DMA_READY, &dd->flags);
582 tasklet_schedule(&dd->done_task);
585 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
588 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
589 struct dma_async_tx_descriptor *tx;
590 struct dma_slave_config cfg;
593 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
594 ctx->digcnt, length, final);
596 if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
597 dev_err(dd->dev, "dma_map_sg error\n");
601 memset(&cfg, 0, sizeof(cfg));
603 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
604 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
605 cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
607 ret = dmaengine_slave_config(dd->dma_lch, &cfg);
609 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
613 tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
615 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
618 dev_err(dd->dev, "prep_slave_sg failed\n");
622 tx->callback = omap_sham_dma_callback;
623 tx->callback_param = dd;
625 dd->pdata->write_ctrl(dd, length, final, 1);
627 ctx->digcnt += length;
628 ctx->total -= length;
631 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
633 set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
635 dmaengine_submit(tx);
636 dma_async_issue_pending(dd->dma_lch);
638 dd->pdata->trigger(dd, length);
643 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
644 struct scatterlist *sg, int bs, int new_len)
646 int n = sg_nents(sg);
647 struct scatterlist *tmp;
648 int offset = ctx->offset;
653 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
657 sg_init_table(ctx->sg, n);
664 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
669 while (sg && new_len) {
670 int len = sg->length - offset;
673 offset -= sg->length;
683 sg_set_page(tmp, sg_page(sg), len, sg->offset);
693 set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
700 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
701 struct scatterlist *sg, int bs, int new_len)
707 len = new_len + ctx->bufcnt;
709 pages = get_order(ctx->total);
711 buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
713 pr_err("Couldn't allocate pages for unaligned cases.\n");
718 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
720 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
721 ctx->total - ctx->bufcnt, 0);
722 sg_init_table(ctx->sgl, 1);
723 sg_set_buf(ctx->sgl, buf, len);
725 set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
733 static int omap_sham_align_sgs(struct scatterlist *sg,
734 int nbytes, int bs, bool final,
735 struct omap_sham_reqctx *rctx)
740 struct scatterlist *sg_tmp = sg;
742 int offset = rctx->offset;
744 if (!sg || !sg->length || !nbytes)
753 new_len = DIV_ROUND_UP(new_len, bs) * bs;
755 new_len = (new_len - 1) / bs * bs;
757 if (nbytes != new_len)
760 while (nbytes > 0 && sg_tmp) {
763 if (offset < sg_tmp->length) {
764 if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
769 if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
776 offset -= sg_tmp->length;
782 nbytes -= sg_tmp->length;
785 sg_tmp = sg_next(sg_tmp);
794 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
796 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
804 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
806 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
810 bool final = rctx->flags & BIT(FLAGS_FINUP);
811 int xmit_len, hash_later;
816 bs = get_block_size(rctx);
819 nbytes = req->nbytes;
823 rctx->total = nbytes + rctx->bufcnt;
828 if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
829 int len = bs - rctx->bufcnt % bs;
833 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
841 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
843 ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
847 xmit_len = rctx->total;
849 if (!IS_ALIGNED(xmit_len, bs)) {
851 xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs;
853 xmit_len = xmit_len / bs * bs;
858 hash_later = rctx->total - xmit_len;
862 if (rctx->bufcnt && nbytes) {
863 /* have data from previous operation and current */
864 sg_init_table(rctx->sgl, 2);
865 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
867 sg_chain(rctx->sgl, 2, req->src);
869 rctx->sg = rctx->sgl;
872 } else if (rctx->bufcnt) {
873 /* have buffered data only */
874 sg_init_table(rctx->sgl, 1);
875 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len);
877 rctx->sg = rctx->sgl;
885 if (hash_later > req->nbytes) {
886 memcpy(rctx->buffer, rctx->buffer + xmit_len,
887 hash_later - req->nbytes);
888 offset = hash_later - req->nbytes;
892 scatterwalk_map_and_copy(rctx->buffer + offset,
894 offset + req->nbytes -
895 hash_later, hash_later, 0);
898 rctx->bufcnt = hash_later;
904 rctx->total = xmit_len;
909 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
911 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
913 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
915 clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
920 struct omap_sham_dev *omap_sham_find_dev(struct omap_sham_reqctx *ctx)
922 struct omap_sham_dev *dd;
927 spin_lock_bh(&sham.lock);
928 dd = list_first_entry(&sham.dev_list, struct omap_sham_dev, list);
929 list_move_tail(&dd->list, &sham.dev_list);
931 spin_unlock_bh(&sham.lock);
936 static int omap_sham_init(struct ahash_request *req)
938 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
939 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
940 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
941 struct omap_sham_dev *dd;
946 dd = omap_sham_find_dev(ctx);
952 dev_dbg(dd->dev, "init: digest size: %d\n",
953 crypto_ahash_digestsize(tfm));
955 switch (crypto_ahash_digestsize(tfm)) {
956 case MD5_DIGEST_SIZE:
957 ctx->flags |= FLAGS_MODE_MD5;
958 bs = SHA1_BLOCK_SIZE;
960 case SHA1_DIGEST_SIZE:
961 ctx->flags |= FLAGS_MODE_SHA1;
962 bs = SHA1_BLOCK_SIZE;
964 case SHA224_DIGEST_SIZE:
965 ctx->flags |= FLAGS_MODE_SHA224;
966 bs = SHA224_BLOCK_SIZE;
968 case SHA256_DIGEST_SIZE:
969 ctx->flags |= FLAGS_MODE_SHA256;
970 bs = SHA256_BLOCK_SIZE;
972 case SHA384_DIGEST_SIZE:
973 ctx->flags |= FLAGS_MODE_SHA384;
974 bs = SHA384_BLOCK_SIZE;
976 case SHA512_DIGEST_SIZE:
977 ctx->flags |= FLAGS_MODE_SHA512;
978 bs = SHA512_BLOCK_SIZE;
986 ctx->buflen = BUFLEN;
988 if (tctx->flags & BIT(FLAGS_HMAC)) {
989 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
990 struct omap_sham_hmac_ctx *bctx = tctx->base;
992 memcpy(ctx->buffer, bctx->ipad, bs);
996 ctx->flags |= BIT(FLAGS_HMAC);
1003 static int omap_sham_update_req(struct omap_sham_dev *dd)
1005 struct ahash_request *req = dd->req;
1006 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1008 bool final = ctx->flags & BIT(FLAGS_FINUP);
1010 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
1011 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
1013 if (ctx->total < get_block_size(ctx) ||
1014 ctx->total < OMAP_SHA_DMA_THRESHOLD)
1015 ctx->flags |= BIT(FLAGS_CPU);
1017 if (ctx->flags & BIT(FLAGS_CPU))
1018 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1020 err = omap_sham_xmit_dma(dd, ctx->total, final);
1022 /* wait for dma completion before can take more data */
1023 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1028 static int omap_sham_final_req(struct omap_sham_dev *dd)
1030 struct ahash_request *req = dd->req;
1031 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1032 int err = 0, use_dma = 1;
1034 if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1036 * faster to handle last block with cpu or
1037 * use cpu when dma is not present.
1042 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1044 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1048 dev_dbg(dd->dev, "final_req: err: %d\n", err);
1053 static int omap_sham_finish_hmac(struct ahash_request *req)
1055 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1056 struct omap_sham_hmac_ctx *bctx = tctx->base;
1057 int bs = crypto_shash_blocksize(bctx->shash);
1058 int ds = crypto_shash_digestsize(bctx->shash);
1059 SHASH_DESC_ON_STACK(shash, bctx->shash);
1061 shash->tfm = bctx->shash;
1062 shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
1064 return crypto_shash_init(shash) ?:
1065 crypto_shash_update(shash, bctx->opad, bs) ?:
1066 crypto_shash_finup(shash, req->result, ds, req->result);
1069 static int omap_sham_finish(struct ahash_request *req)
1071 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1072 struct omap_sham_dev *dd = ctx->dd;
1076 omap_sham_copy_ready_hash(req);
1077 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1078 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1079 err = omap_sham_finish_hmac(req);
1082 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1087 static void omap_sham_finish_req(struct ahash_request *req, int err)
1089 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1090 struct omap_sham_dev *dd = ctx->dd;
1092 if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1093 free_pages((unsigned long)sg_virt(ctx->sg),
1094 get_order(ctx->sg->length + ctx->bufcnt));
1096 if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1101 dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1104 dd->pdata->copy_hash(req, 1);
1105 if (test_bit(FLAGS_FINAL, &dd->flags))
1106 err = omap_sham_finish(req);
1108 ctx->flags |= BIT(FLAGS_ERROR);
1111 /* atomic operation is not needed here */
1112 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1113 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1115 pm_runtime_mark_last_busy(dd->dev);
1116 pm_runtime_put_autosuspend(dd->dev);
1118 if (req->base.complete)
1119 req->base.complete(&req->base, err);
1122 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1123 struct ahash_request *req)
1125 struct crypto_async_request *async_req, *backlog;
1126 struct omap_sham_reqctx *ctx;
1127 unsigned long flags;
1128 int err = 0, ret = 0;
1131 spin_lock_irqsave(&dd->lock, flags);
1133 ret = ahash_enqueue_request(&dd->queue, req);
1134 if (test_bit(FLAGS_BUSY, &dd->flags)) {
1135 spin_unlock_irqrestore(&dd->lock, flags);
1138 backlog = crypto_get_backlog(&dd->queue);
1139 async_req = crypto_dequeue_request(&dd->queue);
1141 set_bit(FLAGS_BUSY, &dd->flags);
1142 spin_unlock_irqrestore(&dd->lock, flags);
1148 backlog->complete(backlog, -EINPROGRESS);
1150 req = ahash_request_cast(async_req);
1152 ctx = ahash_request_ctx(req);
1154 err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1155 if (err || !ctx->total)
1158 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1159 ctx->op, req->nbytes);
1161 err = omap_sham_hw_init(dd);
1166 /* request has changed - restore hash */
1167 dd->pdata->copy_hash(req, 0);
1169 if (ctx->op == OP_UPDATE) {
1170 err = omap_sham_update_req(dd);
1171 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1172 /* no final() after finup() */
1173 err = omap_sham_final_req(dd);
1174 } else if (ctx->op == OP_FINAL) {
1175 err = omap_sham_final_req(dd);
1178 dev_dbg(dd->dev, "exit, err: %d\n", err);
1180 if (err != -EINPROGRESS) {
1181 /* done_task will not finish it, so do it here */
1182 omap_sham_finish_req(req, err);
1186 * Execute next request immediately if there is anything
1195 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1197 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1198 struct omap_sham_dev *dd = ctx->dd;
1202 return omap_sham_handle_queue(dd, req);
1205 static int omap_sham_update(struct ahash_request *req)
1207 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1208 struct omap_sham_dev *dd = omap_sham_find_dev(ctx);
1213 if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1214 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1216 ctx->bufcnt += req->nbytes;
1220 if (dd->polling_mode)
1221 ctx->flags |= BIT(FLAGS_CPU);
1223 return omap_sham_enqueue(req, OP_UPDATE);
1226 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1227 const u8 *data, unsigned int len, u8 *out)
1229 SHASH_DESC_ON_STACK(shash, tfm);
1232 shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1234 return crypto_shash_digest(shash, data, len, out);
1237 static int omap_sham_final_shash(struct ahash_request *req)
1239 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1240 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1244 * If we are running HMAC on limited hardware support, skip
1245 * the ipad in the beginning of the buffer if we are going for
1246 * software fallback algorithm.
1248 if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1249 !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1250 offset = get_block_size(ctx);
1252 return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1253 ctx->buffer + offset,
1254 ctx->bufcnt - offset, req->result);
1257 static int omap_sham_final(struct ahash_request *req)
1259 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1261 ctx->flags |= BIT(FLAGS_FINUP);
1263 if (ctx->flags & BIT(FLAGS_ERROR))
1264 return 0; /* uncompleted hash is not needed */
1267 * OMAP HW accel works only with buffers >= 9.
1268 * HMAC is always >= 9 because ipad == block size.
1269 * If buffersize is less than DMA_THRESHOLD, we use fallback
1270 * SW encoding, as using DMA + HW in this case doesn't provide
1273 if (!ctx->digcnt && ctx->bufcnt < OMAP_SHA_DMA_THRESHOLD)
1274 return omap_sham_final_shash(req);
1275 else if (ctx->bufcnt)
1276 return omap_sham_enqueue(req, OP_FINAL);
1278 /* copy ready hash (+ finalize hmac) */
1279 return omap_sham_finish(req);
1282 static int omap_sham_finup(struct ahash_request *req)
1284 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1287 ctx->flags |= BIT(FLAGS_FINUP);
1289 err1 = omap_sham_update(req);
1290 if (err1 == -EINPROGRESS || err1 == -EBUSY)
1293 * final() has to be always called to cleanup resources
1294 * even if udpate() failed, except EINPROGRESS
1296 err2 = omap_sham_final(req);
1298 return err1 ?: err2;
1301 static int omap_sham_digest(struct ahash_request *req)
1303 return omap_sham_init(req) ?: omap_sham_finup(req);
1306 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1307 unsigned int keylen)
1309 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1310 struct omap_sham_hmac_ctx *bctx = tctx->base;
1311 int bs = crypto_shash_blocksize(bctx->shash);
1312 int ds = crypto_shash_digestsize(bctx->shash);
1315 err = crypto_shash_setkey(tctx->fallback, key, keylen);
1320 err = omap_sham_shash_digest(bctx->shash,
1321 crypto_shash_get_flags(bctx->shash),
1322 key, keylen, bctx->ipad);
1327 memcpy(bctx->ipad, key, keylen);
1330 memset(bctx->ipad + keylen, 0, bs - keylen);
1332 if (!test_bit(FLAGS_AUTO_XOR, &sham.flags)) {
1333 memcpy(bctx->opad, bctx->ipad, bs);
1335 for (i = 0; i < bs; i++) {
1336 bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1337 bctx->opad[i] ^= HMAC_OPAD_VALUE;
1344 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1346 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1347 const char *alg_name = crypto_tfm_alg_name(tfm);
1349 /* Allocate a fallback and abort if it failed. */
1350 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1351 CRYPTO_ALG_NEED_FALLBACK);
1352 if (IS_ERR(tctx->fallback)) {
1353 pr_err("omap-sham: fallback driver '%s' "
1354 "could not be loaded.\n", alg_name);
1355 return PTR_ERR(tctx->fallback);
1358 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1359 sizeof(struct omap_sham_reqctx) + BUFLEN);
1362 struct omap_sham_hmac_ctx *bctx = tctx->base;
1363 tctx->flags |= BIT(FLAGS_HMAC);
1364 bctx->shash = crypto_alloc_shash(alg_base, 0,
1365 CRYPTO_ALG_NEED_FALLBACK);
1366 if (IS_ERR(bctx->shash)) {
1367 pr_err("omap-sham: base driver '%s' "
1368 "could not be loaded.\n", alg_base);
1369 crypto_free_shash(tctx->fallback);
1370 return PTR_ERR(bctx->shash);
1378 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1380 return omap_sham_cra_init_alg(tfm, NULL);
1383 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1385 return omap_sham_cra_init_alg(tfm, "sha1");
1388 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1390 return omap_sham_cra_init_alg(tfm, "sha224");
1393 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1395 return omap_sham_cra_init_alg(tfm, "sha256");
1398 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1400 return omap_sham_cra_init_alg(tfm, "md5");
1403 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1405 return omap_sham_cra_init_alg(tfm, "sha384");
1408 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1410 return omap_sham_cra_init_alg(tfm, "sha512");
1413 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1415 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1417 crypto_free_shash(tctx->fallback);
1418 tctx->fallback = NULL;
1420 if (tctx->flags & BIT(FLAGS_HMAC)) {
1421 struct omap_sham_hmac_ctx *bctx = tctx->base;
1422 crypto_free_shash(bctx->shash);
1426 static int omap_sham_export(struct ahash_request *req, void *out)
1428 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1430 memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1435 static int omap_sham_import(struct ahash_request *req, const void *in)
1437 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1438 const struct omap_sham_reqctx *ctx_in = in;
1440 memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1445 static struct ahash_alg algs_sha1_md5[] = {
1447 .init = omap_sham_init,
1448 .update = omap_sham_update,
1449 .final = omap_sham_final,
1450 .finup = omap_sham_finup,
1451 .digest = omap_sham_digest,
1452 .halg.digestsize = SHA1_DIGEST_SIZE,
1455 .cra_driver_name = "omap-sha1",
1456 .cra_priority = 400,
1457 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1458 CRYPTO_ALG_KERN_DRIVER_ONLY |
1460 CRYPTO_ALG_NEED_FALLBACK,
1461 .cra_blocksize = SHA1_BLOCK_SIZE,
1462 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1463 .cra_alignmask = OMAP_ALIGN_MASK,
1464 .cra_module = THIS_MODULE,
1465 .cra_init = omap_sham_cra_init,
1466 .cra_exit = omap_sham_cra_exit,
1470 .init = omap_sham_init,
1471 .update = omap_sham_update,
1472 .final = omap_sham_final,
1473 .finup = omap_sham_finup,
1474 .digest = omap_sham_digest,
1475 .halg.digestsize = MD5_DIGEST_SIZE,
1478 .cra_driver_name = "omap-md5",
1479 .cra_priority = 400,
1480 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1481 CRYPTO_ALG_KERN_DRIVER_ONLY |
1483 CRYPTO_ALG_NEED_FALLBACK,
1484 .cra_blocksize = SHA1_BLOCK_SIZE,
1485 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1486 .cra_alignmask = OMAP_ALIGN_MASK,
1487 .cra_module = THIS_MODULE,
1488 .cra_init = omap_sham_cra_init,
1489 .cra_exit = omap_sham_cra_exit,
1493 .init = omap_sham_init,
1494 .update = omap_sham_update,
1495 .final = omap_sham_final,
1496 .finup = omap_sham_finup,
1497 .digest = omap_sham_digest,
1498 .setkey = omap_sham_setkey,
1499 .halg.digestsize = SHA1_DIGEST_SIZE,
1501 .cra_name = "hmac(sha1)",
1502 .cra_driver_name = "omap-hmac-sha1",
1503 .cra_priority = 400,
1504 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1505 CRYPTO_ALG_KERN_DRIVER_ONLY |
1507 CRYPTO_ALG_NEED_FALLBACK,
1508 .cra_blocksize = SHA1_BLOCK_SIZE,
1509 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1510 sizeof(struct omap_sham_hmac_ctx),
1511 .cra_alignmask = OMAP_ALIGN_MASK,
1512 .cra_module = THIS_MODULE,
1513 .cra_init = omap_sham_cra_sha1_init,
1514 .cra_exit = omap_sham_cra_exit,
1518 .init = omap_sham_init,
1519 .update = omap_sham_update,
1520 .final = omap_sham_final,
1521 .finup = omap_sham_finup,
1522 .digest = omap_sham_digest,
1523 .setkey = omap_sham_setkey,
1524 .halg.digestsize = MD5_DIGEST_SIZE,
1526 .cra_name = "hmac(md5)",
1527 .cra_driver_name = "omap-hmac-md5",
1528 .cra_priority = 400,
1529 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1530 CRYPTO_ALG_KERN_DRIVER_ONLY |
1532 CRYPTO_ALG_NEED_FALLBACK,
1533 .cra_blocksize = SHA1_BLOCK_SIZE,
1534 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1535 sizeof(struct omap_sham_hmac_ctx),
1536 .cra_alignmask = OMAP_ALIGN_MASK,
1537 .cra_module = THIS_MODULE,
1538 .cra_init = omap_sham_cra_md5_init,
1539 .cra_exit = omap_sham_cra_exit,
1544 /* OMAP4 has some algs in addition to what OMAP2 has */
1545 static struct ahash_alg algs_sha224_sha256[] = {
1547 .init = omap_sham_init,
1548 .update = omap_sham_update,
1549 .final = omap_sham_final,
1550 .finup = omap_sham_finup,
1551 .digest = omap_sham_digest,
1552 .halg.digestsize = SHA224_DIGEST_SIZE,
1554 .cra_name = "sha224",
1555 .cra_driver_name = "omap-sha224",
1556 .cra_priority = 400,
1557 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1559 CRYPTO_ALG_NEED_FALLBACK,
1560 .cra_blocksize = SHA224_BLOCK_SIZE,
1561 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1562 .cra_alignmask = OMAP_ALIGN_MASK,
1563 .cra_module = THIS_MODULE,
1564 .cra_init = omap_sham_cra_init,
1565 .cra_exit = omap_sham_cra_exit,
1569 .init = omap_sham_init,
1570 .update = omap_sham_update,
1571 .final = omap_sham_final,
1572 .finup = omap_sham_finup,
1573 .digest = omap_sham_digest,
1574 .halg.digestsize = SHA256_DIGEST_SIZE,
1576 .cra_name = "sha256",
1577 .cra_driver_name = "omap-sha256",
1578 .cra_priority = 400,
1579 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1581 CRYPTO_ALG_NEED_FALLBACK,
1582 .cra_blocksize = SHA256_BLOCK_SIZE,
1583 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1584 .cra_alignmask = OMAP_ALIGN_MASK,
1585 .cra_module = THIS_MODULE,
1586 .cra_init = omap_sham_cra_init,
1587 .cra_exit = omap_sham_cra_exit,
1591 .init = omap_sham_init,
1592 .update = omap_sham_update,
1593 .final = omap_sham_final,
1594 .finup = omap_sham_finup,
1595 .digest = omap_sham_digest,
1596 .setkey = omap_sham_setkey,
1597 .halg.digestsize = SHA224_DIGEST_SIZE,
1599 .cra_name = "hmac(sha224)",
1600 .cra_driver_name = "omap-hmac-sha224",
1601 .cra_priority = 400,
1602 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1604 CRYPTO_ALG_NEED_FALLBACK,
1605 .cra_blocksize = SHA224_BLOCK_SIZE,
1606 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1607 sizeof(struct omap_sham_hmac_ctx),
1608 .cra_alignmask = OMAP_ALIGN_MASK,
1609 .cra_module = THIS_MODULE,
1610 .cra_init = omap_sham_cra_sha224_init,
1611 .cra_exit = omap_sham_cra_exit,
1615 .init = omap_sham_init,
1616 .update = omap_sham_update,
1617 .final = omap_sham_final,
1618 .finup = omap_sham_finup,
1619 .digest = omap_sham_digest,
1620 .setkey = omap_sham_setkey,
1621 .halg.digestsize = SHA256_DIGEST_SIZE,
1623 .cra_name = "hmac(sha256)",
1624 .cra_driver_name = "omap-hmac-sha256",
1625 .cra_priority = 400,
1626 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1628 CRYPTO_ALG_NEED_FALLBACK,
1629 .cra_blocksize = SHA256_BLOCK_SIZE,
1630 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1631 sizeof(struct omap_sham_hmac_ctx),
1632 .cra_alignmask = OMAP_ALIGN_MASK,
1633 .cra_module = THIS_MODULE,
1634 .cra_init = omap_sham_cra_sha256_init,
1635 .cra_exit = omap_sham_cra_exit,
1640 static struct ahash_alg algs_sha384_sha512[] = {
1642 .init = omap_sham_init,
1643 .update = omap_sham_update,
1644 .final = omap_sham_final,
1645 .finup = omap_sham_finup,
1646 .digest = omap_sham_digest,
1647 .halg.digestsize = SHA384_DIGEST_SIZE,
1649 .cra_name = "sha384",
1650 .cra_driver_name = "omap-sha384",
1651 .cra_priority = 400,
1652 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1654 CRYPTO_ALG_NEED_FALLBACK,
1655 .cra_blocksize = SHA384_BLOCK_SIZE,
1656 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1657 .cra_alignmask = OMAP_ALIGN_MASK,
1658 .cra_module = THIS_MODULE,
1659 .cra_init = omap_sham_cra_init,
1660 .cra_exit = omap_sham_cra_exit,
1664 .init = omap_sham_init,
1665 .update = omap_sham_update,
1666 .final = omap_sham_final,
1667 .finup = omap_sham_finup,
1668 .digest = omap_sham_digest,
1669 .halg.digestsize = SHA512_DIGEST_SIZE,
1671 .cra_name = "sha512",
1672 .cra_driver_name = "omap-sha512",
1673 .cra_priority = 400,
1674 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1676 CRYPTO_ALG_NEED_FALLBACK,
1677 .cra_blocksize = SHA512_BLOCK_SIZE,
1678 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1679 .cra_alignmask = OMAP_ALIGN_MASK,
1680 .cra_module = THIS_MODULE,
1681 .cra_init = omap_sham_cra_init,
1682 .cra_exit = omap_sham_cra_exit,
1686 .init = omap_sham_init,
1687 .update = omap_sham_update,
1688 .final = omap_sham_final,
1689 .finup = omap_sham_finup,
1690 .digest = omap_sham_digest,
1691 .setkey = omap_sham_setkey,
1692 .halg.digestsize = SHA384_DIGEST_SIZE,
1694 .cra_name = "hmac(sha384)",
1695 .cra_driver_name = "omap-hmac-sha384",
1696 .cra_priority = 400,
1697 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1699 CRYPTO_ALG_NEED_FALLBACK,
1700 .cra_blocksize = SHA384_BLOCK_SIZE,
1701 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1702 sizeof(struct omap_sham_hmac_ctx),
1703 .cra_alignmask = OMAP_ALIGN_MASK,
1704 .cra_module = THIS_MODULE,
1705 .cra_init = omap_sham_cra_sha384_init,
1706 .cra_exit = omap_sham_cra_exit,
1710 .init = omap_sham_init,
1711 .update = omap_sham_update,
1712 .final = omap_sham_final,
1713 .finup = omap_sham_finup,
1714 .digest = omap_sham_digest,
1715 .setkey = omap_sham_setkey,
1716 .halg.digestsize = SHA512_DIGEST_SIZE,
1718 .cra_name = "hmac(sha512)",
1719 .cra_driver_name = "omap-hmac-sha512",
1720 .cra_priority = 400,
1721 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1723 CRYPTO_ALG_NEED_FALLBACK,
1724 .cra_blocksize = SHA512_BLOCK_SIZE,
1725 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1726 sizeof(struct omap_sham_hmac_ctx),
1727 .cra_alignmask = OMAP_ALIGN_MASK,
1728 .cra_module = THIS_MODULE,
1729 .cra_init = omap_sham_cra_sha512_init,
1730 .cra_exit = omap_sham_cra_exit,
1735 static void omap_sham_done_task(unsigned long data)
1737 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1740 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1741 omap_sham_handle_queue(dd, NULL);
1745 if (test_bit(FLAGS_CPU, &dd->flags)) {
1746 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1748 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1749 if (test_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1750 omap_sham_update_dma_stop(dd);
1756 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1757 /* hash or semi-hash ready */
1758 clear_bit(FLAGS_DMA_READY, &dd->flags);
1766 dev_dbg(dd->dev, "update done: err: %d\n", err);
1767 /* finish curent request */
1768 omap_sham_finish_req(dd->req, err);
1770 /* If we are not busy, process next req */
1771 if (!test_bit(FLAGS_BUSY, &dd->flags))
1772 omap_sham_handle_queue(dd, NULL);
1775 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1777 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1778 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1780 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1781 tasklet_schedule(&dd->done_task);
1787 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1789 struct omap_sham_dev *dd = dev_id;
1791 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1792 /* final -> allow device to go to power-saving mode */
1793 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1795 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1796 SHA_REG_CTRL_OUTPUT_READY);
1797 omap_sham_read(dd, SHA_REG_CTRL);
1799 return omap_sham_irq_common(dd);
1802 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1804 struct omap_sham_dev *dd = dev_id;
1806 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1808 return omap_sham_irq_common(dd);
1811 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1813 .algs_list = algs_sha1_md5,
1814 .size = ARRAY_SIZE(algs_sha1_md5),
1818 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1819 .algs_info = omap_sham_algs_info_omap2,
1820 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1821 .flags = BIT(FLAGS_BE32_SHA1),
1822 .digest_size = SHA1_DIGEST_SIZE,
1823 .copy_hash = omap_sham_copy_hash_omap2,
1824 .write_ctrl = omap_sham_write_ctrl_omap2,
1825 .trigger = omap_sham_trigger_omap2,
1826 .poll_irq = omap_sham_poll_irq_omap2,
1827 .intr_hdlr = omap_sham_irq_omap2,
1828 .idigest_ofs = 0x00,
1833 .sysstatus_ofs = 0x64,
1841 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1843 .algs_list = algs_sha1_md5,
1844 .size = ARRAY_SIZE(algs_sha1_md5),
1847 .algs_list = algs_sha224_sha256,
1848 .size = ARRAY_SIZE(algs_sha224_sha256),
1852 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1853 .algs_info = omap_sham_algs_info_omap4,
1854 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1855 .flags = BIT(FLAGS_AUTO_XOR),
1856 .digest_size = SHA256_DIGEST_SIZE,
1857 .copy_hash = omap_sham_copy_hash_omap4,
1858 .write_ctrl = omap_sham_write_ctrl_omap4,
1859 .trigger = omap_sham_trigger_omap4,
1860 .poll_irq = omap_sham_poll_irq_omap4,
1861 .intr_hdlr = omap_sham_irq_omap4,
1862 .idigest_ofs = 0x020,
1865 .digcnt_ofs = 0x040,
1868 .sysstatus_ofs = 0x114,
1871 .major_mask = 0x0700,
1873 .minor_mask = 0x003f,
1877 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1879 .algs_list = algs_sha1_md5,
1880 .size = ARRAY_SIZE(algs_sha1_md5),
1883 .algs_list = algs_sha224_sha256,
1884 .size = ARRAY_SIZE(algs_sha224_sha256),
1887 .algs_list = algs_sha384_sha512,
1888 .size = ARRAY_SIZE(algs_sha384_sha512),
1892 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1893 .algs_info = omap_sham_algs_info_omap5,
1894 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1895 .flags = BIT(FLAGS_AUTO_XOR),
1896 .digest_size = SHA512_DIGEST_SIZE,
1897 .copy_hash = omap_sham_copy_hash_omap4,
1898 .write_ctrl = omap_sham_write_ctrl_omap4,
1899 .trigger = omap_sham_trigger_omap4,
1900 .poll_irq = omap_sham_poll_irq_omap4,
1901 .intr_hdlr = omap_sham_irq_omap4,
1902 .idigest_ofs = 0x240,
1903 .odigest_ofs = 0x200,
1905 .digcnt_ofs = 0x280,
1908 .sysstatus_ofs = 0x114,
1910 .length_ofs = 0x288,
1911 .major_mask = 0x0700,
1913 .minor_mask = 0x003f,
1917 static const struct of_device_id omap_sham_of_match[] = {
1919 .compatible = "ti,omap2-sham",
1920 .data = &omap_sham_pdata_omap2,
1923 .compatible = "ti,omap3-sham",
1924 .data = &omap_sham_pdata_omap2,
1927 .compatible = "ti,omap4-sham",
1928 .data = &omap_sham_pdata_omap4,
1931 .compatible = "ti,omap5-sham",
1932 .data = &omap_sham_pdata_omap5,
1936 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1938 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1939 struct device *dev, struct resource *res)
1941 struct device_node *node = dev->of_node;
1942 const struct of_device_id *match;
1945 match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
1947 dev_err(dev, "no compatible OF match\n");
1952 err = of_address_to_resource(node, 0, res);
1954 dev_err(dev, "can't translate OF node address\n");
1959 dd->irq = irq_of_parse_and_map(node, 0);
1961 dev_err(dev, "can't translate OF irq value\n");
1966 dd->pdata = match->data;
1972 static const struct of_device_id omap_sham_of_match[] = {
1976 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1977 struct device *dev, struct resource *res)
1983 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1984 struct platform_device *pdev, struct resource *res)
1986 struct device *dev = &pdev->dev;
1990 /* Get the base address */
1991 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1993 dev_err(dev, "no MEM resource info\n");
1997 memcpy(res, r, sizeof(*res));
2000 dd->irq = platform_get_irq(pdev, 0);
2002 dev_err(dev, "no IRQ resource info\n");
2007 /* Only OMAP2/3 can be non-DT */
2008 dd->pdata = &omap_sham_pdata_omap2;
2014 static int omap_sham_probe(struct platform_device *pdev)
2016 struct omap_sham_dev *dd;
2017 struct device *dev = &pdev->dev;
2018 struct resource res;
2019 dma_cap_mask_t mask;
2023 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2025 dev_err(dev, "unable to alloc data struct.\n");
2030 platform_set_drvdata(pdev, dd);
2032 INIT_LIST_HEAD(&dd->list);
2033 spin_lock_init(&dd->lock);
2034 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2035 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2037 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2038 omap_sham_get_res_pdev(dd, pdev, &res);
2042 dd->io_base = devm_ioremap_resource(dev, &res);
2043 if (IS_ERR(dd->io_base)) {
2044 err = PTR_ERR(dd->io_base);
2047 dd->phys_base = res.start;
2049 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2050 IRQF_TRIGGER_NONE, dev_name(dev), dd);
2052 dev_err(dev, "unable to request irq %d, err = %d\n",
2058 dma_cap_set(DMA_SLAVE, mask);
2060 dd->dma_lch = dma_request_chan(dev, "rx");
2061 if (IS_ERR(dd->dma_lch)) {
2062 err = PTR_ERR(dd->dma_lch);
2063 if (err == -EPROBE_DEFER)
2066 dd->polling_mode = 1;
2067 dev_dbg(dev, "using polling mode instead of dma\n");
2070 dd->flags |= dd->pdata->flags;
2071 sham.flags |= dd->pdata->flags;
2073 pm_runtime_use_autosuspend(dev);
2074 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2076 pm_runtime_enable(dev);
2077 pm_runtime_irq_safe(dev);
2079 err = pm_runtime_get_sync(dev);
2081 dev_err(dev, "failed to get sync: %d\n", err);
2085 rev = omap_sham_read(dd, SHA_REG_REV(dd));
2086 pm_runtime_put_sync(&pdev->dev);
2088 dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2089 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2090 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2092 spin_lock(&sham.lock);
2093 list_add_tail(&dd->list, &sham.dev_list);
2094 spin_unlock(&sham.lock);
2096 for (i = 0; i < dd->pdata->algs_info_size; i++) {
2097 if (dd->pdata->algs_info[i].registered)
2100 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2101 struct ahash_alg *alg;
2103 alg = &dd->pdata->algs_info[i].algs_list[j];
2104 alg->export = omap_sham_export;
2105 alg->import = omap_sham_import;
2106 alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2108 err = crypto_register_ahash(alg);
2112 dd->pdata->algs_info[i].registered++;
2119 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2120 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2121 crypto_unregister_ahash(
2122 &dd->pdata->algs_info[i].algs_list[j]);
2124 pm_runtime_disable(dev);
2125 if (!dd->polling_mode)
2126 dma_release_channel(dd->dma_lch);
2128 dev_err(dev, "initialization failed.\n");
2133 static int omap_sham_remove(struct platform_device *pdev)
2135 struct omap_sham_dev *dd;
2138 dd = platform_get_drvdata(pdev);
2141 spin_lock(&sham.lock);
2142 list_del(&dd->list);
2143 spin_unlock(&sham.lock);
2144 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2145 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
2146 crypto_unregister_ahash(
2147 &dd->pdata->algs_info[i].algs_list[j]);
2148 dd->pdata->algs_info[i].registered--;
2150 tasklet_kill(&dd->done_task);
2151 pm_runtime_disable(&pdev->dev);
2153 if (!dd->polling_mode)
2154 dma_release_channel(dd->dma_lch);
2159 #ifdef CONFIG_PM_SLEEP
2160 static int omap_sham_suspend(struct device *dev)
2162 pm_runtime_put_sync(dev);
2166 static int omap_sham_resume(struct device *dev)
2168 int err = pm_runtime_get_sync(dev);
2170 dev_err(dev, "failed to get sync: %d\n", err);
2177 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2179 static struct platform_driver omap_sham_driver = {
2180 .probe = omap_sham_probe,
2181 .remove = omap_sham_remove,
2183 .name = "omap-sham",
2184 .pm = &omap_sham_pm_ops,
2185 .of_match_table = omap_sham_of_match,
2189 module_platform_driver(omap_sham_driver);
2191 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2192 MODULE_LICENSE("GPL v2");
2193 MODULE_AUTHOR("Dmitry Kasatkin");
2194 MODULE_ALIAS("platform:omap-sham");