4 * Support for OMAP SHA1/MD5 HW acceleration.
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
8 * Copyright (c) 2011 Texas Instruments Incorporated
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
14 * Some ideas are from old omap-sha1-md5.c driver.
17 #define pr_fmt(fmt) "%s: " fmt, __func__
19 #include <linux/err.h>
20 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/irq.h>
28 #include <linux/platform_device.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/of_device.h>
35 #include <linux/of_address.h>
36 #include <linux/of_irq.h>
37 #include <linux/delay.h>
38 #include <linux/crypto.h>
39 #include <linux/cryptohash.h>
40 #include <crypto/scatterwalk.h>
41 #include <crypto/algapi.h>
42 #include <crypto/sha.h>
43 #include <crypto/hash.h>
44 #include <crypto/hmac.h>
45 #include <crypto/internal/hash.h>
47 #define MD5_DIGEST_SIZE 16
49 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04))
50 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04))
51 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs)
53 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04))
55 #define SHA_REG_CTRL 0x18
56 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
57 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
58 #define SHA_REG_CTRL_ALGO_CONST (1 << 3)
59 #define SHA_REG_CTRL_ALGO (1 << 2)
60 #define SHA_REG_CTRL_INPUT_READY (1 << 1)
61 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
63 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs)
65 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs)
66 #define SHA_REG_MASK_DMA_EN (1 << 3)
67 #define SHA_REG_MASK_IT_EN (1 << 2)
68 #define SHA_REG_MASK_SOFTRESET (1 << 1)
69 #define SHA_REG_AUTOIDLE (1 << 0)
71 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs)
72 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
74 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs)
75 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7)
76 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5)
77 #define SHA_REG_MODE_CLOSE_HASH (1 << 4)
78 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3)
80 #define SHA_REG_MODE_ALGO_MASK (7 << 0)
81 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1)
82 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1)
83 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1)
84 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1)
85 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0)
86 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0)
88 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs)
90 #define SHA_REG_IRQSTATUS 0x118
91 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3)
92 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
93 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1)
94 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0)
96 #define SHA_REG_IRQENA 0x11C
97 #define SHA_REG_IRQENA_CTX_RDY (1 << 3)
98 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2)
99 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1)
100 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0)
102 #define DEFAULT_TIMEOUT_INTERVAL HZ
104 #define DEFAULT_AUTOSUSPEND_DELAY 1000
106 /* mostly device flags */
108 #define FLAGS_FINAL 1
109 #define FLAGS_DMA_ACTIVE 2
110 #define FLAGS_OUTPUT_READY 3
113 #define FLAGS_DMA_READY 6
114 #define FLAGS_AUTO_XOR 7
115 #define FLAGS_BE32_SHA1 8
116 #define FLAGS_SGS_COPIED 9
117 #define FLAGS_SGS_ALLOCED 10
119 #define FLAGS_FINUP 16
121 #define FLAGS_MODE_SHIFT 18
122 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
123 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
124 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
125 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
126 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
127 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
128 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
130 #define FLAGS_HMAC 21
131 #define FLAGS_ERROR 22
136 #define OMAP_ALIGN_MASK (sizeof(u32)-1)
137 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
139 #define BUFLEN SHA512_BLOCK_SIZE
140 #define OMAP_SHA_DMA_THRESHOLD 256
142 struct omap_sham_dev;
144 struct omap_sham_reqctx {
145 struct omap_sham_dev *dd;
149 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
155 struct scatterlist *sg;
156 struct scatterlist sgl[2];
157 int offset; /* offset in current sg */
159 unsigned int total; /* total request */
161 u8 buffer[0] OMAP_ALIGNED;
164 struct omap_sham_hmac_ctx {
165 struct crypto_shash *shash;
166 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
167 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
170 struct omap_sham_ctx {
174 struct crypto_shash *fallback;
176 struct omap_sham_hmac_ctx base[0];
179 #define OMAP_SHAM_QUEUE_LENGTH 10
181 struct omap_sham_algs_info {
182 struct ahash_alg *algs_list;
184 unsigned int registered;
187 struct omap_sham_pdata {
188 struct omap_sham_algs_info *algs_info;
189 unsigned int algs_info_size;
193 void (*copy_hash)(struct ahash_request *req, int out);
194 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
196 void (*trigger)(struct omap_sham_dev *dd, size_t length);
197 int (*poll_irq)(struct omap_sham_dev *dd);
198 irqreturn_t (*intr_hdlr)(int irq, void *dev_id);
216 struct omap_sham_dev {
217 struct list_head list;
218 unsigned long phys_base;
220 void __iomem *io_base;
224 struct dma_chan *dma_lch;
225 struct tasklet_struct done_task;
227 u8 xmit_buf[BUFLEN] OMAP_ALIGNED;
231 struct crypto_queue queue;
232 struct ahash_request *req;
234 const struct omap_sham_pdata *pdata;
237 struct omap_sham_drv {
238 struct list_head dev_list;
243 static struct omap_sham_drv sham = {
244 .dev_list = LIST_HEAD_INIT(sham.dev_list),
245 .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
248 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
250 return __raw_readl(dd->io_base + offset);
253 static inline void omap_sham_write(struct omap_sham_dev *dd,
254 u32 offset, u32 value)
256 __raw_writel(value, dd->io_base + offset);
259 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
264 val = omap_sham_read(dd, address);
267 omap_sham_write(dd, address, val);
270 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
272 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
274 while (!(omap_sham_read(dd, offset) & bit)) {
275 if (time_is_before_jiffies(timeout))
282 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
284 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
285 struct omap_sham_dev *dd = ctx->dd;
286 u32 *hash = (u32 *)ctx->digest;
289 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
291 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
293 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
297 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
299 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
300 struct omap_sham_dev *dd = ctx->dd;
303 if (ctx->flags & BIT(FLAGS_HMAC)) {
304 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
305 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
306 struct omap_sham_hmac_ctx *bctx = tctx->base;
307 u32 *opad = (u32 *)bctx->opad;
309 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
311 opad[i] = omap_sham_read(dd,
312 SHA_REG_ODIGEST(dd, i));
314 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
319 omap_sham_copy_hash_omap2(req, out);
322 static void omap_sham_copy_ready_hash(struct ahash_request *req)
324 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
325 u32 *in = (u32 *)ctx->digest;
326 u32 *hash = (u32 *)req->result;
327 int i, d, big_endian = 0;
332 switch (ctx->flags & FLAGS_MODE_MASK) {
334 d = MD5_DIGEST_SIZE / sizeof(u32);
336 case FLAGS_MODE_SHA1:
337 /* OMAP2 SHA1 is big endian */
338 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
340 d = SHA1_DIGEST_SIZE / sizeof(u32);
342 case FLAGS_MODE_SHA224:
343 d = SHA224_DIGEST_SIZE / sizeof(u32);
345 case FLAGS_MODE_SHA256:
346 d = SHA256_DIGEST_SIZE / sizeof(u32);
348 case FLAGS_MODE_SHA384:
349 d = SHA384_DIGEST_SIZE / sizeof(u32);
351 case FLAGS_MODE_SHA512:
352 d = SHA512_DIGEST_SIZE / sizeof(u32);
359 for (i = 0; i < d; i++)
360 hash[i] = be32_to_cpu(in[i]);
362 for (i = 0; i < d; i++)
363 hash[i] = le32_to_cpu(in[i]);
366 static int omap_sham_hw_init(struct omap_sham_dev *dd)
370 err = pm_runtime_get_sync(dd->dev);
372 dev_err(dd->dev, "failed to get sync: %d\n", err);
376 if (!test_bit(FLAGS_INIT, &dd->flags)) {
377 set_bit(FLAGS_INIT, &dd->flags);
384 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
387 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
388 u32 val = length << 5, mask;
390 if (likely(ctx->digcnt))
391 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
393 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
394 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
395 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
397 * Setting ALGO_CONST only for the first iteration
398 * and CLOSE_HASH only for the last one.
400 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
401 val |= SHA_REG_CTRL_ALGO;
403 val |= SHA_REG_CTRL_ALGO_CONST;
405 val |= SHA_REG_CTRL_CLOSE_HASH;
407 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
408 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
410 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
413 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
417 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
419 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
422 static int get_block_size(struct omap_sham_reqctx *ctx)
426 switch (ctx->flags & FLAGS_MODE_MASK) {
428 case FLAGS_MODE_SHA1:
431 case FLAGS_MODE_SHA224:
432 case FLAGS_MODE_SHA256:
433 d = SHA256_BLOCK_SIZE;
435 case FLAGS_MODE_SHA384:
436 case FLAGS_MODE_SHA512:
437 d = SHA512_BLOCK_SIZE;
446 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
447 u32 *value, int count)
449 for (; count--; value++, offset += 4)
450 omap_sham_write(dd, offset, *value);
453 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
456 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
459 if (likely(ctx->digcnt))
460 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
463 * Setting ALGO_CONST only for the first iteration and
464 * CLOSE_HASH only for the last one. Note that flags mode bits
465 * correspond to algorithm encoding in mode register.
467 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
469 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
470 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
471 struct omap_sham_hmac_ctx *bctx = tctx->base;
474 val |= SHA_REG_MODE_ALGO_CONSTANT;
476 if (ctx->flags & BIT(FLAGS_HMAC)) {
477 bs = get_block_size(ctx);
478 nr_dr = bs / (2 * sizeof(u32));
479 val |= SHA_REG_MODE_HMAC_KEY_PROC;
480 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
481 (u32 *)bctx->ipad, nr_dr);
482 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
483 (u32 *)bctx->ipad + nr_dr, nr_dr);
489 val |= SHA_REG_MODE_CLOSE_HASH;
491 if (ctx->flags & BIT(FLAGS_HMAC))
492 val |= SHA_REG_MODE_HMAC_OUTER_HASH;
495 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
496 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
497 SHA_REG_MODE_HMAC_KEY_PROC;
499 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
500 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
501 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
502 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
504 (dma ? SHA_REG_MASK_DMA_EN : 0),
505 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
508 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
510 omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
513 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
515 return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
516 SHA_REG_IRQSTATUS_INPUT_RDY);
519 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
522 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
523 int count, len32, bs32, offset = 0;
526 struct sg_mapping_iter mi;
528 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
529 ctx->digcnt, length, final);
531 dd->pdata->write_ctrl(dd, length, final, 0);
532 dd->pdata->trigger(dd, length);
534 /* should be non-zero before next lines to disable clocks later */
535 ctx->digcnt += length;
536 ctx->total -= length;
539 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
541 set_bit(FLAGS_CPU, &dd->flags);
543 len32 = DIV_ROUND_UP(length, sizeof(u32));
544 bs32 = get_block_size(ctx) / sizeof(u32);
546 sg_miter_start(&mi, ctx->sg, ctx->sg_len,
547 SG_MITER_FROM_SG | SG_MITER_ATOMIC);
552 if (dd->pdata->poll_irq(dd))
555 for (count = 0; count < min(len32, bs32); count++, offset++) {
560 pr_err("sg miter failure.\n");
566 omap_sham_write(dd, SHA_REG_DIN(dd, count),
570 len32 -= min(len32, bs32);
578 static void omap_sham_dma_callback(void *param)
580 struct omap_sham_dev *dd = param;
582 set_bit(FLAGS_DMA_READY, &dd->flags);
583 tasklet_schedule(&dd->done_task);
586 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
589 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
590 struct dma_async_tx_descriptor *tx;
591 struct dma_slave_config cfg;
594 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
595 ctx->digcnt, length, final);
597 if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
598 dev_err(dd->dev, "dma_map_sg error\n");
602 memset(&cfg, 0, sizeof(cfg));
604 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
605 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
606 cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
608 ret = dmaengine_slave_config(dd->dma_lch, &cfg);
610 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
614 tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
616 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
619 dev_err(dd->dev, "prep_slave_sg failed\n");
623 tx->callback = omap_sham_dma_callback;
624 tx->callback_param = dd;
626 dd->pdata->write_ctrl(dd, length, final, 1);
628 ctx->digcnt += length;
629 ctx->total -= length;
632 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
634 set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
636 dmaengine_submit(tx);
637 dma_async_issue_pending(dd->dma_lch);
639 dd->pdata->trigger(dd, length);
644 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
645 struct scatterlist *sg, int bs, int new_len)
647 int n = sg_nents(sg);
648 struct scatterlist *tmp;
649 int offset = ctx->offset;
654 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
658 sg_init_table(ctx->sg, n);
665 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
670 while (sg && new_len) {
671 int len = sg->length - offset;
674 offset -= sg->length;
684 sg_set_page(tmp, sg_page(sg), len, sg->offset);
694 set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
701 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
702 struct scatterlist *sg, int bs, int new_len)
708 len = new_len + ctx->bufcnt;
710 pages = get_order(ctx->total);
712 buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
714 pr_err("Couldn't allocate pages for unaligned cases.\n");
719 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
721 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
722 ctx->total - ctx->bufcnt, 0);
723 sg_init_table(ctx->sgl, 1);
724 sg_set_buf(ctx->sgl, buf, len);
726 set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
734 static int omap_sham_align_sgs(struct scatterlist *sg,
735 int nbytes, int bs, bool final,
736 struct omap_sham_reqctx *rctx)
741 struct scatterlist *sg_tmp = sg;
743 int offset = rctx->offset;
745 if (!sg || !sg->length || !nbytes)
754 new_len = DIV_ROUND_UP(new_len, bs) * bs;
756 new_len = (new_len - 1) / bs * bs;
758 if (nbytes != new_len)
761 while (nbytes > 0 && sg_tmp) {
764 #ifdef CONFIG_ZONE_DMA
765 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) {
771 if (offset < sg_tmp->length) {
772 if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
777 if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
784 offset -= sg_tmp->length;
790 nbytes -= sg_tmp->length;
793 sg_tmp = sg_next(sg_tmp);
802 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
804 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
812 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
814 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
818 bool final = rctx->flags & BIT(FLAGS_FINUP);
819 int xmit_len, hash_later;
821 bs = get_block_size(rctx);
824 nbytes = req->nbytes;
828 rctx->total = nbytes + rctx->bufcnt;
833 if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
834 int len = bs - rctx->bufcnt % bs;
838 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
846 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
848 ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
852 xmit_len = rctx->total;
854 if (!IS_ALIGNED(xmit_len, bs)) {
856 xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs;
858 xmit_len = xmit_len / bs * bs;
863 hash_later = rctx->total - xmit_len;
867 if (rctx->bufcnt && nbytes) {
868 /* have data from previous operation and current */
869 sg_init_table(rctx->sgl, 2);
870 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
872 sg_chain(rctx->sgl, 2, req->src);
874 rctx->sg = rctx->sgl;
877 } else if (rctx->bufcnt) {
878 /* have buffered data only */
879 sg_init_table(rctx->sgl, 1);
880 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len);
882 rctx->sg = rctx->sgl;
890 if (hash_later > req->nbytes) {
891 memcpy(rctx->buffer, rctx->buffer + xmit_len,
892 hash_later - req->nbytes);
893 offset = hash_later - req->nbytes;
897 scatterwalk_map_and_copy(rctx->buffer + offset,
899 offset + req->nbytes -
900 hash_later, hash_later, 0);
903 rctx->bufcnt = hash_later;
909 rctx->total = xmit_len;
914 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
916 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
918 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
920 clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
925 struct omap_sham_dev *omap_sham_find_dev(struct omap_sham_reqctx *ctx)
927 struct omap_sham_dev *dd;
932 spin_lock_bh(&sham.lock);
933 dd = list_first_entry(&sham.dev_list, struct omap_sham_dev, list);
934 list_move_tail(&dd->list, &sham.dev_list);
936 spin_unlock_bh(&sham.lock);
941 static int omap_sham_init(struct ahash_request *req)
943 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
944 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
945 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
946 struct omap_sham_dev *dd;
951 dd = omap_sham_find_dev(ctx);
957 dev_dbg(dd->dev, "init: digest size: %d\n",
958 crypto_ahash_digestsize(tfm));
960 switch (crypto_ahash_digestsize(tfm)) {
961 case MD5_DIGEST_SIZE:
962 ctx->flags |= FLAGS_MODE_MD5;
963 bs = SHA1_BLOCK_SIZE;
965 case SHA1_DIGEST_SIZE:
966 ctx->flags |= FLAGS_MODE_SHA1;
967 bs = SHA1_BLOCK_SIZE;
969 case SHA224_DIGEST_SIZE:
970 ctx->flags |= FLAGS_MODE_SHA224;
971 bs = SHA224_BLOCK_SIZE;
973 case SHA256_DIGEST_SIZE:
974 ctx->flags |= FLAGS_MODE_SHA256;
975 bs = SHA256_BLOCK_SIZE;
977 case SHA384_DIGEST_SIZE:
978 ctx->flags |= FLAGS_MODE_SHA384;
979 bs = SHA384_BLOCK_SIZE;
981 case SHA512_DIGEST_SIZE:
982 ctx->flags |= FLAGS_MODE_SHA512;
983 bs = SHA512_BLOCK_SIZE;
991 ctx->buflen = BUFLEN;
993 if (tctx->flags & BIT(FLAGS_HMAC)) {
994 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
995 struct omap_sham_hmac_ctx *bctx = tctx->base;
997 memcpy(ctx->buffer, bctx->ipad, bs);
1001 ctx->flags |= BIT(FLAGS_HMAC);
1008 static int omap_sham_update_req(struct omap_sham_dev *dd)
1010 struct ahash_request *req = dd->req;
1011 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1013 bool final = ctx->flags & BIT(FLAGS_FINUP);
1015 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
1016 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
1018 if (ctx->total < get_block_size(ctx) ||
1019 ctx->total < dd->fallback_sz)
1020 ctx->flags |= BIT(FLAGS_CPU);
1022 if (ctx->flags & BIT(FLAGS_CPU))
1023 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1025 err = omap_sham_xmit_dma(dd, ctx->total, final);
1027 /* wait for dma completion before can take more data */
1028 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1033 static int omap_sham_final_req(struct omap_sham_dev *dd)
1035 struct ahash_request *req = dd->req;
1036 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1037 int err = 0, use_dma = 1;
1039 if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1041 * faster to handle last block with cpu or
1042 * use cpu when dma is not present.
1047 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1049 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1053 dev_dbg(dd->dev, "final_req: err: %d\n", err);
1058 static int omap_sham_finish_hmac(struct ahash_request *req)
1060 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1061 struct omap_sham_hmac_ctx *bctx = tctx->base;
1062 int bs = crypto_shash_blocksize(bctx->shash);
1063 int ds = crypto_shash_digestsize(bctx->shash);
1064 SHASH_DESC_ON_STACK(shash, bctx->shash);
1066 shash->tfm = bctx->shash;
1067 shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
1069 return crypto_shash_init(shash) ?:
1070 crypto_shash_update(shash, bctx->opad, bs) ?:
1071 crypto_shash_finup(shash, req->result, ds, req->result);
1074 static int omap_sham_finish(struct ahash_request *req)
1076 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1077 struct omap_sham_dev *dd = ctx->dd;
1081 omap_sham_copy_ready_hash(req);
1082 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1083 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1084 err = omap_sham_finish_hmac(req);
1087 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1092 static void omap_sham_finish_req(struct ahash_request *req, int err)
1094 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1095 struct omap_sham_dev *dd = ctx->dd;
1097 if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1098 free_pages((unsigned long)sg_virt(ctx->sg),
1099 get_order(ctx->sg->length + ctx->bufcnt));
1101 if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1106 dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1109 dd->pdata->copy_hash(req, 1);
1110 if (test_bit(FLAGS_FINAL, &dd->flags))
1111 err = omap_sham_finish(req);
1113 ctx->flags |= BIT(FLAGS_ERROR);
1116 /* atomic operation is not needed here */
1117 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1118 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1120 pm_runtime_mark_last_busy(dd->dev);
1121 pm_runtime_put_autosuspend(dd->dev);
1123 if (req->base.complete)
1124 req->base.complete(&req->base, err);
1127 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1128 struct ahash_request *req)
1130 struct crypto_async_request *async_req, *backlog;
1131 struct omap_sham_reqctx *ctx;
1132 unsigned long flags;
1133 int err = 0, ret = 0;
1136 spin_lock_irqsave(&dd->lock, flags);
1138 ret = ahash_enqueue_request(&dd->queue, req);
1139 if (test_bit(FLAGS_BUSY, &dd->flags)) {
1140 spin_unlock_irqrestore(&dd->lock, flags);
1143 backlog = crypto_get_backlog(&dd->queue);
1144 async_req = crypto_dequeue_request(&dd->queue);
1146 set_bit(FLAGS_BUSY, &dd->flags);
1147 spin_unlock_irqrestore(&dd->lock, flags);
1153 backlog->complete(backlog, -EINPROGRESS);
1155 req = ahash_request_cast(async_req);
1157 ctx = ahash_request_ctx(req);
1159 err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1160 if (err || !ctx->total)
1163 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1164 ctx->op, req->nbytes);
1166 err = omap_sham_hw_init(dd);
1171 /* request has changed - restore hash */
1172 dd->pdata->copy_hash(req, 0);
1174 if (ctx->op == OP_UPDATE) {
1175 err = omap_sham_update_req(dd);
1176 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1177 /* no final() after finup() */
1178 err = omap_sham_final_req(dd);
1179 } else if (ctx->op == OP_FINAL) {
1180 err = omap_sham_final_req(dd);
1183 dev_dbg(dd->dev, "exit, err: %d\n", err);
1185 if (err != -EINPROGRESS) {
1186 /* done_task will not finish it, so do it here */
1187 omap_sham_finish_req(req, err);
1191 * Execute next request immediately if there is anything
1200 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1202 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1203 struct omap_sham_dev *dd = ctx->dd;
1207 return omap_sham_handle_queue(dd, req);
1210 static int omap_sham_update(struct ahash_request *req)
1212 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1213 struct omap_sham_dev *dd = omap_sham_find_dev(ctx);
1218 if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1219 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1221 ctx->bufcnt += req->nbytes;
1225 if (dd->polling_mode)
1226 ctx->flags |= BIT(FLAGS_CPU);
1228 return omap_sham_enqueue(req, OP_UPDATE);
1231 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1232 const u8 *data, unsigned int len, u8 *out)
1234 SHASH_DESC_ON_STACK(shash, tfm);
1237 shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1239 return crypto_shash_digest(shash, data, len, out);
1242 static int omap_sham_final_shash(struct ahash_request *req)
1244 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1245 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1249 * If we are running HMAC on limited hardware support, skip
1250 * the ipad in the beginning of the buffer if we are going for
1251 * software fallback algorithm.
1253 if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1254 !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1255 offset = get_block_size(ctx);
1257 return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1258 ctx->buffer + offset,
1259 ctx->bufcnt - offset, req->result);
1262 static int omap_sham_final(struct ahash_request *req)
1264 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1266 ctx->flags |= BIT(FLAGS_FINUP);
1268 if (ctx->flags & BIT(FLAGS_ERROR))
1269 return 0; /* uncompleted hash is not needed */
1272 * OMAP HW accel works only with buffers >= 9.
1273 * HMAC is always >= 9 because ipad == block size.
1274 * If buffersize is less than fallback_sz, we use fallback
1275 * SW encoding, as using DMA + HW in this case doesn't provide
1278 if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz)
1279 return omap_sham_final_shash(req);
1280 else if (ctx->bufcnt)
1281 return omap_sham_enqueue(req, OP_FINAL);
1283 /* copy ready hash (+ finalize hmac) */
1284 return omap_sham_finish(req);
1287 static int omap_sham_finup(struct ahash_request *req)
1289 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1292 ctx->flags |= BIT(FLAGS_FINUP);
1294 err1 = omap_sham_update(req);
1295 if (err1 == -EINPROGRESS || err1 == -EBUSY)
1298 * final() has to be always called to cleanup resources
1299 * even if udpate() failed, except EINPROGRESS
1301 err2 = omap_sham_final(req);
1303 return err1 ?: err2;
1306 static int omap_sham_digest(struct ahash_request *req)
1308 return omap_sham_init(req) ?: omap_sham_finup(req);
1311 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1312 unsigned int keylen)
1314 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1315 struct omap_sham_hmac_ctx *bctx = tctx->base;
1316 int bs = crypto_shash_blocksize(bctx->shash);
1317 int ds = crypto_shash_digestsize(bctx->shash);
1320 err = crypto_shash_setkey(tctx->fallback, key, keylen);
1325 err = omap_sham_shash_digest(bctx->shash,
1326 crypto_shash_get_flags(bctx->shash),
1327 key, keylen, bctx->ipad);
1332 memcpy(bctx->ipad, key, keylen);
1335 memset(bctx->ipad + keylen, 0, bs - keylen);
1337 if (!test_bit(FLAGS_AUTO_XOR, &sham.flags)) {
1338 memcpy(bctx->opad, bctx->ipad, bs);
1340 for (i = 0; i < bs; i++) {
1341 bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1342 bctx->opad[i] ^= HMAC_OPAD_VALUE;
1349 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1351 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1352 const char *alg_name = crypto_tfm_alg_name(tfm);
1354 /* Allocate a fallback and abort if it failed. */
1355 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1356 CRYPTO_ALG_NEED_FALLBACK);
1357 if (IS_ERR(tctx->fallback)) {
1358 pr_err("omap-sham: fallback driver '%s' "
1359 "could not be loaded.\n", alg_name);
1360 return PTR_ERR(tctx->fallback);
1363 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1364 sizeof(struct omap_sham_reqctx) + BUFLEN);
1367 struct omap_sham_hmac_ctx *bctx = tctx->base;
1368 tctx->flags |= BIT(FLAGS_HMAC);
1369 bctx->shash = crypto_alloc_shash(alg_base, 0,
1370 CRYPTO_ALG_NEED_FALLBACK);
1371 if (IS_ERR(bctx->shash)) {
1372 pr_err("omap-sham: base driver '%s' "
1373 "could not be loaded.\n", alg_base);
1374 crypto_free_shash(tctx->fallback);
1375 return PTR_ERR(bctx->shash);
1383 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1385 return omap_sham_cra_init_alg(tfm, NULL);
1388 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1390 return omap_sham_cra_init_alg(tfm, "sha1");
1393 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1395 return omap_sham_cra_init_alg(tfm, "sha224");
1398 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1400 return omap_sham_cra_init_alg(tfm, "sha256");
1403 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1405 return omap_sham_cra_init_alg(tfm, "md5");
1408 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1410 return omap_sham_cra_init_alg(tfm, "sha384");
1413 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1415 return omap_sham_cra_init_alg(tfm, "sha512");
1418 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1420 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1422 crypto_free_shash(tctx->fallback);
1423 tctx->fallback = NULL;
1425 if (tctx->flags & BIT(FLAGS_HMAC)) {
1426 struct omap_sham_hmac_ctx *bctx = tctx->base;
1427 crypto_free_shash(bctx->shash);
1431 static int omap_sham_export(struct ahash_request *req, void *out)
1433 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1435 memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1440 static int omap_sham_import(struct ahash_request *req, const void *in)
1442 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1443 const struct omap_sham_reqctx *ctx_in = in;
1445 memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1450 static struct ahash_alg algs_sha1_md5[] = {
1452 .init = omap_sham_init,
1453 .update = omap_sham_update,
1454 .final = omap_sham_final,
1455 .finup = omap_sham_finup,
1456 .digest = omap_sham_digest,
1457 .halg.digestsize = SHA1_DIGEST_SIZE,
1460 .cra_driver_name = "omap-sha1",
1461 .cra_priority = 400,
1462 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1464 CRYPTO_ALG_NEED_FALLBACK,
1465 .cra_blocksize = SHA1_BLOCK_SIZE,
1466 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1467 .cra_alignmask = OMAP_ALIGN_MASK,
1468 .cra_module = THIS_MODULE,
1469 .cra_init = omap_sham_cra_init,
1470 .cra_exit = omap_sham_cra_exit,
1474 .init = omap_sham_init,
1475 .update = omap_sham_update,
1476 .final = omap_sham_final,
1477 .finup = omap_sham_finup,
1478 .digest = omap_sham_digest,
1479 .halg.digestsize = MD5_DIGEST_SIZE,
1482 .cra_driver_name = "omap-md5",
1483 .cra_priority = 400,
1484 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1486 CRYPTO_ALG_NEED_FALLBACK,
1487 .cra_blocksize = SHA1_BLOCK_SIZE,
1488 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1489 .cra_alignmask = OMAP_ALIGN_MASK,
1490 .cra_module = THIS_MODULE,
1491 .cra_init = omap_sham_cra_init,
1492 .cra_exit = omap_sham_cra_exit,
1496 .init = omap_sham_init,
1497 .update = omap_sham_update,
1498 .final = omap_sham_final,
1499 .finup = omap_sham_finup,
1500 .digest = omap_sham_digest,
1501 .setkey = omap_sham_setkey,
1502 .halg.digestsize = SHA1_DIGEST_SIZE,
1504 .cra_name = "hmac(sha1)",
1505 .cra_driver_name = "omap-hmac-sha1",
1506 .cra_priority = 400,
1507 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1509 CRYPTO_ALG_NEED_FALLBACK,
1510 .cra_blocksize = SHA1_BLOCK_SIZE,
1511 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1512 sizeof(struct omap_sham_hmac_ctx),
1513 .cra_alignmask = OMAP_ALIGN_MASK,
1514 .cra_module = THIS_MODULE,
1515 .cra_init = omap_sham_cra_sha1_init,
1516 .cra_exit = omap_sham_cra_exit,
1520 .init = omap_sham_init,
1521 .update = omap_sham_update,
1522 .final = omap_sham_final,
1523 .finup = omap_sham_finup,
1524 .digest = omap_sham_digest,
1525 .setkey = omap_sham_setkey,
1526 .halg.digestsize = MD5_DIGEST_SIZE,
1528 .cra_name = "hmac(md5)",
1529 .cra_driver_name = "omap-hmac-md5",
1530 .cra_priority = 400,
1531 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1533 CRYPTO_ALG_NEED_FALLBACK,
1534 .cra_blocksize = SHA1_BLOCK_SIZE,
1535 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1536 sizeof(struct omap_sham_hmac_ctx),
1537 .cra_alignmask = OMAP_ALIGN_MASK,
1538 .cra_module = THIS_MODULE,
1539 .cra_init = omap_sham_cra_md5_init,
1540 .cra_exit = omap_sham_cra_exit,
1545 /* OMAP4 has some algs in addition to what OMAP2 has */
1546 static struct ahash_alg algs_sha224_sha256[] = {
1548 .init = omap_sham_init,
1549 .update = omap_sham_update,
1550 .final = omap_sham_final,
1551 .finup = omap_sham_finup,
1552 .digest = omap_sham_digest,
1553 .halg.digestsize = SHA224_DIGEST_SIZE,
1555 .cra_name = "sha224",
1556 .cra_driver_name = "omap-sha224",
1557 .cra_priority = 400,
1558 .cra_flags = CRYPTO_ALG_ASYNC |
1559 CRYPTO_ALG_NEED_FALLBACK,
1560 .cra_blocksize = SHA224_BLOCK_SIZE,
1561 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1562 .cra_alignmask = OMAP_ALIGN_MASK,
1563 .cra_module = THIS_MODULE,
1564 .cra_init = omap_sham_cra_init,
1565 .cra_exit = omap_sham_cra_exit,
1569 .init = omap_sham_init,
1570 .update = omap_sham_update,
1571 .final = omap_sham_final,
1572 .finup = omap_sham_finup,
1573 .digest = omap_sham_digest,
1574 .halg.digestsize = SHA256_DIGEST_SIZE,
1576 .cra_name = "sha256",
1577 .cra_driver_name = "omap-sha256",
1578 .cra_priority = 400,
1579 .cra_flags = CRYPTO_ALG_ASYNC |
1580 CRYPTO_ALG_NEED_FALLBACK,
1581 .cra_blocksize = SHA256_BLOCK_SIZE,
1582 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1583 .cra_alignmask = OMAP_ALIGN_MASK,
1584 .cra_module = THIS_MODULE,
1585 .cra_init = omap_sham_cra_init,
1586 .cra_exit = omap_sham_cra_exit,
1590 .init = omap_sham_init,
1591 .update = omap_sham_update,
1592 .final = omap_sham_final,
1593 .finup = omap_sham_finup,
1594 .digest = omap_sham_digest,
1595 .setkey = omap_sham_setkey,
1596 .halg.digestsize = SHA224_DIGEST_SIZE,
1598 .cra_name = "hmac(sha224)",
1599 .cra_driver_name = "omap-hmac-sha224",
1600 .cra_priority = 400,
1601 .cra_flags = CRYPTO_ALG_ASYNC |
1602 CRYPTO_ALG_NEED_FALLBACK,
1603 .cra_blocksize = SHA224_BLOCK_SIZE,
1604 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1605 sizeof(struct omap_sham_hmac_ctx),
1606 .cra_alignmask = OMAP_ALIGN_MASK,
1607 .cra_module = THIS_MODULE,
1608 .cra_init = omap_sham_cra_sha224_init,
1609 .cra_exit = omap_sham_cra_exit,
1613 .init = omap_sham_init,
1614 .update = omap_sham_update,
1615 .final = omap_sham_final,
1616 .finup = omap_sham_finup,
1617 .digest = omap_sham_digest,
1618 .setkey = omap_sham_setkey,
1619 .halg.digestsize = SHA256_DIGEST_SIZE,
1621 .cra_name = "hmac(sha256)",
1622 .cra_driver_name = "omap-hmac-sha256",
1623 .cra_priority = 400,
1624 .cra_flags = CRYPTO_ALG_ASYNC |
1625 CRYPTO_ALG_NEED_FALLBACK,
1626 .cra_blocksize = SHA256_BLOCK_SIZE,
1627 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1628 sizeof(struct omap_sham_hmac_ctx),
1629 .cra_alignmask = OMAP_ALIGN_MASK,
1630 .cra_module = THIS_MODULE,
1631 .cra_init = omap_sham_cra_sha256_init,
1632 .cra_exit = omap_sham_cra_exit,
1637 static struct ahash_alg algs_sha384_sha512[] = {
1639 .init = omap_sham_init,
1640 .update = omap_sham_update,
1641 .final = omap_sham_final,
1642 .finup = omap_sham_finup,
1643 .digest = omap_sham_digest,
1644 .halg.digestsize = SHA384_DIGEST_SIZE,
1646 .cra_name = "sha384",
1647 .cra_driver_name = "omap-sha384",
1648 .cra_priority = 400,
1649 .cra_flags = CRYPTO_ALG_ASYNC |
1650 CRYPTO_ALG_NEED_FALLBACK,
1651 .cra_blocksize = SHA384_BLOCK_SIZE,
1652 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1653 .cra_alignmask = OMAP_ALIGN_MASK,
1654 .cra_module = THIS_MODULE,
1655 .cra_init = omap_sham_cra_init,
1656 .cra_exit = omap_sham_cra_exit,
1660 .init = omap_sham_init,
1661 .update = omap_sham_update,
1662 .final = omap_sham_final,
1663 .finup = omap_sham_finup,
1664 .digest = omap_sham_digest,
1665 .halg.digestsize = SHA512_DIGEST_SIZE,
1667 .cra_name = "sha512",
1668 .cra_driver_name = "omap-sha512",
1669 .cra_priority = 400,
1670 .cra_flags = CRYPTO_ALG_ASYNC |
1671 CRYPTO_ALG_NEED_FALLBACK,
1672 .cra_blocksize = SHA512_BLOCK_SIZE,
1673 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1674 .cra_alignmask = OMAP_ALIGN_MASK,
1675 .cra_module = THIS_MODULE,
1676 .cra_init = omap_sham_cra_init,
1677 .cra_exit = omap_sham_cra_exit,
1681 .init = omap_sham_init,
1682 .update = omap_sham_update,
1683 .final = omap_sham_final,
1684 .finup = omap_sham_finup,
1685 .digest = omap_sham_digest,
1686 .setkey = omap_sham_setkey,
1687 .halg.digestsize = SHA384_DIGEST_SIZE,
1689 .cra_name = "hmac(sha384)",
1690 .cra_driver_name = "omap-hmac-sha384",
1691 .cra_priority = 400,
1692 .cra_flags = CRYPTO_ALG_ASYNC |
1693 CRYPTO_ALG_NEED_FALLBACK,
1694 .cra_blocksize = SHA384_BLOCK_SIZE,
1695 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1696 sizeof(struct omap_sham_hmac_ctx),
1697 .cra_alignmask = OMAP_ALIGN_MASK,
1698 .cra_module = THIS_MODULE,
1699 .cra_init = omap_sham_cra_sha384_init,
1700 .cra_exit = omap_sham_cra_exit,
1704 .init = omap_sham_init,
1705 .update = omap_sham_update,
1706 .final = omap_sham_final,
1707 .finup = omap_sham_finup,
1708 .digest = omap_sham_digest,
1709 .setkey = omap_sham_setkey,
1710 .halg.digestsize = SHA512_DIGEST_SIZE,
1712 .cra_name = "hmac(sha512)",
1713 .cra_driver_name = "omap-hmac-sha512",
1714 .cra_priority = 400,
1715 .cra_flags = CRYPTO_ALG_ASYNC |
1716 CRYPTO_ALG_NEED_FALLBACK,
1717 .cra_blocksize = SHA512_BLOCK_SIZE,
1718 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1719 sizeof(struct omap_sham_hmac_ctx),
1720 .cra_alignmask = OMAP_ALIGN_MASK,
1721 .cra_module = THIS_MODULE,
1722 .cra_init = omap_sham_cra_sha512_init,
1723 .cra_exit = omap_sham_cra_exit,
1728 static void omap_sham_done_task(unsigned long data)
1730 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1733 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1734 omap_sham_handle_queue(dd, NULL);
1738 if (test_bit(FLAGS_CPU, &dd->flags)) {
1739 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1741 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1742 if (test_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1743 omap_sham_update_dma_stop(dd);
1749 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1750 /* hash or semi-hash ready */
1751 clear_bit(FLAGS_DMA_READY, &dd->flags);
1759 dev_dbg(dd->dev, "update done: err: %d\n", err);
1760 /* finish curent request */
1761 omap_sham_finish_req(dd->req, err);
1763 /* If we are not busy, process next req */
1764 if (!test_bit(FLAGS_BUSY, &dd->flags))
1765 omap_sham_handle_queue(dd, NULL);
1768 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1770 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1771 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1773 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1774 tasklet_schedule(&dd->done_task);
1780 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1782 struct omap_sham_dev *dd = dev_id;
1784 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1785 /* final -> allow device to go to power-saving mode */
1786 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1788 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1789 SHA_REG_CTRL_OUTPUT_READY);
1790 omap_sham_read(dd, SHA_REG_CTRL);
1792 return omap_sham_irq_common(dd);
1795 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1797 struct omap_sham_dev *dd = dev_id;
1799 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1801 return omap_sham_irq_common(dd);
1804 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1806 .algs_list = algs_sha1_md5,
1807 .size = ARRAY_SIZE(algs_sha1_md5),
1811 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1812 .algs_info = omap_sham_algs_info_omap2,
1813 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1814 .flags = BIT(FLAGS_BE32_SHA1),
1815 .digest_size = SHA1_DIGEST_SIZE,
1816 .copy_hash = omap_sham_copy_hash_omap2,
1817 .write_ctrl = omap_sham_write_ctrl_omap2,
1818 .trigger = omap_sham_trigger_omap2,
1819 .poll_irq = omap_sham_poll_irq_omap2,
1820 .intr_hdlr = omap_sham_irq_omap2,
1821 .idigest_ofs = 0x00,
1826 .sysstatus_ofs = 0x64,
1834 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1836 .algs_list = algs_sha1_md5,
1837 .size = ARRAY_SIZE(algs_sha1_md5),
1840 .algs_list = algs_sha224_sha256,
1841 .size = ARRAY_SIZE(algs_sha224_sha256),
1845 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1846 .algs_info = omap_sham_algs_info_omap4,
1847 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1848 .flags = BIT(FLAGS_AUTO_XOR),
1849 .digest_size = SHA256_DIGEST_SIZE,
1850 .copy_hash = omap_sham_copy_hash_omap4,
1851 .write_ctrl = omap_sham_write_ctrl_omap4,
1852 .trigger = omap_sham_trigger_omap4,
1853 .poll_irq = omap_sham_poll_irq_omap4,
1854 .intr_hdlr = omap_sham_irq_omap4,
1855 .idigest_ofs = 0x020,
1858 .digcnt_ofs = 0x040,
1861 .sysstatus_ofs = 0x114,
1864 .major_mask = 0x0700,
1866 .minor_mask = 0x003f,
1870 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1872 .algs_list = algs_sha1_md5,
1873 .size = ARRAY_SIZE(algs_sha1_md5),
1876 .algs_list = algs_sha224_sha256,
1877 .size = ARRAY_SIZE(algs_sha224_sha256),
1880 .algs_list = algs_sha384_sha512,
1881 .size = ARRAY_SIZE(algs_sha384_sha512),
1885 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1886 .algs_info = omap_sham_algs_info_omap5,
1887 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1888 .flags = BIT(FLAGS_AUTO_XOR),
1889 .digest_size = SHA512_DIGEST_SIZE,
1890 .copy_hash = omap_sham_copy_hash_omap4,
1891 .write_ctrl = omap_sham_write_ctrl_omap4,
1892 .trigger = omap_sham_trigger_omap4,
1893 .poll_irq = omap_sham_poll_irq_omap4,
1894 .intr_hdlr = omap_sham_irq_omap4,
1895 .idigest_ofs = 0x240,
1896 .odigest_ofs = 0x200,
1898 .digcnt_ofs = 0x280,
1901 .sysstatus_ofs = 0x114,
1903 .length_ofs = 0x288,
1904 .major_mask = 0x0700,
1906 .minor_mask = 0x003f,
1910 static const struct of_device_id omap_sham_of_match[] = {
1912 .compatible = "ti,omap2-sham",
1913 .data = &omap_sham_pdata_omap2,
1916 .compatible = "ti,omap3-sham",
1917 .data = &omap_sham_pdata_omap2,
1920 .compatible = "ti,omap4-sham",
1921 .data = &omap_sham_pdata_omap4,
1924 .compatible = "ti,omap5-sham",
1925 .data = &omap_sham_pdata_omap5,
1929 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1931 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1932 struct device *dev, struct resource *res)
1934 struct device_node *node = dev->of_node;
1937 dd->pdata = of_device_get_match_data(dev);
1939 dev_err(dev, "no compatible OF match\n");
1944 err = of_address_to_resource(node, 0, res);
1946 dev_err(dev, "can't translate OF node address\n");
1951 dd->irq = irq_of_parse_and_map(node, 0);
1953 dev_err(dev, "can't translate OF irq value\n");
1962 static const struct of_device_id omap_sham_of_match[] = {
1966 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1967 struct device *dev, struct resource *res)
1973 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1974 struct platform_device *pdev, struct resource *res)
1976 struct device *dev = &pdev->dev;
1980 /* Get the base address */
1981 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1983 dev_err(dev, "no MEM resource info\n");
1987 memcpy(res, r, sizeof(*res));
1990 dd->irq = platform_get_irq(pdev, 0);
1992 dev_err(dev, "no IRQ resource info\n");
1997 /* Only OMAP2/3 can be non-DT */
1998 dd->pdata = &omap_sham_pdata_omap2;
2004 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
2007 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2009 return sprintf(buf, "%d\n", dd->fallback_sz);
2012 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
2013 const char *buf, size_t size)
2015 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2019 status = kstrtol(buf, 0, &value);
2023 /* HW accelerator only works with buffers > 9 */
2025 dev_err(dev, "minimum fallback size 9\n");
2029 dd->fallback_sz = value;
2034 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
2037 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2039 return sprintf(buf, "%d\n", dd->queue.max_qlen);
2042 static ssize_t queue_len_store(struct device *dev,
2043 struct device_attribute *attr, const char *buf,
2046 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2049 unsigned long flags;
2051 status = kstrtol(buf, 0, &value);
2059 * Changing the queue size in fly is safe, if size becomes smaller
2060 * than current size, it will just not accept new entries until
2061 * it has shrank enough.
2063 spin_lock_irqsave(&dd->lock, flags);
2064 dd->queue.max_qlen = value;
2065 spin_unlock_irqrestore(&dd->lock, flags);
2070 static DEVICE_ATTR_RW(queue_len);
2071 static DEVICE_ATTR_RW(fallback);
2073 static struct attribute *omap_sham_attrs[] = {
2074 &dev_attr_queue_len.attr,
2075 &dev_attr_fallback.attr,
2079 static struct attribute_group omap_sham_attr_group = {
2080 .attrs = omap_sham_attrs,
2083 static int omap_sham_probe(struct platform_device *pdev)
2085 struct omap_sham_dev *dd;
2086 struct device *dev = &pdev->dev;
2087 struct resource res;
2088 dma_cap_mask_t mask;
2092 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2094 dev_err(dev, "unable to alloc data struct.\n");
2099 platform_set_drvdata(pdev, dd);
2101 INIT_LIST_HEAD(&dd->list);
2102 spin_lock_init(&dd->lock);
2103 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2104 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2106 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2107 omap_sham_get_res_pdev(dd, pdev, &res);
2111 dd->io_base = devm_ioremap_resource(dev, &res);
2112 if (IS_ERR(dd->io_base)) {
2113 err = PTR_ERR(dd->io_base);
2116 dd->phys_base = res.start;
2118 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2119 IRQF_TRIGGER_NONE, dev_name(dev), dd);
2121 dev_err(dev, "unable to request irq %d, err = %d\n",
2127 dma_cap_set(DMA_SLAVE, mask);
2129 dd->dma_lch = dma_request_chan(dev, "rx");
2130 if (IS_ERR(dd->dma_lch)) {
2131 err = PTR_ERR(dd->dma_lch);
2132 if (err == -EPROBE_DEFER)
2135 dd->polling_mode = 1;
2136 dev_dbg(dev, "using polling mode instead of dma\n");
2139 dd->flags |= dd->pdata->flags;
2140 sham.flags |= dd->pdata->flags;
2142 pm_runtime_use_autosuspend(dev);
2143 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2145 dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD;
2147 pm_runtime_enable(dev);
2148 pm_runtime_irq_safe(dev);
2150 err = pm_runtime_get_sync(dev);
2152 dev_err(dev, "failed to get sync: %d\n", err);
2156 rev = omap_sham_read(dd, SHA_REG_REV(dd));
2157 pm_runtime_put_sync(&pdev->dev);
2159 dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2160 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2161 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2163 spin_lock(&sham.lock);
2164 list_add_tail(&dd->list, &sham.dev_list);
2165 spin_unlock(&sham.lock);
2167 for (i = 0; i < dd->pdata->algs_info_size; i++) {
2168 if (dd->pdata->algs_info[i].registered)
2171 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2172 struct ahash_alg *alg;
2174 alg = &dd->pdata->algs_info[i].algs_list[j];
2175 alg->export = omap_sham_export;
2176 alg->import = omap_sham_import;
2177 alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2179 err = crypto_register_ahash(alg);
2183 dd->pdata->algs_info[i].registered++;
2187 err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group);
2189 dev_err(dev, "could not create sysfs device attrs\n");
2196 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2197 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2198 crypto_unregister_ahash(
2199 &dd->pdata->algs_info[i].algs_list[j]);
2201 pm_runtime_disable(dev);
2202 if (!dd->polling_mode)
2203 dma_release_channel(dd->dma_lch);
2205 dev_err(dev, "initialization failed.\n");
2210 static int omap_sham_remove(struct platform_device *pdev)
2212 struct omap_sham_dev *dd;
2215 dd = platform_get_drvdata(pdev);
2218 spin_lock(&sham.lock);
2219 list_del(&dd->list);
2220 spin_unlock(&sham.lock);
2221 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2222 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
2223 crypto_unregister_ahash(
2224 &dd->pdata->algs_info[i].algs_list[j]);
2225 dd->pdata->algs_info[i].registered--;
2227 tasklet_kill(&dd->done_task);
2228 pm_runtime_disable(&pdev->dev);
2230 if (!dd->polling_mode)
2231 dma_release_channel(dd->dma_lch);
2236 #ifdef CONFIG_PM_SLEEP
2237 static int omap_sham_suspend(struct device *dev)
2239 pm_runtime_put_sync(dev);
2243 static int omap_sham_resume(struct device *dev)
2245 int err = pm_runtime_get_sync(dev);
2247 dev_err(dev, "failed to get sync: %d\n", err);
2254 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2256 static struct platform_driver omap_sham_driver = {
2257 .probe = omap_sham_probe,
2258 .remove = omap_sham_remove,
2260 .name = "omap-sham",
2261 .pm = &omap_sham_pm_ops,
2262 .of_match_table = omap_sham_of_match,
2266 module_platform_driver(omap_sham_driver);
2268 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2269 MODULE_LICENSE("GPL v2");
2270 MODULE_AUTHOR("Dmitry Kasatkin");
2271 MODULE_ALIAS("platform:omap-sham");