drivers/crypto/omap-sham.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Cryptographic API.
   4  *
   5  * Support for OMAP SHA1/MD5 HW acceleration.
   6  *
   7  * Copyright (c) 2010 Nokia Corporation
   8  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   9  * Copyright (c) 2011 Texas Instruments Incorporated
  10  *
  11  * Some ideas are from old omap-sha1-md5.c driver.
  12  */
  13
  14 #define pr_fmt(fmt) "%s: " fmt, __func__
  15
  16 #include <linux/err.h>
  17 #include <linux/device.h>
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kernel.h>
  23 #include <linux/irq.h>
  24 #include <linux/io.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/scatterlist.h>
  27 #include <linux/dma-mapping.h>
  28 #include <linux/dmaengine.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_address.h>
  33 #include <linux/of_irq.h>
  34 #include <linux/delay.h>
  35 #include <linux/crypto.h>
  36 #include <linux/cryptohash.h>
  37 #include <crypto/scatterwalk.h>
  38 #include <crypto/algapi.h>
  39 #include <crypto/sha.h>
  40 #include <crypto/hash.h>
  41 #include <crypto/hmac.h>
  42 #include <crypto/internal/hash.h>
  43
  44 #define MD5_DIGEST_SIZE                 16
  45
  46 #define SHA_REG_IDIGEST(dd, x)          ((dd)->pdata->idigest_ofs + ((x)*0x04))
  47 #define SHA_REG_DIN(dd, x)              ((dd)->pdata->din_ofs + ((x) * 0x04))
  48 #define SHA_REG_DIGCNT(dd)              ((dd)->pdata->digcnt_ofs)
  49
  50 #define SHA_REG_ODIGEST(dd, x)          ((dd)->pdata->odigest_ofs + (x * 0x04))
  51
  52 #define SHA_REG_CTRL                    0x18
  53 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  54 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  55 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  56 #define SHA_REG_CTRL_ALGO               (1 << 2)
  57 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  58 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  59
  60 #define SHA_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  61
  62 #define SHA_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  63 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  64 #define SHA_REG_MASK_IT_EN              (1 << 2)
  65 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  66 #define SHA_REG_AUTOIDLE                (1 << 0)
  67
  68 #define SHA_REG_SYSSTATUS(dd)           ((dd)->pdata->sysstatus_ofs)
  69 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  70
  71 #define SHA_REG_MODE(dd)                ((dd)->pdata->mode_ofs)
  72 #define SHA_REG_MODE_HMAC_OUTER_HASH    (1 << 7)
  73 #define SHA_REG_MODE_HMAC_KEY_PROC      (1 << 5)
  74 #define SHA_REG_MODE_CLOSE_HASH         (1 << 4)
  75 #define SHA_REG_MODE_ALGO_CONSTANT      (1 << 3)
  76
  77 #define SHA_REG_MODE_ALGO_MASK          (7 << 0)
  78 #define SHA_REG_MODE_ALGO_MD5_128       (0 << 1)
  79 #define SHA_REG_MODE_ALGO_SHA1_160      (1 << 1)
  80 #define SHA_REG_MODE_ALGO_SHA2_224      (2 << 1)
  81 #define SHA_REG_MODE_ALGO_SHA2_256      (3 << 1)
  82 #define SHA_REG_MODE_ALGO_SHA2_384      (1 << 0)
  83 #define SHA_REG_MODE_ALGO_SHA2_512      (3 << 0)
  84
  85 #define SHA_REG_LENGTH(dd)              ((dd)->pdata->length_ofs)
  86
  87 #define SHA_REG_IRQSTATUS               0x118
  88 #define SHA_REG_IRQSTATUS_CTX_RDY       (1 << 3)
  89 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
  90 #define SHA_REG_IRQSTATUS_INPUT_RDY     (1 << 1)
  91 #define SHA_REG_IRQSTATUS_OUTPUT_RDY    (1 << 0)
  92
  93 #define SHA_REG_IRQENA                  0x11C
  94 #define SHA_REG_IRQENA_CTX_RDY          (1 << 3)
  95 #define SHA_REG_IRQENA_PARTHASH_RDY     (1 << 2)
  96 #define SHA_REG_IRQENA_INPUT_RDY        (1 << 1)
  97 #define SHA_REG_IRQENA_OUTPUT_RDY       (1 << 0)
  98
  99 #define DEFAULT_TIMEOUT_INTERVAL        HZ
 100
 101 #define DEFAULT_AUTOSUSPEND_DELAY       1000
 102
 103 /* mostly device flags */
 104 #define FLAGS_BUSY              0
 105 #define FLAGS_FINAL             1
 106 #define FLAGS_DMA_ACTIVE        2
 107 #define FLAGS_OUTPUT_READY      3
 108 #define FLAGS_INIT              4
 109 #define FLAGS_CPU               5
 110 #define FLAGS_DMA_READY         6
 111 #define FLAGS_AUTO_XOR          7
 112 #define FLAGS_BE32_SHA1         8
 113 #define FLAGS_SGS_COPIED        9
 114 #define FLAGS_SGS_ALLOCED       10
 115 /* context flags */
 116 #define FLAGS_FINUP             16
 117
 118 #define FLAGS_MODE_SHIFT        18
 119 #define FLAGS_MODE_MASK         (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
 120 #define FLAGS_MODE_MD5          (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
 121 #define FLAGS_MODE_SHA1         (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
 122 #define FLAGS_MODE_SHA224       (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
 123 #define FLAGS_MODE_SHA256       (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
 124 #define FLAGS_MODE_SHA384       (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
 125 #define FLAGS_MODE_SHA512       (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
 126
 127 #define FLAGS_HMAC              21
 128 #define FLAGS_ERROR             22
 129
 130 #define OP_UPDATE               1
 131 #define OP_FINAL                2
 132
 133 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
 134 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
 135
 136 #define BUFLEN                  SHA512_BLOCK_SIZE
 137 #define OMAP_SHA_DMA_THRESHOLD  256
 138
 139 struct omap_sham_dev;
 140
 141 struct omap_sham_reqctx {
 142         struct omap_sham_dev    *dd;
 143         unsigned long           flags;
 144         unsigned long           op;
 145
 146         u8                      digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
 147         size_t                  digcnt;
 148         size_t                  bufcnt;
 149         size_t                  buflen;
 150
 151         /* walk state */
 152         struct scatterlist      *sg;
 153         struct scatterlist      sgl[2];
 154         int                     offset; /* offset in current sg */
 155         int                     sg_len;
 156         unsigned int            total;  /* total request */
 157
 158         u8                      buffer[0] OMAP_ALIGNED;
 159 };
 160
 161 struct omap_sham_hmac_ctx {
 162         struct crypto_shash     *shash;
 163         u8                      ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 164         u8                      opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 165 };
 166
 167 struct omap_sham_ctx {
 168         unsigned long           flags;
 169
 170         /* fallback stuff */
 171         struct crypto_shash     *fallback;
 172
 173         struct omap_sham_hmac_ctx base[0];
 174 };
 175
 176 #define OMAP_SHAM_QUEUE_LENGTH  10
 177
 178 struct omap_sham_algs_info {
 179         struct ahash_alg        *algs_list;
 180         unsigned int            size;
 181         unsigned int            registered;
 182 };
 183
 184 struct omap_sham_pdata {
 185         struct omap_sham_algs_info      *algs_info;
 186         unsigned int    algs_info_size;
 187         unsigned long   flags;
 188         int             digest_size;
 189
 190         void            (*copy_hash)(struct ahash_request *req, int out);
 191         void            (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
 192                                       int final, int dma);
 193         void            (*trigger)(struct omap_sham_dev *dd, size_t length);
 194         int             (*poll_irq)(struct omap_sham_dev *dd);
 195         irqreturn_t     (*intr_hdlr)(int irq, void *dev_id);
 196
 197         u32             odigest_ofs;
 198         u32             idigest_ofs;
 199         u32             din_ofs;
 200         u32             digcnt_ofs;
 201         u32             rev_ofs;
 202         u32             mask_ofs;
 203         u32             sysstatus_ofs;
 204         u32             mode_ofs;
 205         u32             length_ofs;
 206
 207         u32             major_mask;
 208         u32             major_shift;
 209         u32             minor_mask;
 210         u32             minor_shift;
 211 };
 212
 213 struct omap_sham_dev {
 214         struct list_head        list;
 215         unsigned long           phys_base;
 216         struct device           *dev;
 217         void __iomem            *io_base;
 218         int                     irq;
 219         spinlock_t              lock;
 220         int                     err;
 221         struct dma_chan         *dma_lch;
 222         struct tasklet_struct   done_task;
 223         u8                      polling_mode;
 224         u8                      xmit_buf[BUFLEN] OMAP_ALIGNED;
 225
 226         unsigned long           flags;
 227         int                     fallback_sz;
 228         struct crypto_queue     queue;
 229         struct ahash_request    *req;
 230
 231         const struct omap_sham_pdata    *pdata;
 232 };
 233
 234 struct omap_sham_drv {
 235         struct list_head        dev_list;
 236         spinlock_t              lock;
 237         unsigned long           flags;
 238 };
 239
 240 static struct omap_sham_drv sham = {
 241         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 242         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 243 };
 244
 245 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 246 {
 247         return __raw_readl(dd->io_base + offset);
 248 }
 249
 250 static inline void omap_sham_write(struct omap_sham_dev *dd,
 251                                         u32 offset, u32 value)
 252 {
 253         __raw_writel(value, dd->io_base + offset);
 254 }
 255
 256 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 257                                         u32 value, u32 mask)
 258 {
 259         u32 val;
 260
 261         val = omap_sham_read(dd, address);
 262         val &= ~mask;
 263         val |= value;
 264         omap_sham_write(dd, address, val);
 265 }
 266
 267 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 268 {
 269         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 270
 271         while (!(omap_sham_read(dd, offset) & bit)) {
 272                 if (time_is_before_jiffies(timeout))
 273                         return -ETIMEDOUT;
 274         }
 275
 276         return 0;
 277 }
 278
 279 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
 280 {
 281         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 282         struct omap_sham_dev *dd = ctx->dd;
 283         u32 *hash = (u32 *)ctx->digest;
 284         int i;
 285
 286         for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 287                 if (out)
 288                         hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
 289                 else
 290                         omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
 291         }
 292 }
 293
 294 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
 295 {
 296         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 297         struct omap_sham_dev *dd = ctx->dd;
 298         int i;
 299
 300         if (ctx->flags & BIT(FLAGS_HMAC)) {
 301                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 302                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 303                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 304                 u32 *opad = (u32 *)bctx->opad;
 305
 306                 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 307                         if (out)
 308                                 opad[i] = omap_sham_read(dd,
 309                                                 SHA_REG_ODIGEST(dd, i));
 310                         else
 311                                 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
 312                                                 opad[i]);
 313                 }
 314         }
 315
 316         omap_sham_copy_hash_omap2(req, out);
 317 }
 318
 319 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 320 {
 321         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 322         u32 *in = (u32 *)ctx->digest;
 323         u32 *hash = (u32 *)req->result;
 324         int i, d, big_endian = 0;
 325
 326         if (!hash)
 327                 return;
 328
 329         switch (ctx->flags & FLAGS_MODE_MASK) {
 330         case FLAGS_MODE_MD5:
 331                 d = MD5_DIGEST_SIZE / sizeof(u32);
 332                 break;
 333         case FLAGS_MODE_SHA1:
 334                 /* OMAP2 SHA1 is big endian */
 335                 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
 336                         big_endian = 1;
 337                 d = SHA1_DIGEST_SIZE / sizeof(u32);
 338                 break;
 339         case FLAGS_MODE_SHA224:
 340                 d = SHA224_DIGEST_SIZE / sizeof(u32);
 341                 break;
 342         case FLAGS_MODE_SHA256:
 343                 d = SHA256_DIGEST_SIZE / sizeof(u32);
 344                 break;
 345         case FLAGS_MODE_SHA384:
 346                 d = SHA384_DIGEST_SIZE / sizeof(u32);
 347                 break;
 348         case FLAGS_MODE_SHA512:
 349                 d = SHA512_DIGEST_SIZE / sizeof(u32);
 350                 break;
 351         default:
 352                 d = 0;
 353         }
 354
 355         if (big_endian)
 356                 for (i = 0; i < d; i++)
 357                         hash[i] = be32_to_cpu(in[i]);
 358         else
 359                 for (i = 0; i < d; i++)
 360                         hash[i] = le32_to_cpu(in[i]);
 361 }
 362
 363 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 364 {
 365         int err;
 366
 367         err = pm_runtime_resume_and_get(dd->dev);
 368         if (err < 0) {
 369                 dev_err(dd->dev, "failed to get sync: %d\n", err);
 370                 return err;
 371         }
 372
 373         if (!test_bit(FLAGS_INIT, &dd->flags)) {
 374                 set_bit(FLAGS_INIT, &dd->flags);
 375                 dd->err = 0;
 376         }
 377
 378         return 0;
 379 }
 380
 381 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
 382                                  int final, int dma)
 383 {
 384         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 385         u32 val = length << 5, mask;
 386
 387         if (likely(ctx->digcnt))
 388                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 389
 390         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 391                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 392                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 393         /*
 394          * Setting ALGO_CONST only for the first iteration
 395          * and CLOSE_HASH only for the last one.
 396          */
 397         if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
 398                 val |= SHA_REG_CTRL_ALGO;
 399         if (!ctx->digcnt)
 400                 val |= SHA_REG_CTRL_ALGO_CONST;
 401         if (final)
 402                 val |= SHA_REG_CTRL_CLOSE_HASH;
 403
 404         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 405                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 406
 407         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 408 }
 409
 410 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
 411 {
 412 }
 413
 414 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
 415 {
 416         return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
 417 }
 418
 419 static int get_block_size(struct omap_sham_reqctx *ctx)
 420 {
 421         int d;
 422
 423         switch (ctx->flags & FLAGS_MODE_MASK) {
 424         case FLAGS_MODE_MD5:
 425         case FLAGS_MODE_SHA1:
 426                 d = SHA1_BLOCK_SIZE;
 427                 break;
 428         case FLAGS_MODE_SHA224:
 429         case FLAGS_MODE_SHA256:
 430                 d = SHA256_BLOCK_SIZE;
 431                 break;
 432         case FLAGS_MODE_SHA384:
 433         case FLAGS_MODE_SHA512:
 434                 d = SHA512_BLOCK_SIZE;
 435                 break;
 436         default:
 437                 d = 0;
 438         }
 439
 440         return d;
 441 }
 442
 443 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
 444                                     u32 *value, int count)
 445 {
 446         for (; count--; value++, offset += 4)
 447                 omap_sham_write(dd, offset, *value);
 448 }
 449
 450 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
 451                                  int final, int dma)
 452 {
 453         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 454         u32 val, mask;
 455
 456         if (likely(ctx->digcnt))
 457                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 458
 459         /*
 460          * Setting ALGO_CONST only for the first iteration and
 461          * CLOSE_HASH only for the last one. Note that flags mode bits
 462          * correspond to algorithm encoding in mode register.
 463          */
 464         val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
 465         if (!ctx->digcnt) {
 466                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 467                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 468                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 469                 int bs, nr_dr;
 470
 471                 val |= SHA_REG_MODE_ALGO_CONSTANT;
 472
 473                 if (ctx->flags & BIT(FLAGS_HMAC)) {
 474                         bs = get_block_size(ctx);
 475                         nr_dr = bs / (2 * sizeof(u32));
 476                         val |= SHA_REG_MODE_HMAC_KEY_PROC;
 477                         omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
 478                                           (u32 *)bctx->ipad, nr_dr);
 479                         omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
 480                                           (u32 *)bctx->ipad + nr_dr, nr_dr);
 481                         ctx->digcnt += bs;
 482                 }
 483         }
 484
 485         if (final) {
 486                 val |= SHA_REG_MODE_CLOSE_HASH;
 487
 488                 if (ctx->flags & BIT(FLAGS_HMAC))
 489                         val |= SHA_REG_MODE_HMAC_OUTER_HASH;
 490         }
 491
 492         mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
 493                SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
 494                SHA_REG_MODE_HMAC_KEY_PROC;
 495
 496         dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
 497         omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
 498         omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
 499         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 500                              SHA_REG_MASK_IT_EN |
 501                                      (dma ? SHA_REG_MASK_DMA_EN : 0),
 502                              SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 503 }
 504
 505 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
 506 {
 507         omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
 508 }
 509
 510 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
 511 {
 512         return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
 513                               SHA_REG_IRQSTATUS_INPUT_RDY);
 514 }
 515
 516 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
 517                               int final)
 518 {
 519         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 520         int count, len32, bs32, offset = 0;
 521         const u32 *buffer;
 522         int mlen;
 523         struct sg_mapping_iter mi;
 524
 525         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 526                                                 ctx->digcnt, length, final);
 527
 528         dd->pdata->write_ctrl(dd, length, final, 0);
 529         dd->pdata->trigger(dd, length);
 530
 531         /* should be non-zero before next lines to disable clocks later */
 532         ctx->digcnt += length;
 533         ctx->total -= length;
 534
 535         if (final)
 536                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 537
 538         set_bit(FLAGS_CPU, &dd->flags);
 539
 540         len32 = DIV_ROUND_UP(length, sizeof(u32));
 541         bs32 = get_block_size(ctx) / sizeof(u32);
 542
 543         sg_miter_start(&mi, ctx->sg, ctx->sg_len,
 544                        SG_MITER_FROM_SG | SG_MITER_ATOMIC);
 545
 546         mlen = 0;
 547
 548         while (len32) {
 549                 if (dd->pdata->poll_irq(dd))
 550                         return -ETIMEDOUT;
 551
 552                 for (count = 0; count < min(len32, bs32); count++, offset++) {
 553                         if (!mlen) {
 554                                 sg_miter_next(&mi);
 555                                 mlen = mi.length;
 556                                 if (!mlen) {
 557                                         pr_err("sg miter failure.\n");
 558                                         return -EINVAL;
 559                                 }
 560                                 offset = 0;
 561                                 buffer = mi.addr;
 562                         }
 563                         omap_sham_write(dd, SHA_REG_DIN(dd, count),
 564                                         buffer[offset]);
 565                         mlen -= 4;
 566                 }
 567                 len32 -= min(len32, bs32);
 568         }
 569
 570         sg_miter_stop(&mi);
 571
 572         return -EINPROGRESS;
 573 }
 574
 575 static void omap_sham_dma_callback(void *param)
 576 {
 577         struct omap_sham_dev *dd = param;
 578
 579         set_bit(FLAGS_DMA_READY, &dd->flags);
 580         tasklet_schedule(&dd->done_task);
 581 }
 582
 583 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
 584                               int final)
 585 {
 586         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 587         struct dma_async_tx_descriptor *tx;
 588         struct dma_slave_config cfg;
 589         int ret;
 590
 591         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 592                                                 ctx->digcnt, length, final);
 593
 594         if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
 595                 dev_err(dd->dev, "dma_map_sg error\n");
 596                 return -EINVAL;
 597         }
 598
 599         memset(&cfg, 0, sizeof(cfg));
 600
 601         cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
 602         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 603         cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
 604
 605         ret = dmaengine_slave_config(dd->dma_lch, &cfg);
 606         if (ret) {
 607                 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
 608                 return ret;
 609         }
 610
 611         tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
 612                                      DMA_MEM_TO_DEV,
 613                                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 614
 615         if (!tx) {
 616                 dev_err(dd->dev, "prep_slave_sg failed\n");
 617                 return -EINVAL;
 618         }
 619
 620         tx->callback = omap_sham_dma_callback;
 621         tx->callback_param = dd;
 622
 623         dd->pdata->write_ctrl(dd, length, final, 1);
 624
 625         ctx->digcnt += length;
 626         ctx->total -= length;
 627
 628         if (final)
 629                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 630
 631         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 632
 633         dmaengine_submit(tx);
 634         dma_async_issue_pending(dd->dma_lch);
 635
 636         dd->pdata->trigger(dd, length);
 637
 638         return -EINPROGRESS;
 639 }
 640
 641 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
 642                                    struct scatterlist *sg, int bs, int new_len)
 643 {
 644         int n = sg_nents(sg);
 645         struct scatterlist *tmp;
 646         int offset = ctx->offset;
 647
 648         if (ctx->bufcnt)
 649                 n++;
 650
 651         ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
 652         if (!ctx->sg)
 653                 return -ENOMEM;
 654
 655         sg_init_table(ctx->sg, n);
 656
 657         tmp = ctx->sg;
 658
 659         ctx->sg_len = 0;
 660
 661         if (ctx->bufcnt) {
 662                 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
 663                 tmp = sg_next(tmp);
 664                 ctx->sg_len++;
 665         }
 666
 667         while (sg && new_len) {
 668                 int len = sg->length - offset;
 669
 670                 if (offset) {
 671                         offset -= sg->length;
 672                         if (offset < 0)
 673                                 offset = 0;
 674                 }
 675
 676                 if (new_len < len)
 677                         len = new_len;
 678
 679                 if (len > 0) {
 680                         new_len -= len;
 681                         sg_set_page(tmp, sg_page(sg), len, sg->offset);
 682                         if (new_len <= 0)
 683                                 sg_mark_end(tmp);
 684                         tmp = sg_next(tmp);
 685                         ctx->sg_len++;
 686                 }
 687
 688                 sg = sg_next(sg);
 689         }
 690
 691         set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
 692
 693         ctx->bufcnt = 0;
 694
 695         return 0;
 696 }
 697
 698 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
 699                               struct scatterlist *sg, int bs, int new_len)
 700 {
 701         int pages;
 702         void *buf;
 703         int len;
 704
 705         len = new_len + ctx->bufcnt;
 706
 707         pages = get_order(ctx->total);
 708
 709         buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
 710         if (!buf) {
 711                 pr_err("Couldn't allocate pages for unaligned cases.\n");
 712                 return -ENOMEM;
 713         }
 714
 715         if (ctx->bufcnt)
 716                 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
 717
 718         scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
 719                                  ctx->total - ctx->bufcnt, 0);
 720         sg_init_table(ctx->sgl, 1);
 721         sg_set_buf(ctx->sgl, buf, len);
 722         ctx->sg = ctx->sgl;
 723         set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
 724         ctx->sg_len = 1;
 725         ctx->bufcnt = 0;
 726         ctx->offset = 0;
 727
 728         return 0;
 729 }
 730
 731 static int omap_sham_align_sgs(struct scatterlist *sg,
 732                                int nbytes, int bs, bool final,
 733                                struct omap_sham_reqctx *rctx)
 734 {
 735         int n = 0;
 736         bool aligned = true;
 737         bool list_ok = true;
 738         struct scatterlist *sg_tmp = sg;
 739         int new_len;
 740         int offset = rctx->offset;
 741
 742         if (!sg || !sg->length || !nbytes)
 743                 return 0;
 744
 745         new_len = nbytes;
 746
 747         if (offset)
 748                 list_ok = false;
 749
 750         if (final)
 751                 new_len = DIV_ROUND_UP(new_len, bs) * bs;
 752         else
 753                 new_len = (new_len - 1) / bs * bs;
 754
 755         if (nbytes != new_len)
 756                 list_ok = false;
 757
 758         while (nbytes > 0 && sg_tmp) {
 759                 n++;
 760
 761 #ifdef CONFIG_ZONE_DMA
 762                 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) {
 763                         aligned = false;
 764                         break;
 765                 }
 766 #endif
 767
 768                 if (offset < sg_tmp->length) {
 769                         if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
 770                                 aligned = false;
 771                                 break;
 772                         }
 773
 774                         if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
 775                                 aligned = false;
 776                                 break;
 777                         }
 778                 }
 779
 780                 if (offset) {
 781                         offset -= sg_tmp->length;
 782                         if (offset < 0) {
 783                                 nbytes += offset;
 784                                 offset = 0;
 785                         }
 786                 } else {
 787                         nbytes -= sg_tmp->length;
 788                 }
 789
 790                 sg_tmp = sg_next(sg_tmp);
 791
 792                 if (nbytes < 0) {
 793                         list_ok = false;
 794                         break;
 795                 }
 796         }
 797
 798         if (!aligned)
 799                 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
 800         else if (!list_ok)
 801                 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
 802
 803         rctx->sg_len = n;
 804         rctx->sg = sg;
 805
 806         return 0;
 807 }
 808
 809 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
 810 {
 811         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
 812         int bs;
 813         int ret;
 814         int nbytes;
 815         bool final = rctx->flags & BIT(FLAGS_FINUP);
 816         int xmit_len, hash_later;
 817
 818         bs = get_block_size(rctx);
 819
 820         if (update)
 821                 nbytes = req->nbytes;
 822         else
 823                 nbytes = 0;
 824
 825         rctx->total = nbytes + rctx->bufcnt;
 826
 827         if (!rctx->total)
 828                 return 0;
 829
 830         if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
 831                 int len = bs - rctx->bufcnt % bs;
 832
 833                 if (len > nbytes)
 834                         len = nbytes;
 835                 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
 836                                          0, len, 0);
 837                 rctx->bufcnt += len;
 838                 nbytes -= len;
 839                 rctx->offset = len;
 840         }
 841
 842         if (rctx->bufcnt)
 843                 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
 844
 845         ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
 846         if (ret)
 847                 return ret;
 848
 849         xmit_len = rctx->total;
 850
 851         if (!IS_ALIGNED(xmit_len, bs)) {
 852                 if (final)
 853                         xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs;
 854                 else
 855                         xmit_len = xmit_len / bs * bs;
 856         } else if (!final) {
 857                 xmit_len -= bs;
 858         }
 859
 860         hash_later = rctx->total - xmit_len;
 861         if (hash_later < 0)
 862                 hash_later = 0;
 863
 864         if (rctx->bufcnt && nbytes) {
 865                 /* have data from previous operation and current */
 866                 sg_init_table(rctx->sgl, 2);
 867                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
 868
 869                 sg_chain(rctx->sgl, 2, req->src);
 870
 871                 rctx->sg = rctx->sgl;
 872
 873                 rctx->sg_len++;
 874         } else if (rctx->bufcnt) {
 875                 /* have buffered data only */
 876                 sg_init_table(rctx->sgl, 1);
 877                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len);
 878
 879                 rctx->sg = rctx->sgl;
 880
 881                 rctx->sg_len = 1;
 882         }
 883
 884         if (hash_later) {
 885                 int offset = 0;
 886
 887                 if (hash_later > req->nbytes) {
 888                         memcpy(rctx->buffer, rctx->buffer + xmit_len,
 889                                hash_later - req->nbytes);
 890                         offset = hash_later - req->nbytes;
 891                 }
 892
 893                 if (req->nbytes) {
 894                         scatterwalk_map_and_copy(rctx->buffer + offset,
 895                                                  req->src,
 896                                                  offset + req->nbytes -
 897                                                  hash_later, hash_later, 0);
 898                 }
 899
 900                 rctx->bufcnt = hash_later;
 901         } else {
 902                 rctx->bufcnt = 0;
 903         }
 904
 905         if (!final)
 906                 rctx->total = xmit_len;
 907
 908         return 0;
 909 }
 910
 911 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 912 {
 913         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 914
 915         dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
 916
 917         clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 918
 919         return 0;
 920 }
 921
 922 struct omap_sham_dev *omap_sham_find_dev(struct omap_sham_reqctx *ctx)
 923 {
 924         struct omap_sham_dev *dd;
 925
 926         if (ctx->dd)
 927                 return ctx->dd;
 928
 929         spin_lock_bh(&sham.lock);
 930         dd = list_first_entry(&sham.dev_list, struct omap_sham_dev, list);
 931         list_move_tail(&dd->list, &sham.dev_list);
 932         ctx->dd = dd;
 933         spin_unlock_bh(&sham.lock);
 934
 935         return dd;
 936 }
 937
 938 static int omap_sham_init(struct ahash_request *req)
 939 {
 940         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 941         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 942         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 943         struct omap_sham_dev *dd;
 944         int bs = 0;
 945
 946         ctx->dd = NULL;
 947
 948         dd = omap_sham_find_dev(ctx);
 949         if (!dd)
 950                 return -ENODEV;
 951
 952         ctx->flags = 0;
 953
 954         dev_dbg(dd->dev, "init: digest size: %d\n",
 955                 crypto_ahash_digestsize(tfm));
 956
 957         switch (crypto_ahash_digestsize(tfm)) {
 958         case MD5_DIGEST_SIZE:
 959                 ctx->flags |= FLAGS_MODE_MD5;
 960                 bs = SHA1_BLOCK_SIZE;
 961                 break;
 962         case SHA1_DIGEST_SIZE:
 963                 ctx->flags |= FLAGS_MODE_SHA1;
 964                 bs = SHA1_BLOCK_SIZE;
 965                 break;
 966         case SHA224_DIGEST_SIZE:
 967                 ctx->flags |= FLAGS_MODE_SHA224;
 968                 bs = SHA224_BLOCK_SIZE;
 969                 break;
 970         case SHA256_DIGEST_SIZE:
 971                 ctx->flags |= FLAGS_MODE_SHA256;
 972                 bs = SHA256_BLOCK_SIZE;
 973                 break;
 974         case SHA384_DIGEST_SIZE:
 975                 ctx->flags |= FLAGS_MODE_SHA384;
 976                 bs = SHA384_BLOCK_SIZE;
 977                 break;
 978         case SHA512_DIGEST_SIZE:
 979                 ctx->flags |= FLAGS_MODE_SHA512;
 980                 bs = SHA512_BLOCK_SIZE;
 981                 break;
 982         }
 983
 984         ctx->bufcnt = 0;
 985         ctx->digcnt = 0;
 986         ctx->total = 0;
 987         ctx->offset = 0;
 988         ctx->buflen = BUFLEN;
 989
 990         if (tctx->flags & BIT(FLAGS_HMAC)) {
 991                 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
 992                         struct omap_sham_hmac_ctx *bctx = tctx->base;
 993
 994                         memcpy(ctx->buffer, bctx->ipad, bs);
 995                         ctx->bufcnt = bs;
 996                 }
 997
 998                 ctx->flags |= BIT(FLAGS_HMAC);
 999         }
1000
1001         return 0;
1002
1003 }
1004
1005 static int omap_sham_update_req(struct omap_sham_dev *dd)
1006 {
1007         struct ahash_request *req = dd->req;
1008         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1009         int err;
1010         bool final = ctx->flags & BIT(FLAGS_FINUP);
1011
1012         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
1013                  ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
1014
1015         if (ctx->total < get_block_size(ctx) ||
1016             ctx->total < dd->fallback_sz)
1017                 ctx->flags |= BIT(FLAGS_CPU);
1018
1019         if (ctx->flags & BIT(FLAGS_CPU))
1020                 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1021         else
1022                 err = omap_sham_xmit_dma(dd, ctx->total, final);
1023
1024         /* wait for dma completion before can take more data */
1025         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1026
1027         return err;
1028 }
1029
1030 static int omap_sham_final_req(struct omap_sham_dev *dd)
1031 {
1032         struct ahash_request *req = dd->req;
1033         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1034         int err = 0, use_dma = 1;
1035
1036         if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1037                 /*
1038                  * faster to handle last block with cpu or
1039                  * use cpu when dma is not present.
1040                  */
1041                 use_dma = 0;
1042
1043         if (use_dma)
1044                 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1045         else
1046                 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1047
1048         ctx->bufcnt = 0;
1049
1050         dev_dbg(dd->dev, "final_req: err: %d\n", err);
1051
1052         return err;
1053 }
1054
1055 static int omap_sham_finish_hmac(struct ahash_request *req)
1056 {
1057         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1058         struct omap_sham_hmac_ctx *bctx = tctx->base;
1059         int bs = crypto_shash_blocksize(bctx->shash);
1060         int ds = crypto_shash_digestsize(bctx->shash);
1061         SHASH_DESC_ON_STACK(shash, bctx->shash);
1062
1063         shash->tfm = bctx->shash;
1064
1065         return crypto_shash_init(shash) ?:
1066                crypto_shash_update(shash, bctx->opad, bs) ?:
1067                crypto_shash_finup(shash, req->result, ds, req->result);
1068 }
1069
1070 static int omap_sham_finish(struct ahash_request *req)
1071 {
1072         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1073         struct omap_sham_dev *dd = ctx->dd;
1074         int err = 0;
1075
1076         if (ctx->digcnt) {
1077                 omap_sham_copy_ready_hash(req);
1078                 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1079                                 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1080                         err = omap_sham_finish_hmac(req);
1081         }
1082
1083         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1084
1085         return err;
1086 }
1087
1088 static void omap_sham_finish_req(struct ahash_request *req, int err)
1089 {
1090         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1091         struct omap_sham_dev *dd = ctx->dd;
1092
1093         if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1094                 free_pages((unsigned long)sg_virt(ctx->sg),
1095                            get_order(ctx->sg->length + ctx->bufcnt));
1096
1097         if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1098                 kfree(ctx->sg);
1099
1100         ctx->sg = NULL;
1101
1102         dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1103
1104         if (!err) {
1105                 dd->pdata->copy_hash(req, 1);
1106                 if (test_bit(FLAGS_FINAL, &dd->flags))
1107                         err = omap_sham_finish(req);
1108         } else {
1109                 ctx->flags |= BIT(FLAGS_ERROR);
1110         }
1111
1112         /* atomic operation is not needed here */
1113         dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1114                         BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1115
1116         pm_runtime_mark_last_busy(dd->dev);
1117         pm_runtime_put_autosuspend(dd->dev);
1118
1119         if (req->base.complete)
1120                 req->base.complete(&req->base, err);
1121 }
1122
1123 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1124                                   struct ahash_request *req)
1125 {
1126         struct crypto_async_request *async_req, *backlog;
1127         struct omap_sham_reqctx *ctx;
1128         unsigned long flags;
1129         int err = 0, ret = 0;
1130
1131 retry:
1132         spin_lock_irqsave(&dd->lock, flags);
1133         if (req)
1134                 ret = ahash_enqueue_request(&dd->queue, req);
1135         if (test_bit(FLAGS_BUSY, &dd->flags)) {
1136                 spin_unlock_irqrestore(&dd->lock, flags);
1137                 return ret;
1138         }
1139         backlog = crypto_get_backlog(&dd->queue);
1140         async_req = crypto_dequeue_request(&dd->queue);
1141         if (async_req)
1142                 set_bit(FLAGS_BUSY, &dd->flags);
1143         spin_unlock_irqrestore(&dd->lock, flags);
1144
1145         if (!async_req)
1146                 return ret;
1147
1148         if (backlog)
1149                 backlog->complete(backlog, -EINPROGRESS);
1150
1151         req = ahash_request_cast(async_req);
1152         dd->req = req;
1153         ctx = ahash_request_ctx(req);
1154
1155         err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1156         if (err || !ctx->total)
1157                 goto err1;
1158
1159         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1160                                                 ctx->op, req->nbytes);
1161
1162         err = omap_sham_hw_init(dd);
1163         if (err)
1164                 goto err1;
1165
1166         if (ctx->digcnt)
1167                 /* request has changed - restore hash */
1168                 dd->pdata->copy_hash(req, 0);
1169
1170         if (ctx->op == OP_UPDATE) {
1171                 err = omap_sham_update_req(dd);
1172                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1173                         /* no final() after finup() */
1174                         err = omap_sham_final_req(dd);
1175         } else if (ctx->op == OP_FINAL) {
1176                 err = omap_sham_final_req(dd);
1177         }
1178 err1:
1179         dev_dbg(dd->dev, "exit, err: %d\n", err);
1180
1181         if (err != -EINPROGRESS) {
1182                 /* done_task will not finish it, so do it here */
1183                 omap_sham_finish_req(req, err);
1184                 req = NULL;
1185
1186                 /*
1187                  * Execute next request immediately if there is anything
1188                  * in queue.
1189                  */
1190                 goto retry;
1191         }
1192
1193         return ret;
1194 }
1195
1196 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1197 {
1198         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1199         struct omap_sham_dev *dd = ctx->dd;
1200
1201         ctx->op = op;
1202
1203         return omap_sham_handle_queue(dd, req);
1204 }
1205
1206 static int omap_sham_update(struct ahash_request *req)
1207 {
1208         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1209         struct omap_sham_dev *dd = omap_sham_find_dev(ctx);
1210
1211         if (!req->nbytes)
1212                 return 0;
1213
1214         if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1215                 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1216                                          0, req->nbytes, 0);
1217                 ctx->bufcnt += req->nbytes;
1218                 return 0;
1219         }
1220
1221         if (dd->polling_mode)
1222                 ctx->flags |= BIT(FLAGS_CPU);
1223
1224         return omap_sham_enqueue(req, OP_UPDATE);
1225 }
1226
1227 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1228                                   const u8 *data, unsigned int len, u8 *out)
1229 {
1230         SHASH_DESC_ON_STACK(shash, tfm);
1231
1232         shash->tfm = tfm;
1233
1234         return crypto_shash_digest(shash, data, len, out);
1235 }
1236
1237 static int omap_sham_final_shash(struct ahash_request *req)
1238 {
1239         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1240         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1241         int offset = 0;
1242
1243         /*
1244          * If we are running HMAC on limited hardware support, skip
1245          * the ipad in the beginning of the buffer if we are going for
1246          * software fallback algorithm.
1247          */
1248         if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1249             !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1250                 offset = get_block_size(ctx);
1251
1252         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1253                                       ctx->buffer + offset,
1254                                       ctx->bufcnt - offset, req->result);
1255 }
1256
1257 static int omap_sham_final(struct ahash_request *req)
1258 {
1259         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1260
1261         ctx->flags |= BIT(FLAGS_FINUP);
1262
1263         if (ctx->flags & BIT(FLAGS_ERROR))
1264                 return 0; /* uncompleted hash is not needed */
1265
1266         /*
1267          * OMAP HW accel works only with buffers >= 9.
1268          * HMAC is always >= 9 because ipad == block size.
1269          * If buffersize is less than fallback_sz, we use fallback
1270          * SW encoding, as using DMA + HW in this case doesn't provide
1271          * any benefit.
1272          */
1273         if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz)
1274                 return omap_sham_final_shash(req);
1275         else if (ctx->bufcnt)
1276                 return omap_sham_enqueue(req, OP_FINAL);
1277
1278         /* copy ready hash (+ finalize hmac) */
1279         return omap_sham_finish(req);
1280 }
1281
1282 static int omap_sham_finup(struct ahash_request *req)
1283 {
1284         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1285         int err1, err2;
1286
1287         ctx->flags |= BIT(FLAGS_FINUP);
1288
1289         err1 = omap_sham_update(req);
1290         if (err1 == -EINPROGRESS || err1 == -EBUSY)
1291                 return err1;
1292         /*
1293          * final() has to be always called to cleanup resources
1294          * even if udpate() failed, except EINPROGRESS
1295          */
1296         err2 = omap_sham_final(req);
1297
1298         return err1 ?: err2;
1299 }
1300
1301 static int omap_sham_digest(struct ahash_request *req)
1302 {
1303         return omap_sham_init(req) ?: omap_sham_finup(req);
1304 }
1305
1306 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1307                       unsigned int keylen)
1308 {
1309         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1310         struct omap_sham_hmac_ctx *bctx = tctx->base;
1311         int bs = crypto_shash_blocksize(bctx->shash);
1312         int ds = crypto_shash_digestsize(bctx->shash);
1313         int err, i;
1314
1315         err = crypto_shash_setkey(tctx->fallback, key, keylen);
1316         if (err)
1317                 return err;
1318
1319         if (keylen > bs) {
1320                 err = omap_sham_shash_digest(bctx->shash,
1321                                 crypto_shash_get_flags(bctx->shash),
1322                                 key, keylen, bctx->ipad);
1323                 if (err)
1324                         return err;
1325                 keylen = ds;
1326         } else {
1327                 memcpy(bctx->ipad, key, keylen);
1328         }
1329
1330         memset(bctx->ipad + keylen, 0, bs - keylen);
1331
1332         if (!test_bit(FLAGS_AUTO_XOR, &sham.flags)) {
1333                 memcpy(bctx->opad, bctx->ipad, bs);
1334
1335                 for (i = 0; i < bs; i++) {
1336                         bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1337                         bctx->opad[i] ^= HMAC_OPAD_VALUE;
1338                 }
1339         }
1340
1341         return err;
1342 }
1343
1344 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1345 {
1346         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1347         const char *alg_name = crypto_tfm_alg_name(tfm);
1348
1349         /* Allocate a fallback and abort if it failed. */
1350         tctx->fallback = crypto_alloc_shash(alg_name, 0,
1351                                             CRYPTO_ALG_NEED_FALLBACK);
1352         if (IS_ERR(tctx->fallback)) {
1353                 pr_err("omap-sham: fallback driver '%s' "
1354                                 "could not be loaded.\n", alg_name);
1355                 return PTR_ERR(tctx->fallback);
1356         }
1357
1358         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1359                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
1360
1361         if (alg_base) {
1362                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1363                 tctx->flags |= BIT(FLAGS_HMAC);
1364                 bctx->shash = crypto_alloc_shash(alg_base, 0,
1365                                                 CRYPTO_ALG_NEED_FALLBACK);
1366                 if (IS_ERR(bctx->shash)) {
1367                         pr_err("omap-sham: base driver '%s' "
1368                                         "could not be loaded.\n", alg_base);
1369                         crypto_free_shash(tctx->fallback);
1370                         return PTR_ERR(bctx->shash);
1371                 }
1372
1373         }
1374
1375         return 0;
1376 }
1377
1378 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1379 {
1380         return omap_sham_cra_init_alg(tfm, NULL);
1381 }
1382
1383 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1384 {
1385         return omap_sham_cra_init_alg(tfm, "sha1");
1386 }
1387
1388 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1389 {
1390         return omap_sham_cra_init_alg(tfm, "sha224");
1391 }
1392
1393 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1394 {
1395         return omap_sham_cra_init_alg(tfm, "sha256");
1396 }
1397
1398 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1399 {
1400         return omap_sham_cra_init_alg(tfm, "md5");
1401 }
1402
1403 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1404 {
1405         return omap_sham_cra_init_alg(tfm, "sha384");
1406 }
1407
1408 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1409 {
1410         return omap_sham_cra_init_alg(tfm, "sha512");
1411 }
1412
1413 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1414 {
1415         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1416
1417         crypto_free_shash(tctx->fallback);
1418         tctx->fallback = NULL;
1419
1420         if (tctx->flags & BIT(FLAGS_HMAC)) {
1421                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1422                 crypto_free_shash(bctx->shash);
1423         }
1424 }
1425
1426 static int omap_sham_export(struct ahash_request *req, void *out)
1427 {
1428         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1429
1430         memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1431
1432         return 0;
1433 }
1434
1435 static int omap_sham_import(struct ahash_request *req, const void *in)
1436 {
1437         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1438         const struct omap_sham_reqctx *ctx_in = in;
1439
1440         memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1441
1442         return 0;
1443 }
1444
1445 static struct ahash_alg algs_sha1_md5[] = {
1446 {
1447         .init           = omap_sham_init,
1448         .update         = omap_sham_update,
1449         .final          = omap_sham_final,
1450         .finup          = omap_sham_finup,
1451         .digest         = omap_sham_digest,
1452         .halg.digestsize        = SHA1_DIGEST_SIZE,
1453         .halg.base      = {
1454                 .cra_name               = "sha1",
1455                 .cra_driver_name        = "omap-sha1",
1456                 .cra_priority           = 400,
1457                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1458                                                 CRYPTO_ALG_ASYNC |
1459                                                 CRYPTO_ALG_NEED_FALLBACK,
1460                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1461                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1462                 .cra_alignmask          = OMAP_ALIGN_MASK,
1463                 .cra_module             = THIS_MODULE,
1464                 .cra_init               = omap_sham_cra_init,
1465                 .cra_exit               = omap_sham_cra_exit,
1466         }
1467 },
1468 {
1469         .init           = omap_sham_init,
1470         .update         = omap_sham_update,
1471         .final          = omap_sham_final,
1472         .finup          = omap_sham_finup,
1473         .digest         = omap_sham_digest,
1474         .halg.digestsize        = MD5_DIGEST_SIZE,
1475         .halg.base      = {
1476                 .cra_name               = "md5",
1477                 .cra_driver_name        = "omap-md5",
1478                 .cra_priority           = 400,
1479                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1480                                                 CRYPTO_ALG_ASYNC |
1481                                                 CRYPTO_ALG_NEED_FALLBACK,
1482                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1483                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1484                 .cra_alignmask          = OMAP_ALIGN_MASK,
1485                 .cra_module             = THIS_MODULE,
1486                 .cra_init               = omap_sham_cra_init,
1487                 .cra_exit               = omap_sham_cra_exit,
1488         }
1489 },
1490 {
1491         .init           = omap_sham_init,
1492         .update         = omap_sham_update,
1493         .final          = omap_sham_final,
1494         .finup          = omap_sham_finup,
1495         .digest         = omap_sham_digest,
1496         .setkey         = omap_sham_setkey,
1497         .halg.digestsize        = SHA1_DIGEST_SIZE,
1498         .halg.base      = {
1499                 .cra_name               = "hmac(sha1)",
1500                 .cra_driver_name        = "omap-hmac-sha1",
1501                 .cra_priority           = 400,
1502                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1503                                                 CRYPTO_ALG_ASYNC |
1504                                                 CRYPTO_ALG_NEED_FALLBACK,
1505                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1506                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1507                                         sizeof(struct omap_sham_hmac_ctx),
1508                 .cra_alignmask          = OMAP_ALIGN_MASK,
1509                 .cra_module             = THIS_MODULE,
1510                 .cra_init               = omap_sham_cra_sha1_init,
1511                 .cra_exit               = omap_sham_cra_exit,
1512         }
1513 },
1514 {
1515         .init           = omap_sham_init,
1516         .update         = omap_sham_update,
1517         .final          = omap_sham_final,
1518         .finup          = omap_sham_finup,
1519         .digest         = omap_sham_digest,
1520         .setkey         = omap_sham_setkey,
1521         .halg.digestsize        = MD5_DIGEST_SIZE,
1522         .halg.base      = {
1523                 .cra_name               = "hmac(md5)",
1524                 .cra_driver_name        = "omap-hmac-md5",
1525                 .cra_priority           = 400,
1526                 .cra_flags              = CRYPTO_ALG_KERN_DRIVER_ONLY |
1527                                                 CRYPTO_ALG_ASYNC |
1528                                                 CRYPTO_ALG_NEED_FALLBACK,
1529                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1530                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1531                                         sizeof(struct omap_sham_hmac_ctx),
1532                 .cra_alignmask          = OMAP_ALIGN_MASK,
1533                 .cra_module             = THIS_MODULE,
1534                 .cra_init               = omap_sham_cra_md5_init,
1535                 .cra_exit               = omap_sham_cra_exit,
1536         }
1537 }
1538 };
1539
1540 /* OMAP4 has some algs in addition to what OMAP2 has */
1541 static struct ahash_alg algs_sha224_sha256[] = {
1542 {
1543         .init           = omap_sham_init,
1544         .update         = omap_sham_update,
1545         .final          = omap_sham_final,
1546         .finup          = omap_sham_finup,
1547         .digest         = omap_sham_digest,
1548         .halg.digestsize        = SHA224_DIGEST_SIZE,
1549         .halg.base      = {
1550                 .cra_name               = "sha224",
1551                 .cra_driver_name        = "omap-sha224",
1552                 .cra_priority           = 400,
1553                 .cra_flags              = CRYPTO_ALG_ASYNC |
1554                                                 CRYPTO_ALG_NEED_FALLBACK,
1555                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1556                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1557                 .cra_alignmask          = OMAP_ALIGN_MASK,
1558                 .cra_module             = THIS_MODULE,
1559                 .cra_init               = omap_sham_cra_init,
1560                 .cra_exit               = omap_sham_cra_exit,
1561         }
1562 },
1563 {
1564         .init           = omap_sham_init,
1565         .update         = omap_sham_update,
1566         .final          = omap_sham_final,
1567         .finup          = omap_sham_finup,
1568         .digest         = omap_sham_digest,
1569         .halg.digestsize        = SHA256_DIGEST_SIZE,
1570         .halg.base      = {
1571                 .cra_name               = "sha256",
1572                 .cra_driver_name        = "omap-sha256",
1573                 .cra_priority           = 400,
1574                 .cra_flags              = CRYPTO_ALG_ASYNC |
1575                                                 CRYPTO_ALG_NEED_FALLBACK,
1576                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1577                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1578                 .cra_alignmask          = OMAP_ALIGN_MASK,
1579                 .cra_module             = THIS_MODULE,
1580                 .cra_init               = omap_sham_cra_init,
1581                 .cra_exit               = omap_sham_cra_exit,
1582         }
1583 },
1584 {
1585         .init           = omap_sham_init,
1586         .update         = omap_sham_update,
1587         .final          = omap_sham_final,
1588         .finup          = omap_sham_finup,
1589         .digest         = omap_sham_digest,
1590         .setkey         = omap_sham_setkey,
1591         .halg.digestsize        = SHA224_DIGEST_SIZE,
1592         .halg.base      = {
1593                 .cra_name               = "hmac(sha224)",
1594                 .cra_driver_name        = "omap-hmac-sha224",
1595                 .cra_priority           = 400,
1596                 .cra_flags              = CRYPTO_ALG_ASYNC |
1597                                                 CRYPTO_ALG_NEED_FALLBACK,
1598                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1599                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1600                                         sizeof(struct omap_sham_hmac_ctx),
1601                 .cra_alignmask          = OMAP_ALIGN_MASK,
1602                 .cra_module             = THIS_MODULE,
1603                 .cra_init               = omap_sham_cra_sha224_init,
1604                 .cra_exit               = omap_sham_cra_exit,
1605         }
1606 },
1607 {
1608         .init           = omap_sham_init,
1609         .update         = omap_sham_update,
1610         .final          = omap_sham_final,
1611         .finup          = omap_sham_finup,
1612         .digest         = omap_sham_digest,
1613         .setkey         = omap_sham_setkey,
1614         .halg.digestsize        = SHA256_DIGEST_SIZE,
1615         .halg.base      = {
1616                 .cra_name               = "hmac(sha256)",
1617                 .cra_driver_name        = "omap-hmac-sha256",
1618                 .cra_priority           = 400,
1619                 .cra_flags              = CRYPTO_ALG_ASYNC |
1620                                                 CRYPTO_ALG_NEED_FALLBACK,
1621                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1622                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1623                                         sizeof(struct omap_sham_hmac_ctx),
1624                 .cra_alignmask          = OMAP_ALIGN_MASK,
1625                 .cra_module             = THIS_MODULE,
1626                 .cra_init               = omap_sham_cra_sha256_init,
1627                 .cra_exit               = omap_sham_cra_exit,
1628         }
1629 },
1630 };
1631
1632 static struct ahash_alg algs_sha384_sha512[] = {
1633 {
1634         .init           = omap_sham_init,
1635         .update         = omap_sham_update,
1636         .final          = omap_sham_final,
1637         .finup          = omap_sham_finup,
1638         .digest         = omap_sham_digest,
1639         .halg.digestsize        = SHA384_DIGEST_SIZE,
1640         .halg.base      = {
1641                 .cra_name               = "sha384",
1642                 .cra_driver_name        = "omap-sha384",
1643                 .cra_priority           = 400,
1644                 .cra_flags              = CRYPTO_ALG_ASYNC |
1645                                                 CRYPTO_ALG_NEED_FALLBACK,
1646                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1647                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1648                 .cra_alignmask          = OMAP_ALIGN_MASK,
1649                 .cra_module             = THIS_MODULE,
1650                 .cra_init               = omap_sham_cra_init,
1651                 .cra_exit               = omap_sham_cra_exit,
1652         }
1653 },
1654 {
1655         .init           = omap_sham_init,
1656         .update         = omap_sham_update,
1657         .final          = omap_sham_final,
1658         .finup          = omap_sham_finup,
1659         .digest         = omap_sham_digest,
1660         .halg.digestsize        = SHA512_DIGEST_SIZE,
1661         .halg.base      = {
1662                 .cra_name               = "sha512",
1663                 .cra_driver_name        = "omap-sha512",
1664                 .cra_priority           = 400,
1665                 .cra_flags              = CRYPTO_ALG_ASYNC |
1666                                                 CRYPTO_ALG_NEED_FALLBACK,
1667                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1668                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1669                 .cra_alignmask          = OMAP_ALIGN_MASK,
1670                 .cra_module             = THIS_MODULE,
1671                 .cra_init               = omap_sham_cra_init,
1672                 .cra_exit               = omap_sham_cra_exit,
1673         }
1674 },
1675 {
1676         .init           = omap_sham_init,
1677         .update         = omap_sham_update,
1678         .final          = omap_sham_final,
1679         .finup          = omap_sham_finup,
1680         .digest         = omap_sham_digest,
1681         .setkey         = omap_sham_setkey,
1682         .halg.digestsize        = SHA384_DIGEST_SIZE,
1683         .halg.base      = {
1684                 .cra_name               = "hmac(sha384)",
1685                 .cra_driver_name        = "omap-hmac-sha384",
1686                 .cra_priority           = 400,
1687                 .cra_flags              = CRYPTO_ALG_ASYNC |
1688                                                 CRYPTO_ALG_NEED_FALLBACK,
1689                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1690                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1691                                         sizeof(struct omap_sham_hmac_ctx),
1692                 .cra_alignmask          = OMAP_ALIGN_MASK,
1693                 .cra_module             = THIS_MODULE,
1694                 .cra_init               = omap_sham_cra_sha384_init,
1695                 .cra_exit               = omap_sham_cra_exit,
1696         }
1697 },
1698 {
1699         .init           = omap_sham_init,
1700         .update         = omap_sham_update,
1701         .final          = omap_sham_final,
1702         .finup          = omap_sham_finup,
1703         .digest         = omap_sham_digest,
1704         .setkey         = omap_sham_setkey,
1705         .halg.digestsize        = SHA512_DIGEST_SIZE,
1706         .halg.base      = {
1707                 .cra_name               = "hmac(sha512)",
1708                 .cra_driver_name        = "omap-hmac-sha512",
1709                 .cra_priority           = 400,
1710                 .cra_flags              = CRYPTO_ALG_ASYNC |
1711                                                 CRYPTO_ALG_NEED_FALLBACK,
1712                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1713                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1714                                         sizeof(struct omap_sham_hmac_ctx),
1715                 .cra_alignmask          = OMAP_ALIGN_MASK,
1716                 .cra_module             = THIS_MODULE,
1717                 .cra_init               = omap_sham_cra_sha512_init,
1718                 .cra_exit               = omap_sham_cra_exit,
1719         }
1720 },
1721 };
1722
1723 static void omap_sham_done_task(unsigned long data)
1724 {
1725         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1726         int err = 0;
1727
1728         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1729                 omap_sham_handle_queue(dd, NULL);
1730                 return;
1731         }
1732
1733         if (test_bit(FLAGS_CPU, &dd->flags)) {
1734                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1735                         goto finish;
1736         } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1737                 if (test_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1738                         omap_sham_update_dma_stop(dd);
1739                         if (dd->err) {
1740                                 err = dd->err;
1741                                 goto finish;
1742                         }
1743                 }
1744                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1745                         /* hash or semi-hash ready */
1746                         clear_bit(FLAGS_DMA_READY, &dd->flags);
1747                         goto finish;
1748                 }
1749         }
1750
1751         return;
1752
1753 finish:
1754         dev_dbg(dd->dev, "update done: err: %d\n", err);
1755         /* finish curent request */
1756         omap_sham_finish_req(dd->req, err);
1757
1758         /* If we are not busy, process next req */
1759         if (!test_bit(FLAGS_BUSY, &dd->flags))
1760                 omap_sham_handle_queue(dd, NULL);
1761 }
1762
1763 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1764 {
1765         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1766                 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1767         } else {
1768                 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1769                 tasklet_schedule(&dd->done_task);
1770         }
1771
1772         return IRQ_HANDLED;
1773 }
1774
1775 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1776 {
1777         struct omap_sham_dev *dd = dev_id;
1778
1779         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1780                 /* final -> allow device to go to power-saving mode */
1781                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1782
1783         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1784                                  SHA_REG_CTRL_OUTPUT_READY);
1785         omap_sham_read(dd, SHA_REG_CTRL);
1786
1787         return omap_sham_irq_common(dd);
1788 }
1789
1790 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1791 {
1792         struct omap_sham_dev *dd = dev_id;
1793
1794         omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1795
1796         return omap_sham_irq_common(dd);
1797 }
1798
1799 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1800         {
1801                 .algs_list      = algs_sha1_md5,
1802                 .size           = ARRAY_SIZE(algs_sha1_md5),
1803         },
1804 };
1805
1806 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1807         .algs_info      = omap_sham_algs_info_omap2,
1808         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1809         .flags          = BIT(FLAGS_BE32_SHA1),
1810         .digest_size    = SHA1_DIGEST_SIZE,
1811         .copy_hash      = omap_sham_copy_hash_omap2,
1812         .write_ctrl     = omap_sham_write_ctrl_omap2,
1813         .trigger        = omap_sham_trigger_omap2,
1814         .poll_irq       = omap_sham_poll_irq_omap2,
1815         .intr_hdlr      = omap_sham_irq_omap2,
1816         .idigest_ofs    = 0x00,
1817         .din_ofs        = 0x1c,
1818         .digcnt_ofs     = 0x14,
1819         .rev_ofs        = 0x5c,
1820         .mask_ofs       = 0x60,
1821         .sysstatus_ofs  = 0x64,
1822         .major_mask     = 0xf0,
1823         .major_shift    = 4,
1824         .minor_mask     = 0x0f,
1825         .minor_shift    = 0,
1826 };
1827
1828 #ifdef CONFIG_OF
1829 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1830         {
1831                 .algs_list      = algs_sha1_md5,
1832                 .size           = ARRAY_SIZE(algs_sha1_md5),
1833         },
1834         {
1835                 .algs_list      = algs_sha224_sha256,
1836                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1837         },
1838 };
1839
1840 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1841         .algs_info      = omap_sham_algs_info_omap4,
1842         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1843         .flags          = BIT(FLAGS_AUTO_XOR),
1844         .digest_size    = SHA256_DIGEST_SIZE,
1845         .copy_hash      = omap_sham_copy_hash_omap4,
1846         .write_ctrl     = omap_sham_write_ctrl_omap4,
1847         .trigger        = omap_sham_trigger_omap4,
1848         .poll_irq       = omap_sham_poll_irq_omap4,
1849         .intr_hdlr      = omap_sham_irq_omap4,
1850         .idigest_ofs    = 0x020,
1851         .odigest_ofs    = 0x0,
1852         .din_ofs        = 0x080,
1853         .digcnt_ofs     = 0x040,
1854         .rev_ofs        = 0x100,
1855         .mask_ofs       = 0x110,
1856         .sysstatus_ofs  = 0x114,
1857         .mode_ofs       = 0x44,
1858         .length_ofs     = 0x48,
1859         .major_mask     = 0x0700,
1860         .major_shift    = 8,
1861         .minor_mask     = 0x003f,
1862         .minor_shift    = 0,
1863 };
1864
1865 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1866         {
1867                 .algs_list      = algs_sha1_md5,
1868                 .size           = ARRAY_SIZE(algs_sha1_md5),
1869         },
1870         {
1871                 .algs_list      = algs_sha224_sha256,
1872                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1873         },
1874         {
1875                 .algs_list      = algs_sha384_sha512,
1876                 .size           = ARRAY_SIZE(algs_sha384_sha512),
1877         },
1878 };
1879
1880 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1881         .algs_info      = omap_sham_algs_info_omap5,
1882         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1883         .flags          = BIT(FLAGS_AUTO_XOR),
1884         .digest_size    = SHA512_DIGEST_SIZE,
1885         .copy_hash      = omap_sham_copy_hash_omap4,
1886         .write_ctrl     = omap_sham_write_ctrl_omap4,
1887         .trigger        = omap_sham_trigger_omap4,
1888         .poll_irq       = omap_sham_poll_irq_omap4,
1889         .intr_hdlr      = omap_sham_irq_omap4,
1890         .idigest_ofs    = 0x240,
1891         .odigest_ofs    = 0x200,
1892         .din_ofs        = 0x080,
1893         .digcnt_ofs     = 0x280,
1894         .rev_ofs        = 0x100,
1895         .mask_ofs       = 0x110,
1896         .sysstatus_ofs  = 0x114,
1897         .mode_ofs       = 0x284,
1898         .length_ofs     = 0x288,
1899         .major_mask     = 0x0700,
1900         .major_shift    = 8,
1901         .minor_mask     = 0x003f,
1902         .minor_shift    = 0,
1903 };
1904
1905 static const struct of_device_id omap_sham_of_match[] = {
1906         {
1907                 .compatible     = "ti,omap2-sham",
1908                 .data           = &omap_sham_pdata_omap2,
1909         },
1910         {
1911                 .compatible     = "ti,omap3-sham",
1912                 .data           = &omap_sham_pdata_omap2,
1913         },
1914         {
1915                 .compatible     = "ti,omap4-sham",
1916                 .data           = &omap_sham_pdata_omap4,
1917         },
1918         {
1919                 .compatible     = "ti,omap5-sham",
1920                 .data           = &omap_sham_pdata_omap5,
1921         },
1922         {},
1923 };
1924 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1925
1926 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1927                 struct device *dev, struct resource *res)
1928 {
1929         struct device_node *node = dev->of_node;
1930         int err = 0;
1931
1932         dd->pdata = of_device_get_match_data(dev);
1933         if (!dd->pdata) {
1934                 dev_err(dev, "no compatible OF match\n");
1935                 err = -EINVAL;
1936                 goto err;
1937         }
1938
1939         err = of_address_to_resource(node, 0, res);
1940         if (err < 0) {
1941                 dev_err(dev, "can't translate OF node address\n");
1942                 err = -EINVAL;
1943                 goto err;
1944         }
1945
1946         dd->irq = irq_of_parse_and_map(node, 0);
1947         if (!dd->irq) {
1948                 dev_err(dev, "can't translate OF irq value\n");
1949                 err = -EINVAL;
1950                 goto err;
1951         }
1952
1953 err:
1954         return err;
1955 }
1956 #else
1957 static const struct of_device_id omap_sham_of_match[] = {
1958         {},
1959 };
1960
1961 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1962                 struct device *dev, struct resource *res)
1963 {
1964         return -EINVAL;
1965 }
1966 #endif
1967
1968 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1969                 struct platform_device *pdev, struct resource *res)
1970 {
1971         struct device *dev = &pdev->dev;
1972         struct resource *r;
1973         int err = 0;
1974
1975         /* Get the base address */
1976         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1977         if (!r) {
1978                 dev_err(dev, "no MEM resource info\n");
1979                 err = -ENODEV;
1980                 goto err;
1981         }
1982         memcpy(res, r, sizeof(*res));
1983
1984         /* Get the IRQ */
1985         dd->irq = platform_get_irq(pdev, 0);
1986         if (dd->irq < 0) {
1987                 err = dd->irq;
1988                 goto err;
1989         }
1990
1991         /* Only OMAP2/3 can be non-DT */
1992         dd->pdata = &omap_sham_pdata_omap2;
1993
1994 err:
1995         return err;
1996 }
1997
1998 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
1999                              char *buf)
2000 {
2001         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2002
2003         return sprintf(buf, "%d\n", dd->fallback_sz);
2004 }
2005
2006 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
2007                               const char *buf, size_t size)
2008 {
2009         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2010         ssize_t status;
2011         long value;
2012
2013         status = kstrtol(buf, 0, &value);
2014         if (status)
2015                 return status;
2016
2017         /* HW accelerator only works with buffers > 9 */
2018         if (value < 9) {
2019                 dev_err(dev, "minimum fallback size 9\n");
2020                 return -EINVAL;
2021         }
2022
2023         dd->fallback_sz = value;
2024
2025         return size;
2026 }
2027
2028 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
2029                               char *buf)
2030 {
2031         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2032
2033         return sprintf(buf, "%d\n", dd->queue.max_qlen);
2034 }
2035
2036 static ssize_t queue_len_store(struct device *dev,
2037                                struct device_attribute *attr, const char *buf,
2038                                size_t size)
2039 {
2040         struct omap_sham_dev *dd = dev_get_drvdata(dev);
2041         ssize_t status;
2042         long value;
2043         unsigned long flags;
2044
2045         status = kstrtol(buf, 0, &value);
2046         if (status)
2047                 return status;
2048
2049         if (value < 1)
2050                 return -EINVAL;
2051
2052         /*
2053          * Changing the queue size in fly is safe, if size becomes smaller
2054          * than current size, it will just not accept new entries until
2055          * it has shrank enough.
2056          */
2057         spin_lock_irqsave(&dd->lock, flags);
2058         dd->queue.max_qlen = value;
2059         spin_unlock_irqrestore(&dd->lock, flags);
2060
2061         return size;
2062 }
2063
2064 static DEVICE_ATTR_RW(queue_len);
2065 static DEVICE_ATTR_RW(fallback);
2066
2067 static struct attribute *omap_sham_attrs[] = {
2068         &dev_attr_queue_len.attr,
2069         &dev_attr_fallback.attr,
2070         NULL,
2071 };
2072
2073 static struct attribute_group omap_sham_attr_group = {
2074         .attrs = omap_sham_attrs,
2075 };
2076
2077 static int omap_sham_probe(struct platform_device *pdev)
2078 {
2079         struct omap_sham_dev *dd;
2080         struct device *dev = &pdev->dev;
2081         struct resource res;
2082         dma_cap_mask_t mask;
2083         int err, i, j;
2084         u32 rev;
2085
2086         dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2087         if (dd == NULL) {
2088                 dev_err(dev, "unable to alloc data struct.\n");
2089                 err = -ENOMEM;
2090                 goto data_err;
2091         }
2092         dd->dev = dev;
2093         platform_set_drvdata(pdev, dd);
2094
2095         INIT_LIST_HEAD(&dd->list);
2096         spin_lock_init(&dd->lock);
2097         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2098         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2099
2100         err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2101                                omap_sham_get_res_pdev(dd, pdev, &res);
2102         if (err)
2103                 goto data_err;
2104
2105         dd->io_base = devm_ioremap_resource(dev, &res);
2106         if (IS_ERR(dd->io_base)) {
2107                 err = PTR_ERR(dd->io_base);
2108                 goto data_err;
2109         }
2110         dd->phys_base = res.start;
2111
2112         err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2113                                IRQF_TRIGGER_NONE, dev_name(dev), dd);
2114         if (err) {
2115                 dev_err(dev, "unable to request irq %d, err = %d\n",
2116                         dd->irq, err);
2117                 goto data_err;
2118         }
2119
2120         dma_cap_zero(mask);
2121         dma_cap_set(DMA_SLAVE, mask);
2122
2123         dd->dma_lch = dma_request_chan(dev, "rx");
2124         if (IS_ERR(dd->dma_lch)) {
2125                 err = PTR_ERR(dd->dma_lch);
2126                 if (err == -EPROBE_DEFER)
2127                         goto data_err;
2128
2129                 dd->polling_mode = 1;
2130                 dev_dbg(dev, "using polling mode instead of dma\n");
2131         }
2132
2133         dd->flags |= dd->pdata->flags;
2134         sham.flags |= dd->pdata->flags;
2135
2136         pm_runtime_use_autosuspend(dev);
2137         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2138
2139         dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD;
2140
2141         pm_runtime_enable(dev);
2142         pm_runtime_irq_safe(dev);
2143
2144         err = pm_runtime_resume_and_get(dev);
2145         if (err < 0) {
2146                 dev_err(dev, "failed to get sync: %d\n", err);
2147                 goto err_pm;
2148         }
2149
2150         rev = omap_sham_read(dd, SHA_REG_REV(dd));
2151         pm_runtime_put_sync(&pdev->dev);
2152
2153         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2154                 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2155                 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2156
2157         spin_lock(&sham.lock);
2158         list_add_tail(&dd->list, &sham.dev_list);
2159         spin_unlock(&sham.lock);
2160
2161         for (i = 0; i < dd->pdata->algs_info_size; i++) {
2162                 if (dd->pdata->algs_info[i].registered)
2163                         break;
2164
2165                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2166                         struct ahash_alg *alg;
2167
2168                         alg = &dd->pdata->algs_info[i].algs_list[j];
2169                         alg->export = omap_sham_export;
2170                         alg->import = omap_sham_import;
2171                         alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2172                                               BUFLEN;
2173                         err = crypto_register_ahash(alg);
2174                         if (err)
2175                                 goto err_algs;
2176
2177                         dd->pdata->algs_info[i].registered++;
2178                 }
2179         }
2180
2181         err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group);
2182         if (err) {
2183                 dev_err(dev, "could not create sysfs device attrs\n");
2184                 goto err_algs;
2185         }
2186
2187         return 0;
2188
2189 err_algs:
2190         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2191                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2192                         crypto_unregister_ahash(
2193                                         &dd->pdata->algs_info[i].algs_list[j]);
2194 err_pm:
2195         pm_runtime_disable(dev);
2196         if (!dd->polling_mode)
2197                 dma_release_channel(dd->dma_lch);
2198 data_err:
2199         dev_err(dev, "initialization failed.\n");
2200
2201         return err;
2202 }
2203
2204 static int omap_sham_remove(struct platform_device *pdev)
2205 {
2206         struct omap_sham_dev *dd;
2207         int i, j;
2208
2209         dd = platform_get_drvdata(pdev);
2210         if (!dd)
2211                 return -ENODEV;
2212         spin_lock(&sham.lock);
2213         list_del(&dd->list);
2214         spin_unlock(&sham.lock);
2215         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2216                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
2217                         crypto_unregister_ahash(
2218                                         &dd->pdata->algs_info[i].algs_list[j]);
2219                         dd->pdata->algs_info[i].registered--;
2220                 }
2221         tasklet_kill(&dd->done_task);
2222         pm_runtime_disable(&pdev->dev);
2223
2224         if (!dd->polling_mode)
2225                 dma_release_channel(dd->dma_lch);
2226
2227         return 0;
2228 }
2229
2230 #ifdef CONFIG_PM_SLEEP
2231 static int omap_sham_suspend(struct device *dev)
2232 {
2233         pm_runtime_put_sync(dev);
2234         return 0;
2235 }
2236
2237 static int omap_sham_resume(struct device *dev)
2238 {
2239         int err = pm_runtime_resume_and_get(dev);
2240         if (err < 0) {
2241                 dev_err(dev, "failed to get sync: %d\n", err);
2242                 return err;
2243         }
2244         return 0;
2245 }
2246 #endif
2247
2248 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2249
2250 static struct platform_driver omap_sham_driver = {
2251         .probe  = omap_sham_probe,
2252         .remove = omap_sham_remove,
2253         .driver = {
2254                 .name   = "omap-sham",
2255                 .pm     = &omap_sham_pm_ops,
2256                 .of_match_table = omap_sham_of_match,
2257         },
2258 };
2259
2260 module_platform_driver(omap_sham_driver);
2261
2262 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2263 MODULE_LICENSE("GPL v2");
2264 MODULE_AUTHOR("Dmitry Kasatkin");
2265 MODULE_ALIAS("platform:omap-sham");