GNU Linux-libre 4.4.300-gnu1
[releases.git] / drivers / crypto / omap-sham.c
1 /*
2  * Cryptographic API.
3  *
4  * Support for OMAP SHA1/MD5 HW acceleration.
5  *
6  * Copyright (c) 2010 Nokia Corporation
7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
8  * Copyright (c) 2011 Texas Instruments Incorporated
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as published
12  * by the Free Software Foundation.
13  *
14  * Some ideas are from old omap-sha1-md5.c driver.
15  */
16
17 #define pr_fmt(fmt) "%s: " fmt, __func__
18
19 #include <linux/err.h>
20 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/irq.h>
27 #include <linux/io.h>
28 #include <linux/platform_device.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/omap-dma.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/of.h>
35 #include <linux/of_device.h>
36 #include <linux/of_address.h>
37 #include <linux/of_irq.h>
38 #include <linux/delay.h>
39 #include <linux/crypto.h>
40 #include <linux/cryptohash.h>
41 #include <crypto/scatterwalk.h>
42 #include <crypto/algapi.h>
43 #include <crypto/sha.h>
44 #include <crypto/hash.h>
45 #include <crypto/internal/hash.h>
46
47 #define MD5_DIGEST_SIZE                 16
48
49 #define SHA_REG_IDIGEST(dd, x)          ((dd)->pdata->idigest_ofs + ((x)*0x04))
50 #define SHA_REG_DIN(dd, x)              ((dd)->pdata->din_ofs + ((x) * 0x04))
51 #define SHA_REG_DIGCNT(dd)              ((dd)->pdata->digcnt_ofs)
52
53 #define SHA_REG_ODIGEST(dd, x)          ((dd)->pdata->odigest_ofs + (x * 0x04))
54
55 #define SHA_REG_CTRL                    0x18
56 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
57 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
58 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
59 #define SHA_REG_CTRL_ALGO               (1 << 2)
60 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
61 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
62
63 #define SHA_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
64
65 #define SHA_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
66 #define SHA_REG_MASK_DMA_EN             (1 << 3)
67 #define SHA_REG_MASK_IT_EN              (1 << 2)
68 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
69 #define SHA_REG_AUTOIDLE                (1 << 0)
70
71 #define SHA_REG_SYSSTATUS(dd)           ((dd)->pdata->sysstatus_ofs)
72 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
73
74 #define SHA_REG_MODE(dd)                ((dd)->pdata->mode_ofs)
75 #define SHA_REG_MODE_HMAC_OUTER_HASH    (1 << 7)
76 #define SHA_REG_MODE_HMAC_KEY_PROC      (1 << 5)
77 #define SHA_REG_MODE_CLOSE_HASH         (1 << 4)
78 #define SHA_REG_MODE_ALGO_CONSTANT      (1 << 3)
79
80 #define SHA_REG_MODE_ALGO_MASK          (7 << 0)
81 #define SHA_REG_MODE_ALGO_MD5_128       (0 << 1)
82 #define SHA_REG_MODE_ALGO_SHA1_160      (1 << 1)
83 #define SHA_REG_MODE_ALGO_SHA2_224      (2 << 1)
84 #define SHA_REG_MODE_ALGO_SHA2_256      (3 << 1)
85 #define SHA_REG_MODE_ALGO_SHA2_384      (1 << 0)
86 #define SHA_REG_MODE_ALGO_SHA2_512      (3 << 0)
87
88 #define SHA_REG_LENGTH(dd)              ((dd)->pdata->length_ofs)
89
90 #define SHA_REG_IRQSTATUS               0x118
91 #define SHA_REG_IRQSTATUS_CTX_RDY       (1 << 3)
92 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
93 #define SHA_REG_IRQSTATUS_INPUT_RDY     (1 << 1)
94 #define SHA_REG_IRQSTATUS_OUTPUT_RDY    (1 << 0)
95
96 #define SHA_REG_IRQENA                  0x11C
97 #define SHA_REG_IRQENA_CTX_RDY          (1 << 3)
98 #define SHA_REG_IRQENA_PARTHASH_RDY     (1 << 2)
99 #define SHA_REG_IRQENA_INPUT_RDY        (1 << 1)
100 #define SHA_REG_IRQENA_OUTPUT_RDY       (1 << 0)
101
102 #define DEFAULT_TIMEOUT_INTERVAL        HZ
103
104 /* mostly device flags */
105 #define FLAGS_BUSY              0
106 #define FLAGS_FINAL             1
107 #define FLAGS_DMA_ACTIVE        2
108 #define FLAGS_OUTPUT_READY      3
109 #define FLAGS_INIT              4
110 #define FLAGS_CPU               5
111 #define FLAGS_DMA_READY         6
112 #define FLAGS_AUTO_XOR          7
113 #define FLAGS_BE32_SHA1         8
114 /* context flags */
115 #define FLAGS_FINUP             16
116 #define FLAGS_SG                17
117
118 #define FLAGS_MODE_SHIFT        18
119 #define FLAGS_MODE_MASK         (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
120 #define FLAGS_MODE_MD5          (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
121 #define FLAGS_MODE_SHA1         (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
122 #define FLAGS_MODE_SHA224       (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
123 #define FLAGS_MODE_SHA256       (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
124 #define FLAGS_MODE_SHA384       (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
125 #define FLAGS_MODE_SHA512       (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
126
127 #define FLAGS_HMAC              21
128 #define FLAGS_ERROR             22
129
130 #define OP_UPDATE               1
131 #define OP_FINAL                2
132
133 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
134 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
135
136 #define BUFLEN                  PAGE_SIZE
137
138 struct omap_sham_dev;
139
140 struct omap_sham_reqctx {
141         struct omap_sham_dev    *dd;
142         unsigned long           flags;
143         unsigned long           op;
144
145         u8                      digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
146         size_t                  digcnt;
147         size_t                  bufcnt;
148         size_t                  buflen;
149         dma_addr_t              dma_addr;
150
151         /* walk state */
152         struct scatterlist      *sg;
153         struct scatterlist      sgl;
154         unsigned int            offset; /* offset in current sg */
155         unsigned int            total;  /* total request */
156
157         u8                      buffer[0] OMAP_ALIGNED;
158 };
159
160 struct omap_sham_hmac_ctx {
161         struct crypto_shash     *shash;
162         u8                      ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
163         u8                      opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
164 };
165
166 struct omap_sham_ctx {
167         struct omap_sham_dev    *dd;
168
169         unsigned long           flags;
170
171         /* fallback stuff */
172         struct crypto_shash     *fallback;
173
174         struct omap_sham_hmac_ctx base[0];
175 };
176
177 #define OMAP_SHAM_QUEUE_LENGTH  1
178
179 struct omap_sham_algs_info {
180         struct ahash_alg        *algs_list;
181         unsigned int            size;
182         unsigned int            registered;
183 };
184
185 struct omap_sham_pdata {
186         struct omap_sham_algs_info      *algs_info;
187         unsigned int    algs_info_size;
188         unsigned long   flags;
189         int             digest_size;
190
191         void            (*copy_hash)(struct ahash_request *req, int out);
192         void            (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
193                                       int final, int dma);
194         void            (*trigger)(struct omap_sham_dev *dd, size_t length);
195         int             (*poll_irq)(struct omap_sham_dev *dd);
196         irqreturn_t     (*intr_hdlr)(int irq, void *dev_id);
197
198         u32             odigest_ofs;
199         u32             idigest_ofs;
200         u32             din_ofs;
201         u32             digcnt_ofs;
202         u32             rev_ofs;
203         u32             mask_ofs;
204         u32             sysstatus_ofs;
205         u32             mode_ofs;
206         u32             length_ofs;
207
208         u32             major_mask;
209         u32             major_shift;
210         u32             minor_mask;
211         u32             minor_shift;
212 };
213
214 struct omap_sham_dev {
215         struct list_head        list;
216         unsigned long           phys_base;
217         struct device           *dev;
218         void __iomem            *io_base;
219         int                     irq;
220         spinlock_t              lock;
221         int                     err;
222         unsigned int            dma;
223         struct dma_chan         *dma_lch;
224         struct tasklet_struct   done_task;
225         u8                      polling_mode;
226
227         unsigned long           flags;
228         struct crypto_queue     queue;
229         struct ahash_request    *req;
230
231         const struct omap_sham_pdata    *pdata;
232 };
233
234 struct omap_sham_drv {
235         struct list_head        dev_list;
236         spinlock_t              lock;
237         unsigned long           flags;
238 };
239
240 static struct omap_sham_drv sham = {
241         .dev_list = LIST_HEAD_INIT(sham.dev_list),
242         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
243 };
244
245 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
246 {
247         return __raw_readl(dd->io_base + offset);
248 }
249
250 static inline void omap_sham_write(struct omap_sham_dev *dd,
251                                         u32 offset, u32 value)
252 {
253         __raw_writel(value, dd->io_base + offset);
254 }
255
256 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
257                                         u32 value, u32 mask)
258 {
259         u32 val;
260
261         val = omap_sham_read(dd, address);
262         val &= ~mask;
263         val |= value;
264         omap_sham_write(dd, address, val);
265 }
266
267 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
268 {
269         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
270
271         while (!(omap_sham_read(dd, offset) & bit)) {
272                 if (time_is_before_jiffies(timeout))
273                         return -ETIMEDOUT;
274         }
275
276         return 0;
277 }
278
279 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
280 {
281         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
282         struct omap_sham_dev *dd = ctx->dd;
283         u32 *hash = (u32 *)ctx->digest;
284         int i;
285
286         for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
287                 if (out)
288                         hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
289                 else
290                         omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
291         }
292 }
293
294 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
295 {
296         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
297         struct omap_sham_dev *dd = ctx->dd;
298         int i;
299
300         if (ctx->flags & BIT(FLAGS_HMAC)) {
301                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
302                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
303                 struct omap_sham_hmac_ctx *bctx = tctx->base;
304                 u32 *opad = (u32 *)bctx->opad;
305
306                 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
307                         if (out)
308                                 opad[i] = omap_sham_read(dd,
309                                                 SHA_REG_ODIGEST(dd, i));
310                         else
311                                 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
312                                                 opad[i]);
313                 }
314         }
315
316         omap_sham_copy_hash_omap2(req, out);
317 }
318
319 static void omap_sham_copy_ready_hash(struct ahash_request *req)
320 {
321         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
322         u32 *in = (u32 *)ctx->digest;
323         u32 *hash = (u32 *)req->result;
324         int i, d, big_endian = 0;
325
326         if (!hash)
327                 return;
328
329         switch (ctx->flags & FLAGS_MODE_MASK) {
330         case FLAGS_MODE_MD5:
331                 d = MD5_DIGEST_SIZE / sizeof(u32);
332                 break;
333         case FLAGS_MODE_SHA1:
334                 /* OMAP2 SHA1 is big endian */
335                 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
336                         big_endian = 1;
337                 d = SHA1_DIGEST_SIZE / sizeof(u32);
338                 break;
339         case FLAGS_MODE_SHA224:
340                 d = SHA224_DIGEST_SIZE / sizeof(u32);
341                 break;
342         case FLAGS_MODE_SHA256:
343                 d = SHA256_DIGEST_SIZE / sizeof(u32);
344                 break;
345         case FLAGS_MODE_SHA384:
346                 d = SHA384_DIGEST_SIZE / sizeof(u32);
347                 break;
348         case FLAGS_MODE_SHA512:
349                 d = SHA512_DIGEST_SIZE / sizeof(u32);
350                 break;
351         default:
352                 d = 0;
353         }
354
355         if (big_endian)
356                 for (i = 0; i < d; i++)
357                         hash[i] = be32_to_cpu(in[i]);
358         else
359                 for (i = 0; i < d; i++)
360                         hash[i] = le32_to_cpu(in[i]);
361 }
362
363 static int omap_sham_hw_init(struct omap_sham_dev *dd)
364 {
365         int err;
366
367         err = pm_runtime_get_sync(dd->dev);
368         if (err < 0) {
369                 dev_err(dd->dev, "failed to get sync: %d\n", err);
370                 return err;
371         }
372
373         if (!test_bit(FLAGS_INIT, &dd->flags)) {
374                 set_bit(FLAGS_INIT, &dd->flags);
375                 dd->err = 0;
376         }
377
378         return 0;
379 }
380
381 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
382                                  int final, int dma)
383 {
384         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
385         u32 val = length << 5, mask;
386
387         if (likely(ctx->digcnt))
388                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
389
390         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
391                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
392                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
393         /*
394          * Setting ALGO_CONST only for the first iteration
395          * and CLOSE_HASH only for the last one.
396          */
397         if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
398                 val |= SHA_REG_CTRL_ALGO;
399         if (!ctx->digcnt)
400                 val |= SHA_REG_CTRL_ALGO_CONST;
401         if (final)
402                 val |= SHA_REG_CTRL_CLOSE_HASH;
403
404         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
405                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
406
407         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
408 }
409
410 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
411 {
412 }
413
414 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
415 {
416         return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
417 }
418
419 static int get_block_size(struct omap_sham_reqctx *ctx)
420 {
421         int d;
422
423         switch (ctx->flags & FLAGS_MODE_MASK) {
424         case FLAGS_MODE_MD5:
425         case FLAGS_MODE_SHA1:
426                 d = SHA1_BLOCK_SIZE;
427                 break;
428         case FLAGS_MODE_SHA224:
429         case FLAGS_MODE_SHA256:
430                 d = SHA256_BLOCK_SIZE;
431                 break;
432         case FLAGS_MODE_SHA384:
433         case FLAGS_MODE_SHA512:
434                 d = SHA512_BLOCK_SIZE;
435                 break;
436         default:
437                 d = 0;
438         }
439
440         return d;
441 }
442
443 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
444                                     u32 *value, int count)
445 {
446         for (; count--; value++, offset += 4)
447                 omap_sham_write(dd, offset, *value);
448 }
449
450 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
451                                  int final, int dma)
452 {
453         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
454         u32 val, mask;
455
456         if (likely(ctx->digcnt))
457                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
458
459         /*
460          * Setting ALGO_CONST only for the first iteration and
461          * CLOSE_HASH only for the last one. Note that flags mode bits
462          * correspond to algorithm encoding in mode register.
463          */
464         val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
465         if (!ctx->digcnt) {
466                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
467                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
468                 struct omap_sham_hmac_ctx *bctx = tctx->base;
469                 int bs, nr_dr;
470
471                 val |= SHA_REG_MODE_ALGO_CONSTANT;
472
473                 if (ctx->flags & BIT(FLAGS_HMAC)) {
474                         bs = get_block_size(ctx);
475                         nr_dr = bs / (2 * sizeof(u32));
476                         val |= SHA_REG_MODE_HMAC_KEY_PROC;
477                         omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
478                                           (u32 *)bctx->ipad, nr_dr);
479                         omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
480                                           (u32 *)bctx->ipad + nr_dr, nr_dr);
481                         ctx->digcnt += bs;
482                 }
483         }
484
485         if (final) {
486                 val |= SHA_REG_MODE_CLOSE_HASH;
487
488                 if (ctx->flags & BIT(FLAGS_HMAC))
489                         val |= SHA_REG_MODE_HMAC_OUTER_HASH;
490         }
491
492         mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
493                SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
494                SHA_REG_MODE_HMAC_KEY_PROC;
495
496         dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
497         omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
498         omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
499         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
500                              SHA_REG_MASK_IT_EN |
501                                      (dma ? SHA_REG_MASK_DMA_EN : 0),
502                              SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
503 }
504
505 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
506 {
507         omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
508 }
509
510 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
511 {
512         return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
513                               SHA_REG_IRQSTATUS_INPUT_RDY);
514 }
515
516 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
517                               size_t length, int final)
518 {
519         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
520         int count, len32, bs32, offset = 0;
521         const u32 *buffer = (const u32 *)buf;
522
523         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
524                                                 ctx->digcnt, length, final);
525
526         dd->pdata->write_ctrl(dd, length, final, 0);
527         dd->pdata->trigger(dd, length);
528
529         /* should be non-zero before next lines to disable clocks later */
530         ctx->digcnt += length;
531
532         if (final)
533                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
534
535         set_bit(FLAGS_CPU, &dd->flags);
536
537         len32 = DIV_ROUND_UP(length, sizeof(u32));
538         bs32 = get_block_size(ctx) / sizeof(u32);
539
540         while (len32) {
541                 if (dd->pdata->poll_irq(dd))
542                         return -ETIMEDOUT;
543
544                 for (count = 0; count < min(len32, bs32); count++, offset++)
545                         omap_sham_write(dd, SHA_REG_DIN(dd, count),
546                                         buffer[offset]);
547                 len32 -= min(len32, bs32);
548         }
549
550         return -EINPROGRESS;
551 }
552
553 static void omap_sham_dma_callback(void *param)
554 {
555         struct omap_sham_dev *dd = param;
556
557         set_bit(FLAGS_DMA_READY, &dd->flags);
558         tasklet_schedule(&dd->done_task);
559 }
560
561 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
562                               size_t length, int final, int is_sg)
563 {
564         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
565         struct dma_async_tx_descriptor *tx;
566         struct dma_slave_config cfg;
567         int len32, ret, dma_min = get_block_size(ctx);
568
569         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
570                                                 ctx->digcnt, length, final);
571
572         memset(&cfg, 0, sizeof(cfg));
573
574         cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
575         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
576         cfg.dst_maxburst = dma_min / DMA_SLAVE_BUSWIDTH_4_BYTES;
577
578         ret = dmaengine_slave_config(dd->dma_lch, &cfg);
579         if (ret) {
580                 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
581                 return ret;
582         }
583
584         len32 = DIV_ROUND_UP(length, dma_min) * dma_min;
585
586         if (is_sg) {
587                 /*
588                  * The SG entry passed in may not have the 'length' member
589                  * set correctly so use a local SG entry (sgl) with the
590                  * proper value for 'length' instead.  If this is not done,
591                  * the dmaengine may try to DMA the incorrect amount of data.
592                  */
593                 sg_init_table(&ctx->sgl, 1);
594                 sg_assign_page(&ctx->sgl, sg_page(ctx->sg));
595                 ctx->sgl.offset = ctx->sg->offset;
596                 sg_dma_len(&ctx->sgl) = len32;
597                 sg_dma_address(&ctx->sgl) = sg_dma_address(ctx->sg);
598
599                 tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl, 1,
600                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
601         } else {
602                 tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32,
603                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
604         }
605
606         if (!tx) {
607                 dev_err(dd->dev, "prep_slave_sg/single() failed\n");
608                 return -EINVAL;
609         }
610
611         tx->callback = omap_sham_dma_callback;
612         tx->callback_param = dd;
613
614         dd->pdata->write_ctrl(dd, length, final, 1);
615
616         ctx->digcnt += length;
617
618         if (final)
619                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
620
621         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
622
623         dmaengine_submit(tx);
624         dma_async_issue_pending(dd->dma_lch);
625
626         dd->pdata->trigger(dd, length);
627
628         return -EINPROGRESS;
629 }
630
631 static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
632                                 const u8 *data, size_t length)
633 {
634         size_t count = min(length, ctx->buflen - ctx->bufcnt);
635
636         count = min(count, ctx->total);
637         if (count <= 0)
638                 return 0;
639         memcpy(ctx->buffer + ctx->bufcnt, data, count);
640         ctx->bufcnt += count;
641
642         return count;
643 }
644
645 static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
646 {
647         size_t count;
648         const u8 *vaddr;
649
650         while (ctx->sg) {
651                 vaddr = kmap_atomic(sg_page(ctx->sg));
652                 vaddr += ctx->sg->offset;
653
654                 count = omap_sham_append_buffer(ctx,
655                                 vaddr + ctx->offset,
656                                 ctx->sg->length - ctx->offset);
657
658                 kunmap_atomic((void *)vaddr);
659
660                 if (!count)
661                         break;
662                 ctx->offset += count;
663                 ctx->total -= count;
664                 if (ctx->offset == ctx->sg->length) {
665                         ctx->sg = sg_next(ctx->sg);
666                         if (ctx->sg)
667                                 ctx->offset = 0;
668                         else
669                                 ctx->total = 0;
670                 }
671         }
672
673         return 0;
674 }
675
676 static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
677                                         struct omap_sham_reqctx *ctx,
678                                         size_t length, int final)
679 {
680         int ret;
681
682         ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
683                                        DMA_TO_DEVICE);
684         if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
685                 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
686                 return -EINVAL;
687         }
688
689         ctx->flags &= ~BIT(FLAGS_SG);
690
691         ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0);
692         if (ret != -EINPROGRESS)
693                 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
694                                  DMA_TO_DEVICE);
695
696         return ret;
697 }
698
699 static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
700 {
701         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
702         unsigned int final;
703         size_t count;
704
705         omap_sham_append_sg(ctx);
706
707         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
708
709         dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
710                                          ctx->bufcnt, ctx->digcnt, final);
711
712         if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
713                 count = ctx->bufcnt;
714                 ctx->bufcnt = 0;
715                 return omap_sham_xmit_dma_map(dd, ctx, count, final);
716         }
717
718         return 0;
719 }
720
721 /* Start address alignment */
722 #define SG_AA(sg)       (IS_ALIGNED(sg->offset, sizeof(u32)))
723 /* SHA1 block size alignment */
724 #define SG_SA(sg, bs)   (IS_ALIGNED(sg->length, bs))
725
726 static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
727 {
728         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
729         unsigned int length, final, tail;
730         struct scatterlist *sg;
731         int ret, bs;
732
733         if (!ctx->total)
734                 return 0;
735
736         if (ctx->bufcnt || ctx->offset)
737                 return omap_sham_update_dma_slow(dd);
738
739         /*
740          * Don't use the sg interface when the transfer size is less
741          * than the number of elements in a DMA frame.  Otherwise,
742          * the dmaengine infrastructure will calculate that it needs
743          * to transfer 0 frames which ultimately fails.
744          */
745         if (ctx->total < get_block_size(ctx))
746                 return omap_sham_update_dma_slow(dd);
747
748         dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
749                         ctx->digcnt, ctx->bufcnt, ctx->total);
750
751         sg = ctx->sg;
752         bs = get_block_size(ctx);
753
754         if (!SG_AA(sg))
755                 return omap_sham_update_dma_slow(dd);
756
757         if (!sg_is_last(sg) && !SG_SA(sg, bs))
758                 /* size is not BLOCK_SIZE aligned */
759                 return omap_sham_update_dma_slow(dd);
760
761         length = min(ctx->total, sg->length);
762
763         if (sg_is_last(sg)) {
764                 if (!(ctx->flags & BIT(FLAGS_FINUP))) {
765                         /* not last sg must be BLOCK_SIZE aligned */
766                         tail = length & (bs - 1);
767                         /* without finup() we need one block to close hash */
768                         if (!tail)
769                                 tail = bs;
770                         length -= tail;
771                 }
772         }
773
774         if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
775                 dev_err(dd->dev, "dma_map_sg  error\n");
776                 return -EINVAL;
777         }
778
779         ctx->flags |= BIT(FLAGS_SG);
780
781         ctx->total -= length;
782         ctx->offset = length; /* offset where to start slow */
783
784         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
785
786         ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1);
787         if (ret != -EINPROGRESS)
788                 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
789
790         return ret;
791 }
792
793 static int omap_sham_update_cpu(struct omap_sham_dev *dd)
794 {
795         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
796         int bufcnt, final;
797
798         if (!ctx->total)
799                 return 0;
800
801         omap_sham_append_sg(ctx);
802
803         final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
804
805         dev_dbg(dd->dev, "cpu: bufcnt: %u, digcnt: %d, final: %d\n",
806                 ctx->bufcnt, ctx->digcnt, final);
807
808         if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
809                 bufcnt = ctx->bufcnt;
810                 ctx->bufcnt = 0;
811                 return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, final);
812         }
813
814         return 0;
815 }
816
817 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
818 {
819         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
820
821         dmaengine_terminate_all(dd->dma_lch);
822
823         if (ctx->flags & BIT(FLAGS_SG)) {
824                 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
825                 if (ctx->sg->length == ctx->offset) {
826                         ctx->sg = sg_next(ctx->sg);
827                         if (ctx->sg)
828                                 ctx->offset = 0;
829                 }
830         } else {
831                 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
832                                  DMA_TO_DEVICE);
833         }
834
835         return 0;
836 }
837
838 static int omap_sham_init(struct ahash_request *req)
839 {
840         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
841         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
842         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
843         struct omap_sham_dev *dd = NULL, *tmp;
844         int bs = 0;
845
846         spin_lock_bh(&sham.lock);
847         if (!tctx->dd) {
848                 list_for_each_entry(tmp, &sham.dev_list, list) {
849                         dd = tmp;
850                         break;
851                 }
852                 tctx->dd = dd;
853         } else {
854                 dd = tctx->dd;
855         }
856         spin_unlock_bh(&sham.lock);
857
858         ctx->dd = dd;
859
860         ctx->flags = 0;
861
862         dev_dbg(dd->dev, "init: digest size: %d\n",
863                 crypto_ahash_digestsize(tfm));
864
865         switch (crypto_ahash_digestsize(tfm)) {
866         case MD5_DIGEST_SIZE:
867                 ctx->flags |= FLAGS_MODE_MD5;
868                 bs = SHA1_BLOCK_SIZE;
869                 break;
870         case SHA1_DIGEST_SIZE:
871                 ctx->flags |= FLAGS_MODE_SHA1;
872                 bs = SHA1_BLOCK_SIZE;
873                 break;
874         case SHA224_DIGEST_SIZE:
875                 ctx->flags |= FLAGS_MODE_SHA224;
876                 bs = SHA224_BLOCK_SIZE;
877                 break;
878         case SHA256_DIGEST_SIZE:
879                 ctx->flags |= FLAGS_MODE_SHA256;
880                 bs = SHA256_BLOCK_SIZE;
881                 break;
882         case SHA384_DIGEST_SIZE:
883                 ctx->flags |= FLAGS_MODE_SHA384;
884                 bs = SHA384_BLOCK_SIZE;
885                 break;
886         case SHA512_DIGEST_SIZE:
887                 ctx->flags |= FLAGS_MODE_SHA512;
888                 bs = SHA512_BLOCK_SIZE;
889                 break;
890         }
891
892         ctx->bufcnt = 0;
893         ctx->digcnt = 0;
894         ctx->buflen = BUFLEN;
895
896         if (tctx->flags & BIT(FLAGS_HMAC)) {
897                 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
898                         struct omap_sham_hmac_ctx *bctx = tctx->base;
899
900                         memcpy(ctx->buffer, bctx->ipad, bs);
901                         ctx->bufcnt = bs;
902                 }
903
904                 ctx->flags |= BIT(FLAGS_HMAC);
905         }
906
907         return 0;
908
909 }
910
911 static int omap_sham_update_req(struct omap_sham_dev *dd)
912 {
913         struct ahash_request *req = dd->req;
914         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
915         int err;
916
917         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
918                  ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
919
920         if (ctx->flags & BIT(FLAGS_CPU))
921                 err = omap_sham_update_cpu(dd);
922         else
923                 err = omap_sham_update_dma_start(dd);
924
925         /* wait for dma completion before can take more data */
926         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
927
928         return err;
929 }
930
931 static int omap_sham_final_req(struct omap_sham_dev *dd)
932 {
933         struct ahash_request *req = dd->req;
934         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
935         int err = 0, use_dma = 1;
936
937         if ((ctx->bufcnt <= get_block_size(ctx)) || dd->polling_mode)
938                 /*
939                  * faster to handle last block with cpu or
940                  * use cpu when dma is not present.
941                  */
942                 use_dma = 0;
943
944         if (use_dma)
945                 err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
946         else
947                 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
948
949         ctx->bufcnt = 0;
950
951         dev_dbg(dd->dev, "final_req: err: %d\n", err);
952
953         return err;
954 }
955
956 static int omap_sham_finish_hmac(struct ahash_request *req)
957 {
958         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
959         struct omap_sham_hmac_ctx *bctx = tctx->base;
960         int bs = crypto_shash_blocksize(bctx->shash);
961         int ds = crypto_shash_digestsize(bctx->shash);
962         SHASH_DESC_ON_STACK(shash, bctx->shash);
963
964         shash->tfm = bctx->shash;
965         shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
966
967         return crypto_shash_init(shash) ?:
968                crypto_shash_update(shash, bctx->opad, bs) ?:
969                crypto_shash_finup(shash, req->result, ds, req->result);
970 }
971
972 static int omap_sham_finish(struct ahash_request *req)
973 {
974         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
975         struct omap_sham_dev *dd = ctx->dd;
976         int err = 0;
977
978         if (ctx->digcnt) {
979                 omap_sham_copy_ready_hash(req);
980                 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
981                                 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
982                         err = omap_sham_finish_hmac(req);
983         }
984
985         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
986
987         return err;
988 }
989
990 static void omap_sham_finish_req(struct ahash_request *req, int err)
991 {
992         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
993         struct omap_sham_dev *dd = ctx->dd;
994
995         if (!err) {
996                 dd->pdata->copy_hash(req, 1);
997                 if (test_bit(FLAGS_FINAL, &dd->flags))
998                         err = omap_sham_finish(req);
999         } else {
1000                 ctx->flags |= BIT(FLAGS_ERROR);
1001         }
1002
1003         /* atomic operation is not needed here */
1004         dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1005                         BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1006
1007         pm_runtime_put(dd->dev);
1008
1009         if (req->base.complete)
1010                 req->base.complete(&req->base, err);
1011
1012         /* handle new request */
1013         tasklet_schedule(&dd->done_task);
1014 }
1015
1016 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1017                                   struct ahash_request *req)
1018 {
1019         struct crypto_async_request *async_req, *backlog;
1020         struct omap_sham_reqctx *ctx;
1021         unsigned long flags;
1022         int err = 0, ret = 0;
1023
1024         spin_lock_irqsave(&dd->lock, flags);
1025         if (req)
1026                 ret = ahash_enqueue_request(&dd->queue, req);
1027         if (test_bit(FLAGS_BUSY, &dd->flags)) {
1028                 spin_unlock_irqrestore(&dd->lock, flags);
1029                 return ret;
1030         }
1031         backlog = crypto_get_backlog(&dd->queue);
1032         async_req = crypto_dequeue_request(&dd->queue);
1033         if (async_req)
1034                 set_bit(FLAGS_BUSY, &dd->flags);
1035         spin_unlock_irqrestore(&dd->lock, flags);
1036
1037         if (!async_req)
1038                 return ret;
1039
1040         if (backlog)
1041                 backlog->complete(backlog, -EINPROGRESS);
1042
1043         req = ahash_request_cast(async_req);
1044         dd->req = req;
1045         ctx = ahash_request_ctx(req);
1046
1047         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1048                                                 ctx->op, req->nbytes);
1049
1050         err = omap_sham_hw_init(dd);
1051         if (err)
1052                 goto err1;
1053
1054         if (ctx->digcnt)
1055                 /* request has changed - restore hash */
1056                 dd->pdata->copy_hash(req, 0);
1057
1058         if (ctx->op == OP_UPDATE) {
1059                 err = omap_sham_update_req(dd);
1060                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1061                         /* no final() after finup() */
1062                         err = omap_sham_final_req(dd);
1063         } else if (ctx->op == OP_FINAL) {
1064                 err = omap_sham_final_req(dd);
1065         }
1066 err1:
1067         if (err != -EINPROGRESS)
1068                 /* done_task will not finish it, so do it here */
1069                 omap_sham_finish_req(req, err);
1070
1071         dev_dbg(dd->dev, "exit, err: %d\n", err);
1072
1073         return ret;
1074 }
1075
1076 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1077 {
1078         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1079         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1080         struct omap_sham_dev *dd = tctx->dd;
1081
1082         ctx->op = op;
1083
1084         return omap_sham_handle_queue(dd, req);
1085 }
1086
1087 static int omap_sham_update(struct ahash_request *req)
1088 {
1089         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1090         struct omap_sham_dev *dd = ctx->dd;
1091         int bs = get_block_size(ctx);
1092
1093         if (!req->nbytes)
1094                 return 0;
1095
1096         ctx->total = req->nbytes;
1097         ctx->sg = req->src;
1098         ctx->offset = 0;
1099
1100         if (ctx->flags & BIT(FLAGS_FINUP)) {
1101                 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) {
1102                         /*
1103                         * OMAP HW accel works only with buffers >= 9
1104                         * will switch to bypass in final()
1105                         * final has the same request and data
1106                         */
1107                         omap_sham_append_sg(ctx);
1108                         return 0;
1109                 } else if ((ctx->bufcnt + ctx->total <= bs) ||
1110                            dd->polling_mode) {
1111                         /*
1112                          * faster to use CPU for short transfers or
1113                          * use cpu when dma is not present.
1114                          */
1115                         ctx->flags |= BIT(FLAGS_CPU);
1116                 }
1117         } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
1118                 omap_sham_append_sg(ctx);
1119                 return 0;
1120         }
1121
1122         if (dd->polling_mode)
1123                 ctx->flags |= BIT(FLAGS_CPU);
1124
1125         return omap_sham_enqueue(req, OP_UPDATE);
1126 }
1127
1128 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1129                                   const u8 *data, unsigned int len, u8 *out)
1130 {
1131         SHASH_DESC_ON_STACK(shash, tfm);
1132
1133         shash->tfm = tfm;
1134         shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1135
1136         return crypto_shash_digest(shash, data, len, out);
1137 }
1138
1139 static int omap_sham_final_shash(struct ahash_request *req)
1140 {
1141         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1142         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1143
1144         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1145                                       ctx->buffer, ctx->bufcnt, req->result);
1146 }
1147
1148 static int omap_sham_final(struct ahash_request *req)
1149 {
1150         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1151
1152         ctx->flags |= BIT(FLAGS_FINUP);
1153
1154         if (ctx->flags & BIT(FLAGS_ERROR))
1155                 return 0; /* uncompleted hash is not needed */
1156
1157         /* OMAP HW accel works only with buffers >= 9 */
1158         /* HMAC is always >= 9 because ipad == block size */
1159         if ((ctx->digcnt + ctx->bufcnt) < 9)
1160                 return omap_sham_final_shash(req);
1161         else if (ctx->bufcnt)
1162                 return omap_sham_enqueue(req, OP_FINAL);
1163
1164         /* copy ready hash (+ finalize hmac) */
1165         return omap_sham_finish(req);
1166 }
1167
1168 static int omap_sham_finup(struct ahash_request *req)
1169 {
1170         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1171         int err1, err2;
1172
1173         ctx->flags |= BIT(FLAGS_FINUP);
1174
1175         err1 = omap_sham_update(req);
1176         if (err1 == -EINPROGRESS || err1 == -EBUSY)
1177                 return err1;
1178         /*
1179          * final() has to be always called to cleanup resources
1180          * even if udpate() failed, except EINPROGRESS
1181          */
1182         err2 = omap_sham_final(req);
1183
1184         return err1 ?: err2;
1185 }
1186
1187 static int omap_sham_digest(struct ahash_request *req)
1188 {
1189         return omap_sham_init(req) ?: omap_sham_finup(req);
1190 }
1191
1192 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1193                       unsigned int keylen)
1194 {
1195         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1196         struct omap_sham_hmac_ctx *bctx = tctx->base;
1197         int bs = crypto_shash_blocksize(bctx->shash);
1198         int ds = crypto_shash_digestsize(bctx->shash);
1199         struct omap_sham_dev *dd = NULL, *tmp;
1200         int err, i;
1201
1202         spin_lock_bh(&sham.lock);
1203         if (!tctx->dd) {
1204                 list_for_each_entry(tmp, &sham.dev_list, list) {
1205                         dd = tmp;
1206                         break;
1207                 }
1208                 tctx->dd = dd;
1209         } else {
1210                 dd = tctx->dd;
1211         }
1212         spin_unlock_bh(&sham.lock);
1213
1214         err = crypto_shash_setkey(tctx->fallback, key, keylen);
1215         if (err)
1216                 return err;
1217
1218         if (keylen > bs) {
1219                 err = omap_sham_shash_digest(bctx->shash,
1220                                 crypto_shash_get_flags(bctx->shash),
1221                                 key, keylen, bctx->ipad);
1222                 if (err)
1223                         return err;
1224                 keylen = ds;
1225         } else {
1226                 memcpy(bctx->ipad, key, keylen);
1227         }
1228
1229         memset(bctx->ipad + keylen, 0, bs - keylen);
1230
1231         if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1232                 memcpy(bctx->opad, bctx->ipad, bs);
1233
1234                 for (i = 0; i < bs; i++) {
1235                         bctx->ipad[i] ^= 0x36;
1236                         bctx->opad[i] ^= 0x5c;
1237                 }
1238         }
1239
1240         return err;
1241 }
1242
1243 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1244 {
1245         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1246         const char *alg_name = crypto_tfm_alg_name(tfm);
1247
1248         /* Allocate a fallback and abort if it failed. */
1249         tctx->fallback = crypto_alloc_shash(alg_name, 0,
1250                                             CRYPTO_ALG_NEED_FALLBACK);
1251         if (IS_ERR(tctx->fallback)) {
1252                 pr_err("omap-sham: fallback driver '%s' "
1253                                 "could not be loaded.\n", alg_name);
1254                 return PTR_ERR(tctx->fallback);
1255         }
1256
1257         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1258                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
1259
1260         if (alg_base) {
1261                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1262                 tctx->flags |= BIT(FLAGS_HMAC);
1263                 bctx->shash = crypto_alloc_shash(alg_base, 0,
1264                                                 CRYPTO_ALG_NEED_FALLBACK);
1265                 if (IS_ERR(bctx->shash)) {
1266                         pr_err("omap-sham: base driver '%s' "
1267                                         "could not be loaded.\n", alg_base);
1268                         crypto_free_shash(tctx->fallback);
1269                         return PTR_ERR(bctx->shash);
1270                 }
1271
1272         }
1273
1274         return 0;
1275 }
1276
1277 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1278 {
1279         return omap_sham_cra_init_alg(tfm, NULL);
1280 }
1281
1282 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1283 {
1284         return omap_sham_cra_init_alg(tfm, "sha1");
1285 }
1286
1287 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1288 {
1289         return omap_sham_cra_init_alg(tfm, "sha224");
1290 }
1291
1292 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1293 {
1294         return omap_sham_cra_init_alg(tfm, "sha256");
1295 }
1296
1297 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1298 {
1299         return omap_sham_cra_init_alg(tfm, "md5");
1300 }
1301
1302 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1303 {
1304         return omap_sham_cra_init_alg(tfm, "sha384");
1305 }
1306
1307 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1308 {
1309         return omap_sham_cra_init_alg(tfm, "sha512");
1310 }
1311
1312 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1313 {
1314         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1315
1316         crypto_free_shash(tctx->fallback);
1317         tctx->fallback = NULL;
1318
1319         if (tctx->flags & BIT(FLAGS_HMAC)) {
1320                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1321                 crypto_free_shash(bctx->shash);
1322         }
1323 }
1324
1325 static struct ahash_alg algs_sha1_md5[] = {
1326 {
1327         .init           = omap_sham_init,
1328         .update         = omap_sham_update,
1329         .final          = omap_sham_final,
1330         .finup          = omap_sham_finup,
1331         .digest         = omap_sham_digest,
1332         .halg.digestsize        = SHA1_DIGEST_SIZE,
1333         .halg.base      = {
1334                 .cra_name               = "sha1",
1335                 .cra_driver_name        = "omap-sha1",
1336                 .cra_priority           = 100,
1337                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1338                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1339                                                 CRYPTO_ALG_ASYNC |
1340                                                 CRYPTO_ALG_NEED_FALLBACK,
1341                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1342                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1343                 .cra_alignmask          = 0,
1344                 .cra_module             = THIS_MODULE,
1345                 .cra_init               = omap_sham_cra_init,
1346                 .cra_exit               = omap_sham_cra_exit,
1347         }
1348 },
1349 {
1350         .init           = omap_sham_init,
1351         .update         = omap_sham_update,
1352         .final          = omap_sham_final,
1353         .finup          = omap_sham_finup,
1354         .digest         = omap_sham_digest,
1355         .halg.digestsize        = MD5_DIGEST_SIZE,
1356         .halg.base      = {
1357                 .cra_name               = "md5",
1358                 .cra_driver_name        = "omap-md5",
1359                 .cra_priority           = 100,
1360                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1361                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1362                                                 CRYPTO_ALG_ASYNC |
1363                                                 CRYPTO_ALG_NEED_FALLBACK,
1364                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1365                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1366                 .cra_alignmask          = OMAP_ALIGN_MASK,
1367                 .cra_module             = THIS_MODULE,
1368                 .cra_init               = omap_sham_cra_init,
1369                 .cra_exit               = omap_sham_cra_exit,
1370         }
1371 },
1372 {
1373         .init           = omap_sham_init,
1374         .update         = omap_sham_update,
1375         .final          = omap_sham_final,
1376         .finup          = omap_sham_finup,
1377         .digest         = omap_sham_digest,
1378         .setkey         = omap_sham_setkey,
1379         .halg.digestsize        = SHA1_DIGEST_SIZE,
1380         .halg.base      = {
1381                 .cra_name               = "hmac(sha1)",
1382                 .cra_driver_name        = "omap-hmac-sha1",
1383                 .cra_priority           = 100,
1384                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1385                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1386                                                 CRYPTO_ALG_ASYNC |
1387                                                 CRYPTO_ALG_NEED_FALLBACK,
1388                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1389                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1390                                         sizeof(struct omap_sham_hmac_ctx),
1391                 .cra_alignmask          = OMAP_ALIGN_MASK,
1392                 .cra_module             = THIS_MODULE,
1393                 .cra_init               = omap_sham_cra_sha1_init,
1394                 .cra_exit               = omap_sham_cra_exit,
1395         }
1396 },
1397 {
1398         .init           = omap_sham_init,
1399         .update         = omap_sham_update,
1400         .final          = omap_sham_final,
1401         .finup          = omap_sham_finup,
1402         .digest         = omap_sham_digest,
1403         .setkey         = omap_sham_setkey,
1404         .halg.digestsize        = MD5_DIGEST_SIZE,
1405         .halg.base      = {
1406                 .cra_name               = "hmac(md5)",
1407                 .cra_driver_name        = "omap-hmac-md5",
1408                 .cra_priority           = 100,
1409                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1410                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1411                                                 CRYPTO_ALG_ASYNC |
1412                                                 CRYPTO_ALG_NEED_FALLBACK,
1413                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1414                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1415                                         sizeof(struct omap_sham_hmac_ctx),
1416                 .cra_alignmask          = OMAP_ALIGN_MASK,
1417                 .cra_module             = THIS_MODULE,
1418                 .cra_init               = omap_sham_cra_md5_init,
1419                 .cra_exit               = omap_sham_cra_exit,
1420         }
1421 }
1422 };
1423
1424 /* OMAP4 has some algs in addition to what OMAP2 has */
1425 static struct ahash_alg algs_sha224_sha256[] = {
1426 {
1427         .init           = omap_sham_init,
1428         .update         = omap_sham_update,
1429         .final          = omap_sham_final,
1430         .finup          = omap_sham_finup,
1431         .digest         = omap_sham_digest,
1432         .halg.digestsize        = SHA224_DIGEST_SIZE,
1433         .halg.base      = {
1434                 .cra_name               = "sha224",
1435                 .cra_driver_name        = "omap-sha224",
1436                 .cra_priority           = 100,
1437                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1438                                                 CRYPTO_ALG_ASYNC |
1439                                                 CRYPTO_ALG_NEED_FALLBACK,
1440                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1441                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1442                 .cra_alignmask          = 0,
1443                 .cra_module             = THIS_MODULE,
1444                 .cra_init               = omap_sham_cra_init,
1445                 .cra_exit               = omap_sham_cra_exit,
1446         }
1447 },
1448 {
1449         .init           = omap_sham_init,
1450         .update         = omap_sham_update,
1451         .final          = omap_sham_final,
1452         .finup          = omap_sham_finup,
1453         .digest         = omap_sham_digest,
1454         .halg.digestsize        = SHA256_DIGEST_SIZE,
1455         .halg.base      = {
1456                 .cra_name               = "sha256",
1457                 .cra_driver_name        = "omap-sha256",
1458                 .cra_priority           = 100,
1459                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1460                                                 CRYPTO_ALG_ASYNC |
1461                                                 CRYPTO_ALG_NEED_FALLBACK,
1462                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1463                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1464                 .cra_alignmask          = 0,
1465                 .cra_module             = THIS_MODULE,
1466                 .cra_init               = omap_sham_cra_init,
1467                 .cra_exit               = omap_sham_cra_exit,
1468         }
1469 },
1470 {
1471         .init           = omap_sham_init,
1472         .update         = omap_sham_update,
1473         .final          = omap_sham_final,
1474         .finup          = omap_sham_finup,
1475         .digest         = omap_sham_digest,
1476         .setkey         = omap_sham_setkey,
1477         .halg.digestsize        = SHA224_DIGEST_SIZE,
1478         .halg.base      = {
1479                 .cra_name               = "hmac(sha224)",
1480                 .cra_driver_name        = "omap-hmac-sha224",
1481                 .cra_priority           = 100,
1482                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1483                                                 CRYPTO_ALG_ASYNC |
1484                                                 CRYPTO_ALG_NEED_FALLBACK,
1485                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1486                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1487                                         sizeof(struct omap_sham_hmac_ctx),
1488                 .cra_alignmask          = OMAP_ALIGN_MASK,
1489                 .cra_module             = THIS_MODULE,
1490                 .cra_init               = omap_sham_cra_sha224_init,
1491                 .cra_exit               = omap_sham_cra_exit,
1492         }
1493 },
1494 {
1495         .init           = omap_sham_init,
1496         .update         = omap_sham_update,
1497         .final          = omap_sham_final,
1498         .finup          = omap_sham_finup,
1499         .digest         = omap_sham_digest,
1500         .setkey         = omap_sham_setkey,
1501         .halg.digestsize        = SHA256_DIGEST_SIZE,
1502         .halg.base      = {
1503                 .cra_name               = "hmac(sha256)",
1504                 .cra_driver_name        = "omap-hmac-sha256",
1505                 .cra_priority           = 100,
1506                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1507                                                 CRYPTO_ALG_ASYNC |
1508                                                 CRYPTO_ALG_NEED_FALLBACK,
1509                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1510                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1511                                         sizeof(struct omap_sham_hmac_ctx),
1512                 .cra_alignmask          = OMAP_ALIGN_MASK,
1513                 .cra_module             = THIS_MODULE,
1514                 .cra_init               = omap_sham_cra_sha256_init,
1515                 .cra_exit               = omap_sham_cra_exit,
1516         }
1517 },
1518 };
1519
1520 static struct ahash_alg algs_sha384_sha512[] = {
1521 {
1522         .init           = omap_sham_init,
1523         .update         = omap_sham_update,
1524         .final          = omap_sham_final,
1525         .finup          = omap_sham_finup,
1526         .digest         = omap_sham_digest,
1527         .halg.digestsize        = SHA384_DIGEST_SIZE,
1528         .halg.base      = {
1529                 .cra_name               = "sha384",
1530                 .cra_driver_name        = "omap-sha384",
1531                 .cra_priority           = 100,
1532                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1533                                                 CRYPTO_ALG_ASYNC |
1534                                                 CRYPTO_ALG_NEED_FALLBACK,
1535                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1536                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1537                 .cra_alignmask          = 0,
1538                 .cra_module             = THIS_MODULE,
1539                 .cra_init               = omap_sham_cra_init,
1540                 .cra_exit               = omap_sham_cra_exit,
1541         }
1542 },
1543 {
1544         .init           = omap_sham_init,
1545         .update         = omap_sham_update,
1546         .final          = omap_sham_final,
1547         .finup          = omap_sham_finup,
1548         .digest         = omap_sham_digest,
1549         .halg.digestsize        = SHA512_DIGEST_SIZE,
1550         .halg.base      = {
1551                 .cra_name               = "sha512",
1552                 .cra_driver_name        = "omap-sha512",
1553                 .cra_priority           = 100,
1554                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1555                                                 CRYPTO_ALG_ASYNC |
1556                                                 CRYPTO_ALG_NEED_FALLBACK,
1557                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1558                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1559                 .cra_alignmask          = 0,
1560                 .cra_module             = THIS_MODULE,
1561                 .cra_init               = omap_sham_cra_init,
1562                 .cra_exit               = omap_sham_cra_exit,
1563         }
1564 },
1565 {
1566         .init           = omap_sham_init,
1567         .update         = omap_sham_update,
1568         .final          = omap_sham_final,
1569         .finup          = omap_sham_finup,
1570         .digest         = omap_sham_digest,
1571         .setkey         = omap_sham_setkey,
1572         .halg.digestsize        = SHA384_DIGEST_SIZE,
1573         .halg.base      = {
1574                 .cra_name               = "hmac(sha384)",
1575                 .cra_driver_name        = "omap-hmac-sha384",
1576                 .cra_priority           = 100,
1577                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1578                                                 CRYPTO_ALG_ASYNC |
1579                                                 CRYPTO_ALG_NEED_FALLBACK,
1580                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1581                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1582                                         sizeof(struct omap_sham_hmac_ctx),
1583                 .cra_alignmask          = OMAP_ALIGN_MASK,
1584                 .cra_module             = THIS_MODULE,
1585                 .cra_init               = omap_sham_cra_sha384_init,
1586                 .cra_exit               = omap_sham_cra_exit,
1587         }
1588 },
1589 {
1590         .init           = omap_sham_init,
1591         .update         = omap_sham_update,
1592         .final          = omap_sham_final,
1593         .finup          = omap_sham_finup,
1594         .digest         = omap_sham_digest,
1595         .setkey         = omap_sham_setkey,
1596         .halg.digestsize        = SHA512_DIGEST_SIZE,
1597         .halg.base      = {
1598                 .cra_name               = "hmac(sha512)",
1599                 .cra_driver_name        = "omap-hmac-sha512",
1600                 .cra_priority           = 100,
1601                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1602                                                 CRYPTO_ALG_ASYNC |
1603                                                 CRYPTO_ALG_NEED_FALLBACK,
1604                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1605                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1606                                         sizeof(struct omap_sham_hmac_ctx),
1607                 .cra_alignmask          = OMAP_ALIGN_MASK,
1608                 .cra_module             = THIS_MODULE,
1609                 .cra_init               = omap_sham_cra_sha512_init,
1610                 .cra_exit               = omap_sham_cra_exit,
1611         }
1612 },
1613 };
1614
1615 static void omap_sham_done_task(unsigned long data)
1616 {
1617         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1618         int err = 0;
1619
1620         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1621                 omap_sham_handle_queue(dd, NULL);
1622                 return;
1623         }
1624
1625         if (test_bit(FLAGS_CPU, &dd->flags)) {
1626                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1627                         /* hash or semi-hash ready */
1628                         err = omap_sham_update_cpu(dd);
1629                         if (err != -EINPROGRESS)
1630                                 goto finish;
1631                 }
1632         } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1633                 if (test_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1634                         omap_sham_update_dma_stop(dd);
1635                         if (dd->err) {
1636                                 err = dd->err;
1637                                 goto finish;
1638                         }
1639                 }
1640                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1641                         /* hash or semi-hash ready */
1642                         clear_bit(FLAGS_DMA_READY, &dd->flags);
1643                         err = omap_sham_update_dma_start(dd);
1644                         if (err != -EINPROGRESS)
1645                                 goto finish;
1646                 }
1647         }
1648
1649         return;
1650
1651 finish:
1652         dev_dbg(dd->dev, "update done: err: %d\n", err);
1653         /* finish curent request */
1654         omap_sham_finish_req(dd->req, err);
1655 }
1656
1657 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1658 {
1659         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1660                 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1661         } else {
1662                 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1663                 tasklet_schedule(&dd->done_task);
1664         }
1665
1666         return IRQ_HANDLED;
1667 }
1668
1669 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1670 {
1671         struct omap_sham_dev *dd = dev_id;
1672
1673         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1674                 /* final -> allow device to go to power-saving mode */
1675                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1676
1677         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1678                                  SHA_REG_CTRL_OUTPUT_READY);
1679         omap_sham_read(dd, SHA_REG_CTRL);
1680
1681         return omap_sham_irq_common(dd);
1682 }
1683
1684 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1685 {
1686         struct omap_sham_dev *dd = dev_id;
1687
1688         omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1689
1690         return omap_sham_irq_common(dd);
1691 }
1692
1693 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1694         {
1695                 .algs_list      = algs_sha1_md5,
1696                 .size           = ARRAY_SIZE(algs_sha1_md5),
1697         },
1698 };
1699
1700 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1701         .algs_info      = omap_sham_algs_info_omap2,
1702         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1703         .flags          = BIT(FLAGS_BE32_SHA1),
1704         .digest_size    = SHA1_DIGEST_SIZE,
1705         .copy_hash      = omap_sham_copy_hash_omap2,
1706         .write_ctrl     = omap_sham_write_ctrl_omap2,
1707         .trigger        = omap_sham_trigger_omap2,
1708         .poll_irq       = omap_sham_poll_irq_omap2,
1709         .intr_hdlr      = omap_sham_irq_omap2,
1710         .idigest_ofs    = 0x00,
1711         .din_ofs        = 0x1c,
1712         .digcnt_ofs     = 0x14,
1713         .rev_ofs        = 0x5c,
1714         .mask_ofs       = 0x60,
1715         .sysstatus_ofs  = 0x64,
1716         .major_mask     = 0xf0,
1717         .major_shift    = 4,
1718         .minor_mask     = 0x0f,
1719         .minor_shift    = 0,
1720 };
1721
1722 #ifdef CONFIG_OF
1723 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1724         {
1725                 .algs_list      = algs_sha1_md5,
1726                 .size           = ARRAY_SIZE(algs_sha1_md5),
1727         },
1728         {
1729                 .algs_list      = algs_sha224_sha256,
1730                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1731         },
1732 };
1733
1734 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1735         .algs_info      = omap_sham_algs_info_omap4,
1736         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1737         .flags          = BIT(FLAGS_AUTO_XOR),
1738         .digest_size    = SHA256_DIGEST_SIZE,
1739         .copy_hash      = omap_sham_copy_hash_omap4,
1740         .write_ctrl     = omap_sham_write_ctrl_omap4,
1741         .trigger        = omap_sham_trigger_omap4,
1742         .poll_irq       = omap_sham_poll_irq_omap4,
1743         .intr_hdlr      = omap_sham_irq_omap4,
1744         .idigest_ofs    = 0x020,
1745         .odigest_ofs    = 0x0,
1746         .din_ofs        = 0x080,
1747         .digcnt_ofs     = 0x040,
1748         .rev_ofs        = 0x100,
1749         .mask_ofs       = 0x110,
1750         .sysstatus_ofs  = 0x114,
1751         .mode_ofs       = 0x44,
1752         .length_ofs     = 0x48,
1753         .major_mask     = 0x0700,
1754         .major_shift    = 8,
1755         .minor_mask     = 0x003f,
1756         .minor_shift    = 0,
1757 };
1758
1759 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1760         {
1761                 .algs_list      = algs_sha1_md5,
1762                 .size           = ARRAY_SIZE(algs_sha1_md5),
1763         },
1764         {
1765                 .algs_list      = algs_sha224_sha256,
1766                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1767         },
1768         {
1769                 .algs_list      = algs_sha384_sha512,
1770                 .size           = ARRAY_SIZE(algs_sha384_sha512),
1771         },
1772 };
1773
1774 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1775         .algs_info      = omap_sham_algs_info_omap5,
1776         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1777         .flags          = BIT(FLAGS_AUTO_XOR),
1778         .digest_size    = SHA512_DIGEST_SIZE,
1779         .copy_hash      = omap_sham_copy_hash_omap4,
1780         .write_ctrl     = omap_sham_write_ctrl_omap4,
1781         .trigger        = omap_sham_trigger_omap4,
1782         .poll_irq       = omap_sham_poll_irq_omap4,
1783         .intr_hdlr      = omap_sham_irq_omap4,
1784         .idigest_ofs    = 0x240,
1785         .odigest_ofs    = 0x200,
1786         .din_ofs        = 0x080,
1787         .digcnt_ofs     = 0x280,
1788         .rev_ofs        = 0x100,
1789         .mask_ofs       = 0x110,
1790         .sysstatus_ofs  = 0x114,
1791         .mode_ofs       = 0x284,
1792         .length_ofs     = 0x288,
1793         .major_mask     = 0x0700,
1794         .major_shift    = 8,
1795         .minor_mask     = 0x003f,
1796         .minor_shift    = 0,
1797 };
1798
1799 static const struct of_device_id omap_sham_of_match[] = {
1800         {
1801                 .compatible     = "ti,omap2-sham",
1802                 .data           = &omap_sham_pdata_omap2,
1803         },
1804         {
1805                 .compatible     = "ti,omap3-sham",
1806                 .data           = &omap_sham_pdata_omap2,
1807         },
1808         {
1809                 .compatible     = "ti,omap4-sham",
1810                 .data           = &omap_sham_pdata_omap4,
1811         },
1812         {
1813                 .compatible     = "ti,omap5-sham",
1814                 .data           = &omap_sham_pdata_omap5,
1815         },
1816         {},
1817 };
1818 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1819
1820 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1821                 struct device *dev, struct resource *res)
1822 {
1823         struct device_node *node = dev->of_node;
1824         const struct of_device_id *match;
1825         int err = 0;
1826
1827         match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
1828         if (!match) {
1829                 dev_err(dev, "no compatible OF match\n");
1830                 err = -EINVAL;
1831                 goto err;
1832         }
1833
1834         err = of_address_to_resource(node, 0, res);
1835         if (err < 0) {
1836                 dev_err(dev, "can't translate OF node address\n");
1837                 err = -EINVAL;
1838                 goto err;
1839         }
1840
1841         dd->irq = irq_of_parse_and_map(node, 0);
1842         if (!dd->irq) {
1843                 dev_err(dev, "can't translate OF irq value\n");
1844                 err = -EINVAL;
1845                 goto err;
1846         }
1847
1848         dd->dma = -1; /* Dummy value that's unused */
1849         dd->pdata = match->data;
1850
1851 err:
1852         return err;
1853 }
1854 #else
1855 static const struct of_device_id omap_sham_of_match[] = {
1856         {},
1857 };
1858
1859 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1860                 struct device *dev, struct resource *res)
1861 {
1862         return -EINVAL;
1863 }
1864 #endif
1865
1866 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1867                 struct platform_device *pdev, struct resource *res)
1868 {
1869         struct device *dev = &pdev->dev;
1870         struct resource *r;
1871         int err = 0;
1872
1873         /* Get the base address */
1874         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1875         if (!r) {
1876                 dev_err(dev, "no MEM resource info\n");
1877                 err = -ENODEV;
1878                 goto err;
1879         }
1880         memcpy(res, r, sizeof(*res));
1881
1882         /* Get the IRQ */
1883         dd->irq = platform_get_irq(pdev, 0);
1884         if (dd->irq < 0) {
1885                 dev_err(dev, "no IRQ resource info\n");
1886                 err = dd->irq;
1887                 goto err;
1888         }
1889
1890         /* Get the DMA */
1891         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1892         if (!r) {
1893                 dev_err(dev, "no DMA resource info\n");
1894                 err = -ENODEV;
1895                 goto err;
1896         }
1897         dd->dma = r->start;
1898
1899         /* Only OMAP2/3 can be non-DT */
1900         dd->pdata = &omap_sham_pdata_omap2;
1901
1902 err:
1903         return err;
1904 }
1905
1906 static int omap_sham_probe(struct platform_device *pdev)
1907 {
1908         struct omap_sham_dev *dd;
1909         struct device *dev = &pdev->dev;
1910         struct resource res;
1911         dma_cap_mask_t mask;
1912         int err, i, j;
1913         u32 rev;
1914
1915         dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
1916         if (dd == NULL) {
1917                 dev_err(dev, "unable to alloc data struct.\n");
1918                 err = -ENOMEM;
1919                 goto data_err;
1920         }
1921         dd->dev = dev;
1922         platform_set_drvdata(pdev, dd);
1923
1924         INIT_LIST_HEAD(&dd->list);
1925         spin_lock_init(&dd->lock);
1926         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
1927         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
1928
1929         err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
1930                                omap_sham_get_res_pdev(dd, pdev, &res);
1931         if (err)
1932                 goto data_err;
1933
1934         dd->io_base = devm_ioremap_resource(dev, &res);
1935         if (IS_ERR(dd->io_base)) {
1936                 err = PTR_ERR(dd->io_base);
1937                 goto data_err;
1938         }
1939         dd->phys_base = res.start;
1940
1941         err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
1942                                IRQF_TRIGGER_NONE, dev_name(dev), dd);
1943         if (err) {
1944                 dev_err(dev, "unable to request irq %d, err = %d\n",
1945                         dd->irq, err);
1946                 goto data_err;
1947         }
1948
1949         dma_cap_zero(mask);
1950         dma_cap_set(DMA_SLAVE, mask);
1951
1952         dd->dma_lch = dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1953                                                        &dd->dma, dev, "rx");
1954         if (!dd->dma_lch) {
1955                 dd->polling_mode = 1;
1956                 dev_dbg(dev, "using polling mode instead of dma\n");
1957         }
1958
1959         dd->flags |= dd->pdata->flags;
1960
1961         pm_runtime_enable(dev);
1962         pm_runtime_irq_safe(dev);
1963
1964         err = pm_runtime_get_sync(dev);
1965         if (err < 0) {
1966                 dev_err(dev, "failed to get sync: %d\n", err);
1967                 goto err_pm;
1968         }
1969
1970         rev = omap_sham_read(dd, SHA_REG_REV(dd));
1971         pm_runtime_put_sync(&pdev->dev);
1972
1973         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
1974                 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
1975                 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1976
1977         spin_lock(&sham.lock);
1978         list_add_tail(&dd->list, &sham.dev_list);
1979         spin_unlock(&sham.lock);
1980
1981         for (i = 0; i < dd->pdata->algs_info_size; i++) {
1982                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1983                         err = crypto_register_ahash(
1984                                         &dd->pdata->algs_info[i].algs_list[j]);
1985                         if (err)
1986                                 goto err_algs;
1987
1988                         dd->pdata->algs_info[i].registered++;
1989                 }
1990         }
1991
1992         return 0;
1993
1994 err_algs:
1995         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1996                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1997                         crypto_unregister_ahash(
1998                                         &dd->pdata->algs_info[i].algs_list[j]);
1999 err_pm:
2000         pm_runtime_disable(dev);
2001         if (dd->dma_lch)
2002                 dma_release_channel(dd->dma_lch);
2003 data_err:
2004         dev_err(dev, "initialization failed.\n");
2005
2006         return err;
2007 }
2008
2009 static int omap_sham_remove(struct platform_device *pdev)
2010 {
2011         static struct omap_sham_dev *dd;
2012         int i, j;
2013
2014         dd = platform_get_drvdata(pdev);
2015         if (!dd)
2016                 return -ENODEV;
2017         spin_lock(&sham.lock);
2018         list_del(&dd->list);
2019         spin_unlock(&sham.lock);
2020         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2021                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2022                         crypto_unregister_ahash(
2023                                         &dd->pdata->algs_info[i].algs_list[j]);
2024         tasklet_kill(&dd->done_task);
2025         pm_runtime_disable(&pdev->dev);
2026
2027         if (dd->dma_lch)
2028                 dma_release_channel(dd->dma_lch);
2029
2030         return 0;
2031 }
2032
2033 #ifdef CONFIG_PM_SLEEP
2034 static int omap_sham_suspend(struct device *dev)
2035 {
2036         pm_runtime_put_sync(dev);
2037         return 0;
2038 }
2039
2040 static int omap_sham_resume(struct device *dev)
2041 {
2042         int err = pm_runtime_get_sync(dev);
2043         if (err < 0) {
2044                 dev_err(dev, "failed to get sync: %d\n", err);
2045                 return err;
2046         }
2047         return 0;
2048 }
2049 #endif
2050
2051 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2052
2053 static struct platform_driver omap_sham_driver = {
2054         .probe  = omap_sham_probe,
2055         .remove = omap_sham_remove,
2056         .driver = {
2057                 .name   = "omap-sham",
2058                 .pm     = &omap_sham_pm_ops,
2059                 .of_match_table = omap_sham_of_match,
2060         },
2061 };
2062
2063 module_platform_driver(omap_sham_driver);
2064
2065 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2066 MODULE_LICENSE("GPL v2");
2067 MODULE_AUTHOR("Dmitry Kasatkin");
2068 MODULE_ALIAS("platform:omap-sham");