drivers/crypto/omap-sham.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP SHA1/MD5 HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  * Copyright (c) 2011 Texas Instruments Incorporated
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  * Some ideas are from old omap-sha1-md5.c driver.
  15  */
  16
  17 #define pr_fmt(fmt) "%s: " fmt, __func__
  18
  19 #include <linux/err.h>
  20 #include <linux/device.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/irq.h>
  27 #include <linux/io.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/delay.h>
  38 #include <linux/crypto.h>
  39 #include <linux/cryptohash.h>
  40 #include <crypto/scatterwalk.h>
  41 #include <crypto/algapi.h>
  42 #include <crypto/sha.h>
  43 #include <crypto/hash.h>
  44 #include <crypto/hmac.h>
  45 #include <crypto/internal/hash.h>
  46
  47 #define MD5_DIGEST_SIZE                 16
  48
  49 #define SHA_REG_IDIGEST(dd, x)          ((dd)->pdata->idigest_ofs + ((x)*0x04))
  50 #define SHA_REG_DIN(dd, x)              ((dd)->pdata->din_ofs + ((x) * 0x04))
  51 #define SHA_REG_DIGCNT(dd)              ((dd)->pdata->digcnt_ofs)
  52
  53 #define SHA_REG_ODIGEST(dd, x)          ((dd)->pdata->odigest_ofs + (x * 0x04))
  54
  55 #define SHA_REG_CTRL                    0x18
  56 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  57 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  58 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  59 #define SHA_REG_CTRL_ALGO               (1 << 2)
  60 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  61 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  62
  63 #define SHA_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  64
  65 #define SHA_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  66 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  67 #define SHA_REG_MASK_IT_EN              (1 << 2)
  68 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  69 #define SHA_REG_AUTOIDLE                (1 << 0)
  70
  71 #define SHA_REG_SYSSTATUS(dd)           ((dd)->pdata->sysstatus_ofs)
  72 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  73
  74 #define SHA_REG_MODE(dd)                ((dd)->pdata->mode_ofs)
  75 #define SHA_REG_MODE_HMAC_OUTER_HASH    (1 << 7)
  76 #define SHA_REG_MODE_HMAC_KEY_PROC      (1 << 5)
  77 #define SHA_REG_MODE_CLOSE_HASH         (1 << 4)
  78 #define SHA_REG_MODE_ALGO_CONSTANT      (1 << 3)
  79
  80 #define SHA_REG_MODE_ALGO_MASK          (7 << 0)
  81 #define SHA_REG_MODE_ALGO_MD5_128       (0 << 1)
  82 #define SHA_REG_MODE_ALGO_SHA1_160      (1 << 1)
  83 #define SHA_REG_MODE_ALGO_SHA2_224      (2 << 1)
  84 #define SHA_REG_MODE_ALGO_SHA2_256      (3 << 1)
  85 #define SHA_REG_MODE_ALGO_SHA2_384      (1 << 0)
  86 #define SHA_REG_MODE_ALGO_SHA2_512      (3 << 0)
  87
  88 #define SHA_REG_LENGTH(dd)              ((dd)->pdata->length_ofs)
  89
  90 #define SHA_REG_IRQSTATUS               0x118
  91 #define SHA_REG_IRQSTATUS_CTX_RDY       (1 << 3)
  92 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
  93 #define SHA_REG_IRQSTATUS_INPUT_RDY     (1 << 1)
  94 #define SHA_REG_IRQSTATUS_OUTPUT_RDY    (1 << 0)
  95
  96 #define SHA_REG_IRQENA                  0x11C
  97 #define SHA_REG_IRQENA_CTX_RDY          (1 << 3)
  98 #define SHA_REG_IRQENA_PARTHASH_RDY     (1 << 2)
  99 #define SHA_REG_IRQENA_INPUT_RDY        (1 << 1)
 100 #define SHA_REG_IRQENA_OUTPUT_RDY       (1 << 0)
 101
 102 #define DEFAULT_TIMEOUT_INTERVAL        HZ
 103
 104 #define DEFAULT_AUTOSUSPEND_DELAY       1000
 105
 106 /* mostly device flags */
 107 #define FLAGS_BUSY              0
 108 #define FLAGS_FINAL             1
 109 #define FLAGS_DMA_ACTIVE        2
 110 #define FLAGS_OUTPUT_READY      3
 111 #define FLAGS_INIT              4
 112 #define FLAGS_CPU               5
 113 #define FLAGS_DMA_READY         6
 114 #define FLAGS_AUTO_XOR          7
 115 #define FLAGS_BE32_SHA1         8
 116 #define FLAGS_SGS_COPIED        9
 117 #define FLAGS_SGS_ALLOCED       10
 118 /* context flags */
 119 #define FLAGS_FINUP             16
 120
 121 #define FLAGS_MODE_SHIFT        18
 122 #define FLAGS_MODE_MASK         (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
 123 #define FLAGS_MODE_MD5          (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
 124 #define FLAGS_MODE_SHA1         (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
 125 #define FLAGS_MODE_SHA224       (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
 126 #define FLAGS_MODE_SHA256       (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
 127 #define FLAGS_MODE_SHA384       (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
 128 #define FLAGS_MODE_SHA512       (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
 129
 130 #define FLAGS_HMAC              21
 131 #define FLAGS_ERROR             22
 132
 133 #define OP_UPDATE               1
 134 #define OP_FINAL                2
 135
 136 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
 137 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
 138
 139 #define BUFLEN                  SHA512_BLOCK_SIZE
 140 #define OMAP_SHA_DMA_THRESHOLD  256
 141
 142 struct omap_sham_dev;
 143
 144 struct omap_sham_reqctx {
 145         struct omap_sham_dev    *dd;
 146         unsigned long           flags;
 147         unsigned long           op;
 148
 149         u8                      digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
 150         size_t                  digcnt;
 151         size_t                  bufcnt;
 152         size_t                  buflen;
 153
 154         /* walk state */
 155         struct scatterlist      *sg;
 156         struct scatterlist      sgl[2];
 157         int                     offset; /* offset in current sg */
 158         int                     sg_len;
 159         unsigned int            total;  /* total request */
 160
 161         u8                      buffer[0] OMAP_ALIGNED;
 162 };
 163
 164 struct omap_sham_hmac_ctx {
 165         struct crypto_shash     *shash;
 166         u8                      ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 167         u8                      opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 168 };
 169
 170 struct omap_sham_ctx {
 171         unsigned long           flags;
 172
 173         /* fallback stuff */
 174         struct crypto_shash     *fallback;
 175
 176         struct omap_sham_hmac_ctx base[0];
 177 };
 178
 179 #define OMAP_SHAM_QUEUE_LENGTH  10
 180
 181 struct omap_sham_algs_info {
 182         struct ahash_alg        *algs_list;
 183         unsigned int            size;
 184         unsigned int            registered;
 185 };
 186
 187 struct omap_sham_pdata {
 188         struct omap_sham_algs_info      *algs_info;
 189         unsigned int    algs_info_size;
 190         unsigned long   flags;
 191         int             digest_size;
 192
 193         void            (*copy_hash)(struct ahash_request *req, int out);
 194         void            (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
 195                                       int final, int dma);
 196         void            (*trigger)(struct omap_sham_dev *dd, size_t length);
 197         int             (*poll_irq)(struct omap_sham_dev *dd);
 198         irqreturn_t     (*intr_hdlr)(int irq, void *dev_id);
 199
 200         u32             odigest_ofs;
 201         u32             idigest_ofs;
 202         u32             din_ofs;
 203         u32             digcnt_ofs;
 204         u32             rev_ofs;
 205         u32             mask_ofs;
 206         u32             sysstatus_ofs;
 207         u32             mode_ofs;
 208         u32             length_ofs;
 209
 210         u32             major_mask;
 211         u32             major_shift;
 212         u32             minor_mask;
 213         u32             minor_shift;
 214 };
 215
 216 struct omap_sham_dev {
 217         struct list_head        list;
 218         unsigned long           phys_base;
 219         struct device           *dev;
 220         void __iomem            *io_base;
 221         int                     irq;
 222         spinlock_t              lock;
 223         int                     err;
 224         struct dma_chan         *dma_lch;
 225         struct tasklet_struct   done_task;
 226         u8                      polling_mode;
 227         u8                      xmit_buf[BUFLEN] OMAP_ALIGNED;
 228
 229         unsigned long           flags;
 230         struct crypto_queue     queue;
 231         struct ahash_request    *req;
 232
 233         const struct omap_sham_pdata    *pdata;
 234 };
 235
 236 struct omap_sham_drv {
 237         struct list_head        dev_list;
 238         spinlock_t              lock;
 239         unsigned long           flags;
 240 };
 241
 242 static struct omap_sham_drv sham = {
 243         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 244         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 245 };
 246
 247 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 248 {
 249         return __raw_readl(dd->io_base + offset);
 250 }
 251
 252 static inline void omap_sham_write(struct omap_sham_dev *dd,
 253                                         u32 offset, u32 value)
 254 {
 255         __raw_writel(value, dd->io_base + offset);
 256 }
 257
 258 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 259                                         u32 value, u32 mask)
 260 {
 261         u32 val;
 262
 263         val = omap_sham_read(dd, address);
 264         val &= ~mask;
 265         val |= value;
 266         omap_sham_write(dd, address, val);
 267 }
 268
 269 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 270 {
 271         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 272
 273         while (!(omap_sham_read(dd, offset) & bit)) {
 274                 if (time_is_before_jiffies(timeout))
 275                         return -ETIMEDOUT;
 276         }
 277
 278         return 0;
 279 }
 280
 281 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
 282 {
 283         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 284         struct omap_sham_dev *dd = ctx->dd;
 285         u32 *hash = (u32 *)ctx->digest;
 286         int i;
 287
 288         for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 289                 if (out)
 290                         hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
 291                 else
 292                         omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
 293         }
 294 }
 295
 296 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
 297 {
 298         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 299         struct omap_sham_dev *dd = ctx->dd;
 300         int i;
 301
 302         if (ctx->flags & BIT(FLAGS_HMAC)) {
 303                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 304                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 305                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 306                 u32 *opad = (u32 *)bctx->opad;
 307
 308                 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 309                         if (out)
 310                                 opad[i] = omap_sham_read(dd,
 311                                                 SHA_REG_ODIGEST(dd, i));
 312                         else
 313                                 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
 314                                                 opad[i]);
 315                 }
 316         }
 317
 318         omap_sham_copy_hash_omap2(req, out);
 319 }
 320
 321 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 322 {
 323         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 324         u32 *in = (u32 *)ctx->digest;
 325         u32 *hash = (u32 *)req->result;
 326         int i, d, big_endian = 0;
 327
 328         if (!hash)
 329                 return;
 330
 331         switch (ctx->flags & FLAGS_MODE_MASK) {
 332         case FLAGS_MODE_MD5:
 333                 d = MD5_DIGEST_SIZE / sizeof(u32);
 334                 break;
 335         case FLAGS_MODE_SHA1:
 336                 /* OMAP2 SHA1 is big endian */
 337                 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
 338                         big_endian = 1;
 339                 d = SHA1_DIGEST_SIZE / sizeof(u32);
 340                 break;
 341         case FLAGS_MODE_SHA224:
 342                 d = SHA224_DIGEST_SIZE / sizeof(u32);
 343                 break;
 344         case FLAGS_MODE_SHA256:
 345                 d = SHA256_DIGEST_SIZE / sizeof(u32);
 346                 break;
 347         case FLAGS_MODE_SHA384:
 348                 d = SHA384_DIGEST_SIZE / sizeof(u32);
 349                 break;
 350         case FLAGS_MODE_SHA512:
 351                 d = SHA512_DIGEST_SIZE / sizeof(u32);
 352                 break;
 353         default:
 354                 d = 0;
 355         }
 356
 357         if (big_endian)
 358                 for (i = 0; i < d; i++)
 359                         hash[i] = be32_to_cpu(in[i]);
 360         else
 361                 for (i = 0; i < d; i++)
 362                         hash[i] = le32_to_cpu(in[i]);
 363 }
 364
 365 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 366 {
 367         int err;
 368
 369         err = pm_runtime_get_sync(dd->dev);
 370         if (err < 0) {
 371                 dev_err(dd->dev, "failed to get sync: %d\n", err);
 372                 return err;
 373         }
 374
 375         if (!test_bit(FLAGS_INIT, &dd->flags)) {
 376                 set_bit(FLAGS_INIT, &dd->flags);
 377                 dd->err = 0;
 378         }
 379
 380         return 0;
 381 }
 382
 383 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
 384                                  int final, int dma)
 385 {
 386         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 387         u32 val = length << 5, mask;
 388
 389         if (likely(ctx->digcnt))
 390                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 391
 392         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 393                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 394                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 395         /*
 396          * Setting ALGO_CONST only for the first iteration
 397          * and CLOSE_HASH only for the last one.
 398          */
 399         if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
 400                 val |= SHA_REG_CTRL_ALGO;
 401         if (!ctx->digcnt)
 402                 val |= SHA_REG_CTRL_ALGO_CONST;
 403         if (final)
 404                 val |= SHA_REG_CTRL_CLOSE_HASH;
 405
 406         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 407                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 408
 409         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 410 }
 411
 412 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
 413 {
 414 }
 415
 416 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
 417 {
 418         return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
 419 }
 420
 421 static int get_block_size(struct omap_sham_reqctx *ctx)
 422 {
 423         int d;
 424
 425         switch (ctx->flags & FLAGS_MODE_MASK) {
 426         case FLAGS_MODE_MD5:
 427         case FLAGS_MODE_SHA1:
 428                 d = SHA1_BLOCK_SIZE;
 429                 break;
 430         case FLAGS_MODE_SHA224:
 431         case FLAGS_MODE_SHA256:
 432                 d = SHA256_BLOCK_SIZE;
 433                 break;
 434         case FLAGS_MODE_SHA384:
 435         case FLAGS_MODE_SHA512:
 436                 d = SHA512_BLOCK_SIZE;
 437                 break;
 438         default:
 439                 d = 0;
 440         }
 441
 442         return d;
 443 }
 444
 445 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
 446                                     u32 *value, int count)
 447 {
 448         for (; count--; value++, offset += 4)
 449                 omap_sham_write(dd, offset, *value);
 450 }
 451
 452 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
 453                                  int final, int dma)
 454 {
 455         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 456         u32 val, mask;
 457
 458         if (likely(ctx->digcnt))
 459                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 460
 461         /*
 462          * Setting ALGO_CONST only for the first iteration and
 463          * CLOSE_HASH only for the last one. Note that flags mode bits
 464          * correspond to algorithm encoding in mode register.
 465          */
 466         val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
 467         if (!ctx->digcnt) {
 468                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 469                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 470                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 471                 int bs, nr_dr;
 472
 473                 val |= SHA_REG_MODE_ALGO_CONSTANT;
 474
 475                 if (ctx->flags & BIT(FLAGS_HMAC)) {
 476                         bs = get_block_size(ctx);
 477                         nr_dr = bs / (2 * sizeof(u32));
 478                         val |= SHA_REG_MODE_HMAC_KEY_PROC;
 479                         omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
 480                                           (u32 *)bctx->ipad, nr_dr);
 481                         omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
 482                                           (u32 *)bctx->ipad + nr_dr, nr_dr);
 483                         ctx->digcnt += bs;
 484                 }
 485         }
 486
 487         if (final) {
 488                 val |= SHA_REG_MODE_CLOSE_HASH;
 489
 490                 if (ctx->flags & BIT(FLAGS_HMAC))
 491                         val |= SHA_REG_MODE_HMAC_OUTER_HASH;
 492         }
 493
 494         mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
 495                SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
 496                SHA_REG_MODE_HMAC_KEY_PROC;
 497
 498         dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
 499         omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
 500         omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
 501         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 502                              SHA_REG_MASK_IT_EN |
 503                                      (dma ? SHA_REG_MASK_DMA_EN : 0),
 504                              SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 505 }
 506
 507 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
 508 {
 509         omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
 510 }
 511
 512 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
 513 {
 514         return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
 515                               SHA_REG_IRQSTATUS_INPUT_RDY);
 516 }
 517
 518 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
 519                               int final)
 520 {
 521         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 522         int count, len32, bs32, offset = 0;
 523         const u32 *buffer;
 524         int mlen;
 525         struct sg_mapping_iter mi;
 526
 527         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 528                                                 ctx->digcnt, length, final);
 529
 530         dd->pdata->write_ctrl(dd, length, final, 0);
 531         dd->pdata->trigger(dd, length);
 532
 533         /* should be non-zero before next lines to disable clocks later */
 534         ctx->digcnt += length;
 535         ctx->total -= length;
 536
 537         if (final)
 538                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 539
 540         set_bit(FLAGS_CPU, &dd->flags);
 541
 542         len32 = DIV_ROUND_UP(length, sizeof(u32));
 543         bs32 = get_block_size(ctx) / sizeof(u32);
 544
 545         sg_miter_start(&mi, ctx->sg, ctx->sg_len,
 546                        SG_MITER_FROM_SG | SG_MITER_ATOMIC);
 547
 548         mlen = 0;
 549
 550         while (len32) {
 551                 if (dd->pdata->poll_irq(dd))
 552                         return -ETIMEDOUT;
 553
 554                 for (count = 0; count < min(len32, bs32); count++, offset++) {
 555                         if (!mlen) {
 556                                 sg_miter_next(&mi);
 557                                 mlen = mi.length;
 558                                 if (!mlen) {
 559                                         pr_err("sg miter failure.\n");
 560                                         return -EINVAL;
 561                                 }
 562                                 offset = 0;
 563                                 buffer = mi.addr;
 564                         }
 565                         omap_sham_write(dd, SHA_REG_DIN(dd, count),
 566                                         buffer[offset]);
 567                         mlen -= 4;
 568                 }
 569                 len32 -= min(len32, bs32);
 570         }
 571
 572         sg_miter_stop(&mi);
 573
 574         return -EINPROGRESS;
 575 }
 576
 577 static void omap_sham_dma_callback(void *param)
 578 {
 579         struct omap_sham_dev *dd = param;
 580
 581         set_bit(FLAGS_DMA_READY, &dd->flags);
 582         tasklet_schedule(&dd->done_task);
 583 }
 584
 585 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
 586                               int final)
 587 {
 588         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 589         struct dma_async_tx_descriptor *tx;
 590         struct dma_slave_config cfg;
 591         int ret;
 592
 593         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 594                                                 ctx->digcnt, length, final);
 595
 596         if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
 597                 dev_err(dd->dev, "dma_map_sg error\n");
 598                 return -EINVAL;
 599         }
 600
 601         memset(&cfg, 0, sizeof(cfg));
 602
 603         cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
 604         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 605         cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
 606
 607         ret = dmaengine_slave_config(dd->dma_lch, &cfg);
 608         if (ret) {
 609                 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
 610                 return ret;
 611         }
 612
 613         tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
 614                                      DMA_MEM_TO_DEV,
 615                                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 616
 617         if (!tx) {
 618                 dev_err(dd->dev, "prep_slave_sg failed\n");
 619                 return -EINVAL;
 620         }
 621
 622         tx->callback = omap_sham_dma_callback;
 623         tx->callback_param = dd;
 624
 625         dd->pdata->write_ctrl(dd, length, final, 1);
 626
 627         ctx->digcnt += length;
 628         ctx->total -= length;
 629
 630         if (final)
 631                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 632
 633         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 634
 635         dmaengine_submit(tx);
 636         dma_async_issue_pending(dd->dma_lch);
 637
 638         dd->pdata->trigger(dd, length);
 639
 640         return -EINPROGRESS;
 641 }
 642
 643 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
 644                                    struct scatterlist *sg, int bs, int new_len)
 645 {
 646         int n = sg_nents(sg);
 647         struct scatterlist *tmp;
 648         int offset = ctx->offset;
 649
 650         if (ctx->bufcnt)
 651                 n++;
 652
 653         ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
 654         if (!ctx->sg)
 655                 return -ENOMEM;
 656
 657         sg_init_table(ctx->sg, n);
 658
 659         tmp = ctx->sg;
 660
 661         ctx->sg_len = 0;
 662
 663         if (ctx->bufcnt) {
 664                 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
 665                 tmp = sg_next(tmp);
 666                 ctx->sg_len++;
 667         }
 668
 669         while (sg && new_len) {
 670                 int len = sg->length - offset;
 671
 672                 if (offset) {
 673                         offset -= sg->length;
 674                         if (offset < 0)
 675                                 offset = 0;
 676                 }
 677
 678                 if (new_len < len)
 679                         len = new_len;
 680
 681                 if (len > 0) {
 682                         new_len -= len;
 683                         sg_set_page(tmp, sg_page(sg), len, sg->offset);
 684                         if (new_len <= 0)
 685                                 sg_mark_end(tmp);
 686                         tmp = sg_next(tmp);
 687                         ctx->sg_len++;
 688                 }
 689
 690                 sg = sg_next(sg);
 691         }
 692
 693         set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
 694
 695         ctx->bufcnt = 0;
 696
 697         return 0;
 698 }
 699
 700 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
 701                               struct scatterlist *sg, int bs, int new_len)
 702 {
 703         int pages;
 704         void *buf;
 705         int len;
 706
 707         len = new_len + ctx->bufcnt;
 708
 709         pages = get_order(ctx->total);
 710
 711         buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
 712         if (!buf) {
 713                 pr_err("Couldn't allocate pages for unaligned cases.\n");
 714                 return -ENOMEM;
 715         }
 716
 717         if (ctx->bufcnt)
 718                 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
 719
 720         scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
 721                                  ctx->total - ctx->bufcnt, 0);
 722         sg_init_table(ctx->sgl, 1);
 723         sg_set_buf(ctx->sgl, buf, len);
 724         ctx->sg = ctx->sgl;
 725         set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
 726         ctx->sg_len = 1;
 727         ctx->bufcnt = 0;
 728         ctx->offset = 0;
 729
 730         return 0;
 731 }
 732
 733 static int omap_sham_align_sgs(struct scatterlist *sg,
 734                                int nbytes, int bs, bool final,
 735                                struct omap_sham_reqctx *rctx)
 736 {
 737         int n = 0;
 738         bool aligned = true;
 739         bool list_ok = true;
 740         struct scatterlist *sg_tmp = sg;
 741         int new_len;
 742         int offset = rctx->offset;
 743
 744         if (!sg || !sg->length || !nbytes)
 745                 return 0;
 746
 747         new_len = nbytes;
 748
 749         if (offset)
 750                 list_ok = false;
 751
 752         if (final)
 753                 new_len = DIV_ROUND_UP(new_len, bs) * bs;
 754         else
 755                 new_len = (new_len - 1) / bs * bs;
 756
 757         if (nbytes != new_len)
 758                 list_ok = false;
 759
 760         while (nbytes > 0 && sg_tmp) {
 761                 n++;
 762
 763                 if (offset < sg_tmp->length) {
 764                         if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
 765                                 aligned = false;
 766                                 break;
 767                         }
 768
 769                         if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
 770                                 aligned = false;
 771                                 break;
 772                         }
 773                 }
 774
 775                 if (offset) {
 776                         offset -= sg_tmp->length;
 777                         if (offset < 0) {
 778                                 nbytes += offset;
 779                                 offset = 0;
 780                         }
 781                 } else {
 782                         nbytes -= sg_tmp->length;
 783                 }
 784
 785                 sg_tmp = sg_next(sg_tmp);
 786
 787                 if (nbytes < 0) {
 788                         list_ok = false;
 789                         break;
 790                 }
 791         }
 792
 793         if (!aligned)
 794                 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
 795         else if (!list_ok)
 796                 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
 797
 798         rctx->sg_len = n;
 799         rctx->sg = sg;
 800
 801         return 0;
 802 }
 803
 804 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
 805 {
 806         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
 807         int bs;
 808         int ret;
 809         int nbytes;
 810         bool final = rctx->flags & BIT(FLAGS_FINUP);
 811         int xmit_len, hash_later;
 812
 813         if (!req)
 814                 return 0;
 815
 816         bs = get_block_size(rctx);
 817
 818         if (update)
 819                 nbytes = req->nbytes;
 820         else
 821                 nbytes = 0;
 822
 823         rctx->total = nbytes + rctx->bufcnt;
 824
 825         if (!rctx->total)
 826                 return 0;
 827
 828         if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
 829                 int len = bs - rctx->bufcnt % bs;
 830
 831                 if (len > nbytes)
 832                         len = nbytes;
 833                 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
 834                                          0, len, 0);
 835                 rctx->bufcnt += len;
 836                 nbytes -= len;
 837                 rctx->offset = len;
 838         }
 839
 840         if (rctx->bufcnt)
 841                 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
 842
 843         ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
 844         if (ret)
 845                 return ret;
 846
 847         xmit_len = rctx->total;
 848
 849         if (!IS_ALIGNED(xmit_len, bs)) {
 850                 if (final)
 851                         xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs;
 852                 else
 853                         xmit_len = xmit_len / bs * bs;
 854         } else if (!final) {
 855                 xmit_len -= bs;
 856         }
 857
 858         hash_later = rctx->total - xmit_len;
 859         if (hash_later < 0)
 860                 hash_later = 0;
 861
 862         if (rctx->bufcnt && nbytes) {
 863                 /* have data from previous operation and current */
 864                 sg_init_table(rctx->sgl, 2);
 865                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
 866
 867                 sg_chain(rctx->sgl, 2, req->src);
 868
 869                 rctx->sg = rctx->sgl;
 870
 871                 rctx->sg_len++;
 872         } else if (rctx->bufcnt) {
 873                 /* have buffered data only */
 874                 sg_init_table(rctx->sgl, 1);
 875                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len);
 876
 877                 rctx->sg = rctx->sgl;
 878
 879                 rctx->sg_len = 1;
 880         }
 881
 882         if (hash_later) {
 883                 int offset = 0;
 884
 885                 if (hash_later > req->nbytes) {
 886                         memcpy(rctx->buffer, rctx->buffer + xmit_len,
 887                                hash_later - req->nbytes);
 888                         offset = hash_later - req->nbytes;
 889                 }
 890
 891                 if (req->nbytes) {
 892                         scatterwalk_map_and_copy(rctx->buffer + offset,
 893                                                  req->src,
 894                                                  offset + req->nbytes -
 895                                                  hash_later, hash_later, 0);
 896                 }
 897
 898                 rctx->bufcnt = hash_later;
 899         } else {
 900                 rctx->bufcnt = 0;
 901         }
 902
 903         if (!final)
 904                 rctx->total = xmit_len;
 905
 906         return 0;
 907 }
 908
 909 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 910 {
 911         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 912
 913         dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
 914
 915         clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 916
 917         return 0;
 918 }
 919
 920 struct omap_sham_dev *omap_sham_find_dev(struct omap_sham_reqctx *ctx)
 921 {
 922         struct omap_sham_dev *dd;
 923
 924         if (ctx->dd)
 925                 return ctx->dd;
 926
 927         spin_lock_bh(&sham.lock);
 928         dd = list_first_entry(&sham.dev_list, struct omap_sham_dev, list);
 929         list_move_tail(&dd->list, &sham.dev_list);
 930         ctx->dd = dd;
 931         spin_unlock_bh(&sham.lock);
 932
 933         return dd;
 934 }
 935
 936 static int omap_sham_init(struct ahash_request *req)
 937 {
 938         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 939         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 940         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 941         struct omap_sham_dev *dd;
 942         int bs = 0;
 943
 944         ctx->dd = NULL;
 945
 946         dd = omap_sham_find_dev(ctx);
 947         if (!dd)
 948                 return -ENODEV;
 949
 950         ctx->flags = 0;
 951
 952         dev_dbg(dd->dev, "init: digest size: %d\n",
 953                 crypto_ahash_digestsize(tfm));
 954
 955         switch (crypto_ahash_digestsize(tfm)) {
 956         case MD5_DIGEST_SIZE:
 957                 ctx->flags |= FLAGS_MODE_MD5;
 958                 bs = SHA1_BLOCK_SIZE;
 959                 break;
 960         case SHA1_DIGEST_SIZE:
 961                 ctx->flags |= FLAGS_MODE_SHA1;
 962                 bs = SHA1_BLOCK_SIZE;
 963                 break;
 964         case SHA224_DIGEST_SIZE:
 965                 ctx->flags |= FLAGS_MODE_SHA224;
 966                 bs = SHA224_BLOCK_SIZE;
 967                 break;
 968         case SHA256_DIGEST_SIZE:
 969                 ctx->flags |= FLAGS_MODE_SHA256;
 970                 bs = SHA256_BLOCK_SIZE;
 971                 break;
 972         case SHA384_DIGEST_SIZE:
 973                 ctx->flags |= FLAGS_MODE_SHA384;
 974                 bs = SHA384_BLOCK_SIZE;
 975                 break;
 976         case SHA512_DIGEST_SIZE:
 977                 ctx->flags |= FLAGS_MODE_SHA512;
 978                 bs = SHA512_BLOCK_SIZE;
 979                 break;
 980         }
 981
 982         ctx->bufcnt = 0;
 983         ctx->digcnt = 0;
 984         ctx->total = 0;
 985         ctx->offset = 0;
 986         ctx->buflen = BUFLEN;
 987
 988         if (tctx->flags & BIT(FLAGS_HMAC)) {
 989                 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
 990                         struct omap_sham_hmac_ctx *bctx = tctx->base;
 991
 992                         memcpy(ctx->buffer, bctx->ipad, bs);
 993                         ctx->bufcnt = bs;
 994                 }
 995
 996                 ctx->flags |= BIT(FLAGS_HMAC);
 997         }
 998
 999         return 0;
1000
1001 }
1002
1003 static int omap_sham_update_req(struct omap_sham_dev *dd)
1004 {
1005         struct ahash_request *req = dd->req;
1006         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1007         int err;
1008         bool final = ctx->flags & BIT(FLAGS_FINUP);
1009
1010         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
1011                  ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
1012
1013         if (ctx->total < get_block_size(ctx) ||
1014             ctx->total < OMAP_SHA_DMA_THRESHOLD)
1015                 ctx->flags |= BIT(FLAGS_CPU);
1016
1017         if (ctx->flags & BIT(FLAGS_CPU))
1018                 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1019         else
1020                 err = omap_sham_xmit_dma(dd, ctx->total, final);
1021
1022         /* wait for dma completion before can take more data */
1023         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1024
1025         return err;
1026 }
1027
1028 static int omap_sham_final_req(struct omap_sham_dev *dd)
1029 {
1030         struct ahash_request *req = dd->req;
1031         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1032         int err = 0, use_dma = 1;
1033
1034         if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1035                 /*
1036                  * faster to handle last block with cpu or
1037                  * use cpu when dma is not present.
1038                  */
1039                 use_dma = 0;
1040
1041         if (use_dma)
1042                 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1043         else
1044                 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1045
1046         ctx->bufcnt = 0;
1047
1048         dev_dbg(dd->dev, "final_req: err: %d\n", err);
1049
1050         return err;
1051 }
1052
1053 static int omap_sham_finish_hmac(struct ahash_request *req)
1054 {
1055         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1056         struct omap_sham_hmac_ctx *bctx = tctx->base;
1057         int bs = crypto_shash_blocksize(bctx->shash);
1058         int ds = crypto_shash_digestsize(bctx->shash);
1059         SHASH_DESC_ON_STACK(shash, bctx->shash);
1060
1061         shash->tfm = bctx->shash;
1062         shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
1063
1064         return crypto_shash_init(shash) ?:
1065                crypto_shash_update(shash, bctx->opad, bs) ?:
1066                crypto_shash_finup(shash, req->result, ds, req->result);
1067 }
1068
1069 static int omap_sham_finish(struct ahash_request *req)
1070 {
1071         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1072         struct omap_sham_dev *dd = ctx->dd;
1073         int err = 0;
1074
1075         if (ctx->digcnt) {
1076                 omap_sham_copy_ready_hash(req);
1077                 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1078                                 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1079                         err = omap_sham_finish_hmac(req);
1080         }
1081
1082         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1083
1084         return err;
1085 }
1086
1087 static void omap_sham_finish_req(struct ahash_request *req, int err)
1088 {
1089         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1090         struct omap_sham_dev *dd = ctx->dd;
1091
1092         if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1093                 free_pages((unsigned long)sg_virt(ctx->sg),
1094                            get_order(ctx->sg->length + ctx->bufcnt));
1095
1096         if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1097                 kfree(ctx->sg);
1098
1099         ctx->sg = NULL;
1100
1101         dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1102
1103         if (!err) {
1104                 dd->pdata->copy_hash(req, 1);
1105                 if (test_bit(FLAGS_FINAL, &dd->flags))
1106                         err = omap_sham_finish(req);
1107         } else {
1108                 ctx->flags |= BIT(FLAGS_ERROR);
1109         }
1110
1111         /* atomic operation is not needed here */
1112         dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1113                         BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1114
1115         pm_runtime_mark_last_busy(dd->dev);
1116         pm_runtime_put_autosuspend(dd->dev);
1117
1118         if (req->base.complete)
1119                 req->base.complete(&req->base, err);
1120 }
1121
1122 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1123                                   struct ahash_request *req)
1124 {
1125         struct crypto_async_request *async_req, *backlog;
1126         struct omap_sham_reqctx *ctx;
1127         unsigned long flags;
1128         int err = 0, ret = 0;
1129
1130 retry:
1131         spin_lock_irqsave(&dd->lock, flags);
1132         if (req)
1133                 ret = ahash_enqueue_request(&dd->queue, req);
1134         if (test_bit(FLAGS_BUSY, &dd->flags)) {
1135                 spin_unlock_irqrestore(&dd->lock, flags);
1136                 return ret;
1137         }
1138         backlog = crypto_get_backlog(&dd->queue);
1139         async_req = crypto_dequeue_request(&dd->queue);
1140         if (async_req)
1141                 set_bit(FLAGS_BUSY, &dd->flags);
1142         spin_unlock_irqrestore(&dd->lock, flags);
1143
1144         if (!async_req)
1145                 return ret;
1146
1147         if (backlog)
1148                 backlog->complete(backlog, -EINPROGRESS);
1149
1150         req = ahash_request_cast(async_req);
1151         dd->req = req;
1152         ctx = ahash_request_ctx(req);
1153
1154         err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1155         if (err || !ctx->total)
1156                 goto err1;
1157
1158         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1159                                                 ctx->op, req->nbytes);
1160
1161         err = omap_sham_hw_init(dd);
1162         if (err)
1163                 goto err1;
1164
1165         if (ctx->digcnt)
1166                 /* request has changed - restore hash */
1167                 dd->pdata->copy_hash(req, 0);
1168
1169         if (ctx->op == OP_UPDATE) {
1170                 err = omap_sham_update_req(dd);
1171                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1172                         /* no final() after finup() */
1173                         err = omap_sham_final_req(dd);
1174         } else if (ctx->op == OP_FINAL) {
1175                 err = omap_sham_final_req(dd);
1176         }
1177 err1:
1178         dev_dbg(dd->dev, "exit, err: %d\n", err);
1179
1180         if (err != -EINPROGRESS) {
1181                 /* done_task will not finish it, so do it here */
1182                 omap_sham_finish_req(req, err);
1183                 req = NULL;
1184
1185                 /*
1186                  * Execute next request immediately if there is anything
1187                  * in queue.
1188                  */
1189                 goto retry;
1190         }
1191
1192         return ret;
1193 }
1194
1195 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1196 {
1197         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1198         struct omap_sham_dev *dd = ctx->dd;
1199
1200         ctx->op = op;
1201
1202         return omap_sham_handle_queue(dd, req);
1203 }
1204
1205 static int omap_sham_update(struct ahash_request *req)
1206 {
1207         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1208         struct omap_sham_dev *dd = omap_sham_find_dev(ctx);
1209
1210         if (!req->nbytes)
1211                 return 0;
1212
1213         if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1214                 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1215                                          0, req->nbytes, 0);
1216                 ctx->bufcnt += req->nbytes;
1217                 return 0;
1218         }
1219
1220         if (dd->polling_mode)
1221                 ctx->flags |= BIT(FLAGS_CPU);
1222
1223         return omap_sham_enqueue(req, OP_UPDATE);
1224 }
1225
1226 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1227                                   const u8 *data, unsigned int len, u8 *out)
1228 {
1229         SHASH_DESC_ON_STACK(shash, tfm);
1230
1231         shash->tfm = tfm;
1232         shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1233
1234         return crypto_shash_digest(shash, data, len, out);
1235 }
1236
1237 static int omap_sham_final_shash(struct ahash_request *req)
1238 {
1239         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1240         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1241         int offset = 0;
1242
1243         /*
1244          * If we are running HMAC on limited hardware support, skip
1245          * the ipad in the beginning of the buffer if we are going for
1246          * software fallback algorithm.
1247          */
1248         if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1249             !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1250                 offset = get_block_size(ctx);
1251
1252         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1253                                       ctx->buffer + offset,
1254                                       ctx->bufcnt - offset, req->result);
1255 }
1256
1257 static int omap_sham_final(struct ahash_request *req)
1258 {
1259         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1260
1261         ctx->flags |= BIT(FLAGS_FINUP);
1262
1263         if (ctx->flags & BIT(FLAGS_ERROR))
1264                 return 0; /* uncompleted hash is not needed */
1265
1266         /*
1267          * OMAP HW accel works only with buffers >= 9.
1268          * HMAC is always >= 9 because ipad == block size.
1269          * If buffersize is less than DMA_THRESHOLD, we use fallback
1270          * SW encoding, as using DMA + HW in this case doesn't provide
1271          * any benefit.
1272          */
1273         if (!ctx->digcnt && ctx->bufcnt < OMAP_SHA_DMA_THRESHOLD)
1274                 return omap_sham_final_shash(req);
1275         else if (ctx->bufcnt)
1276                 return omap_sham_enqueue(req, OP_FINAL);
1277
1278         /* copy ready hash (+ finalize hmac) */
1279         return omap_sham_finish(req);
1280 }
1281
1282 static int omap_sham_finup(struct ahash_request *req)
1283 {
1284         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1285         int err1, err2;
1286
1287         ctx->flags |= BIT(FLAGS_FINUP);
1288
1289         err1 = omap_sham_update(req);
1290         if (err1 == -EINPROGRESS || err1 == -EBUSY)
1291                 return err1;
1292         /*
1293          * final() has to be always called to cleanup resources
1294          * even if udpate() failed, except EINPROGRESS
1295          */
1296         err2 = omap_sham_final(req);
1297
1298         return err1 ?: err2;
1299 }
1300
1301 static int omap_sham_digest(struct ahash_request *req)
1302 {
1303         return omap_sham_init(req) ?: omap_sham_finup(req);
1304 }
1305
1306 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1307                       unsigned int keylen)
1308 {
1309         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1310         struct omap_sham_hmac_ctx *bctx = tctx->base;
1311         int bs = crypto_shash_blocksize(bctx->shash);
1312         int ds = crypto_shash_digestsize(bctx->shash);
1313         int err, i;
1314
1315         err = crypto_shash_setkey(tctx->fallback, key, keylen);
1316         if (err)
1317                 return err;
1318
1319         if (keylen > bs) {
1320                 err = omap_sham_shash_digest(bctx->shash,
1321                                 crypto_shash_get_flags(bctx->shash),
1322                                 key, keylen, bctx->ipad);
1323                 if (err)
1324                         return err;
1325                 keylen = ds;
1326         } else {
1327                 memcpy(bctx->ipad, key, keylen);
1328         }
1329
1330         memset(bctx->ipad + keylen, 0, bs - keylen);
1331
1332         if (!test_bit(FLAGS_AUTO_XOR, &sham.flags)) {
1333                 memcpy(bctx->opad, bctx->ipad, bs);
1334
1335                 for (i = 0; i < bs; i++) {
1336                         bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1337                         bctx->opad[i] ^= HMAC_OPAD_VALUE;
1338                 }
1339         }
1340
1341         return err;
1342 }
1343
1344 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1345 {
1346         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1347         const char *alg_name = crypto_tfm_alg_name(tfm);
1348
1349         /* Allocate a fallback and abort if it failed. */
1350         tctx->fallback = crypto_alloc_shash(alg_name, 0,
1351                                             CRYPTO_ALG_NEED_FALLBACK);
1352         if (IS_ERR(tctx->fallback)) {
1353                 pr_err("omap-sham: fallback driver '%s' "
1354                                 "could not be loaded.\n", alg_name);
1355                 return PTR_ERR(tctx->fallback);
1356         }
1357
1358         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1359                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
1360
1361         if (alg_base) {
1362                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1363                 tctx->flags |= BIT(FLAGS_HMAC);
1364                 bctx->shash = crypto_alloc_shash(alg_base, 0,
1365                                                 CRYPTO_ALG_NEED_FALLBACK);
1366                 if (IS_ERR(bctx->shash)) {
1367                         pr_err("omap-sham: base driver '%s' "
1368                                         "could not be loaded.\n", alg_base);
1369                         crypto_free_shash(tctx->fallback);
1370                         return PTR_ERR(bctx->shash);
1371                 }
1372
1373         }
1374
1375         return 0;
1376 }
1377
1378 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1379 {
1380         return omap_sham_cra_init_alg(tfm, NULL);
1381 }
1382
1383 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1384 {
1385         return omap_sham_cra_init_alg(tfm, "sha1");
1386 }
1387
1388 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1389 {
1390         return omap_sham_cra_init_alg(tfm, "sha224");
1391 }
1392
1393 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1394 {
1395         return omap_sham_cra_init_alg(tfm, "sha256");
1396 }
1397
1398 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1399 {
1400         return omap_sham_cra_init_alg(tfm, "md5");
1401 }
1402
1403 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1404 {
1405         return omap_sham_cra_init_alg(tfm, "sha384");
1406 }
1407
1408 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1409 {
1410         return omap_sham_cra_init_alg(tfm, "sha512");
1411 }
1412
1413 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1414 {
1415         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1416
1417         crypto_free_shash(tctx->fallback);
1418         tctx->fallback = NULL;
1419
1420         if (tctx->flags & BIT(FLAGS_HMAC)) {
1421                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1422                 crypto_free_shash(bctx->shash);
1423         }
1424 }
1425
1426 static int omap_sham_export(struct ahash_request *req, void *out)
1427 {
1428         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1429
1430         memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1431
1432         return 0;
1433 }
1434
1435 static int omap_sham_import(struct ahash_request *req, const void *in)
1436 {
1437         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1438         const struct omap_sham_reqctx *ctx_in = in;
1439
1440         memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1441
1442         return 0;
1443 }
1444
1445 static struct ahash_alg algs_sha1_md5[] = {
1446 {
1447         .init           = omap_sham_init,
1448         .update         = omap_sham_update,
1449         .final          = omap_sham_final,
1450         .finup          = omap_sham_finup,
1451         .digest         = omap_sham_digest,
1452         .halg.digestsize        = SHA1_DIGEST_SIZE,
1453         .halg.base      = {
1454                 .cra_name               = "sha1",
1455                 .cra_driver_name        = "omap-sha1",
1456                 .cra_priority           = 400,
1457                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1458                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1459                                                 CRYPTO_ALG_ASYNC |
1460                                                 CRYPTO_ALG_NEED_FALLBACK,
1461                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1462                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1463                 .cra_alignmask          = OMAP_ALIGN_MASK,
1464                 .cra_module             = THIS_MODULE,
1465                 .cra_init               = omap_sham_cra_init,
1466                 .cra_exit               = omap_sham_cra_exit,
1467         }
1468 },
1469 {
1470         .init           = omap_sham_init,
1471         .update         = omap_sham_update,
1472         .final          = omap_sham_final,
1473         .finup          = omap_sham_finup,
1474         .digest         = omap_sham_digest,
1475         .halg.digestsize        = MD5_DIGEST_SIZE,
1476         .halg.base      = {
1477                 .cra_name               = "md5",
1478                 .cra_driver_name        = "omap-md5",
1479                 .cra_priority           = 400,
1480                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1481                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1482                                                 CRYPTO_ALG_ASYNC |
1483                                                 CRYPTO_ALG_NEED_FALLBACK,
1484                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1485                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1486                 .cra_alignmask          = OMAP_ALIGN_MASK,
1487                 .cra_module             = THIS_MODULE,
1488                 .cra_init               = omap_sham_cra_init,
1489                 .cra_exit               = omap_sham_cra_exit,
1490         }
1491 },
1492 {
1493         .init           = omap_sham_init,
1494         .update         = omap_sham_update,
1495         .final          = omap_sham_final,
1496         .finup          = omap_sham_finup,
1497         .digest         = omap_sham_digest,
1498         .setkey         = omap_sham_setkey,
1499         .halg.digestsize        = SHA1_DIGEST_SIZE,
1500         .halg.base      = {
1501                 .cra_name               = "hmac(sha1)",
1502                 .cra_driver_name        = "omap-hmac-sha1",
1503                 .cra_priority           = 400,
1504                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1505                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1506                                                 CRYPTO_ALG_ASYNC |
1507                                                 CRYPTO_ALG_NEED_FALLBACK,
1508                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1509                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1510                                         sizeof(struct omap_sham_hmac_ctx),
1511                 .cra_alignmask          = OMAP_ALIGN_MASK,
1512                 .cra_module             = THIS_MODULE,
1513                 .cra_init               = omap_sham_cra_sha1_init,
1514                 .cra_exit               = omap_sham_cra_exit,
1515         }
1516 },
1517 {
1518         .init           = omap_sham_init,
1519         .update         = omap_sham_update,
1520         .final          = omap_sham_final,
1521         .finup          = omap_sham_finup,
1522         .digest         = omap_sham_digest,
1523         .setkey         = omap_sham_setkey,
1524         .halg.digestsize        = MD5_DIGEST_SIZE,
1525         .halg.base      = {
1526                 .cra_name               = "hmac(md5)",
1527                 .cra_driver_name        = "omap-hmac-md5",
1528                 .cra_priority           = 400,
1529                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1530                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1531                                                 CRYPTO_ALG_ASYNC |
1532                                                 CRYPTO_ALG_NEED_FALLBACK,
1533                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1534                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1535                                         sizeof(struct omap_sham_hmac_ctx),
1536                 .cra_alignmask          = OMAP_ALIGN_MASK,
1537                 .cra_module             = THIS_MODULE,
1538                 .cra_init               = omap_sham_cra_md5_init,
1539                 .cra_exit               = omap_sham_cra_exit,
1540         }
1541 }
1542 };
1543
1544 /* OMAP4 has some algs in addition to what OMAP2 has */
1545 static struct ahash_alg algs_sha224_sha256[] = {
1546 {
1547         .init           = omap_sham_init,
1548         .update         = omap_sham_update,
1549         .final          = omap_sham_final,
1550         .finup          = omap_sham_finup,
1551         .digest         = omap_sham_digest,
1552         .halg.digestsize        = SHA224_DIGEST_SIZE,
1553         .halg.base      = {
1554                 .cra_name               = "sha224",
1555                 .cra_driver_name        = "omap-sha224",
1556                 .cra_priority           = 400,
1557                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1558                                                 CRYPTO_ALG_ASYNC |
1559                                                 CRYPTO_ALG_NEED_FALLBACK,
1560                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1561                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1562                 .cra_alignmask          = OMAP_ALIGN_MASK,
1563                 .cra_module             = THIS_MODULE,
1564                 .cra_init               = omap_sham_cra_init,
1565                 .cra_exit               = omap_sham_cra_exit,
1566         }
1567 },
1568 {
1569         .init           = omap_sham_init,
1570         .update         = omap_sham_update,
1571         .final          = omap_sham_final,
1572         .finup          = omap_sham_finup,
1573         .digest         = omap_sham_digest,
1574         .halg.digestsize        = SHA256_DIGEST_SIZE,
1575         .halg.base      = {
1576                 .cra_name               = "sha256",
1577                 .cra_driver_name        = "omap-sha256",
1578                 .cra_priority           = 400,
1579                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1580                                                 CRYPTO_ALG_ASYNC |
1581                                                 CRYPTO_ALG_NEED_FALLBACK,
1582                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1583                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1584                 .cra_alignmask          = OMAP_ALIGN_MASK,
1585                 .cra_module             = THIS_MODULE,
1586                 .cra_init               = omap_sham_cra_init,
1587                 .cra_exit               = omap_sham_cra_exit,
1588         }
1589 },
1590 {
1591         .init           = omap_sham_init,
1592         .update         = omap_sham_update,
1593         .final          = omap_sham_final,
1594         .finup          = omap_sham_finup,
1595         .digest         = omap_sham_digest,
1596         .setkey         = omap_sham_setkey,
1597         .halg.digestsize        = SHA224_DIGEST_SIZE,
1598         .halg.base      = {
1599                 .cra_name               = "hmac(sha224)",
1600                 .cra_driver_name        = "omap-hmac-sha224",
1601                 .cra_priority           = 400,
1602                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1603                                                 CRYPTO_ALG_ASYNC |
1604                                                 CRYPTO_ALG_NEED_FALLBACK,
1605                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1606                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1607                                         sizeof(struct omap_sham_hmac_ctx),
1608                 .cra_alignmask          = OMAP_ALIGN_MASK,
1609                 .cra_module             = THIS_MODULE,
1610                 .cra_init               = omap_sham_cra_sha224_init,
1611                 .cra_exit               = omap_sham_cra_exit,
1612         }
1613 },
1614 {
1615         .init           = omap_sham_init,
1616         .update         = omap_sham_update,
1617         .final          = omap_sham_final,
1618         .finup          = omap_sham_finup,
1619         .digest         = omap_sham_digest,
1620         .setkey         = omap_sham_setkey,
1621         .halg.digestsize        = SHA256_DIGEST_SIZE,
1622         .halg.base      = {
1623                 .cra_name               = "hmac(sha256)",
1624                 .cra_driver_name        = "omap-hmac-sha256",
1625                 .cra_priority           = 400,
1626                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1627                                                 CRYPTO_ALG_ASYNC |
1628                                                 CRYPTO_ALG_NEED_FALLBACK,
1629                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1630                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1631                                         sizeof(struct omap_sham_hmac_ctx),
1632                 .cra_alignmask          = OMAP_ALIGN_MASK,
1633                 .cra_module             = THIS_MODULE,
1634                 .cra_init               = omap_sham_cra_sha256_init,
1635                 .cra_exit               = omap_sham_cra_exit,
1636         }
1637 },
1638 };
1639
1640 static struct ahash_alg algs_sha384_sha512[] = {
1641 {
1642         .init           = omap_sham_init,
1643         .update         = omap_sham_update,
1644         .final          = omap_sham_final,
1645         .finup          = omap_sham_finup,
1646         .digest         = omap_sham_digest,
1647         .halg.digestsize        = SHA384_DIGEST_SIZE,
1648         .halg.base      = {
1649                 .cra_name               = "sha384",
1650                 .cra_driver_name        = "omap-sha384",
1651                 .cra_priority           = 400,
1652                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1653                                                 CRYPTO_ALG_ASYNC |
1654                                                 CRYPTO_ALG_NEED_FALLBACK,
1655                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1656                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1657                 .cra_alignmask          = OMAP_ALIGN_MASK,
1658                 .cra_module             = THIS_MODULE,
1659                 .cra_init               = omap_sham_cra_init,
1660                 .cra_exit               = omap_sham_cra_exit,
1661         }
1662 },
1663 {
1664         .init           = omap_sham_init,
1665         .update         = omap_sham_update,
1666         .final          = omap_sham_final,
1667         .finup          = omap_sham_finup,
1668         .digest         = omap_sham_digest,
1669         .halg.digestsize        = SHA512_DIGEST_SIZE,
1670         .halg.base      = {
1671                 .cra_name               = "sha512",
1672                 .cra_driver_name        = "omap-sha512",
1673                 .cra_priority           = 400,
1674                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1675                                                 CRYPTO_ALG_ASYNC |
1676                                                 CRYPTO_ALG_NEED_FALLBACK,
1677                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1678                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1679                 .cra_alignmask          = OMAP_ALIGN_MASK,
1680                 .cra_module             = THIS_MODULE,
1681                 .cra_init               = omap_sham_cra_init,
1682                 .cra_exit               = omap_sham_cra_exit,
1683         }
1684 },
1685 {
1686         .init           = omap_sham_init,
1687         .update         = omap_sham_update,
1688         .final          = omap_sham_final,
1689         .finup          = omap_sham_finup,
1690         .digest         = omap_sham_digest,
1691         .setkey         = omap_sham_setkey,
1692         .halg.digestsize        = SHA384_DIGEST_SIZE,
1693         .halg.base      = {
1694                 .cra_name               = "hmac(sha384)",
1695                 .cra_driver_name        = "omap-hmac-sha384",
1696                 .cra_priority           = 400,
1697                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1698                                                 CRYPTO_ALG_ASYNC |
1699                                                 CRYPTO_ALG_NEED_FALLBACK,
1700                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1701                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1702                                         sizeof(struct omap_sham_hmac_ctx),
1703                 .cra_alignmask          = OMAP_ALIGN_MASK,
1704                 .cra_module             = THIS_MODULE,
1705                 .cra_init               = omap_sham_cra_sha384_init,
1706                 .cra_exit               = omap_sham_cra_exit,
1707         }
1708 },
1709 {
1710         .init           = omap_sham_init,
1711         .update         = omap_sham_update,
1712         .final          = omap_sham_final,
1713         .finup          = omap_sham_finup,
1714         .digest         = omap_sham_digest,
1715         .setkey         = omap_sham_setkey,
1716         .halg.digestsize        = SHA512_DIGEST_SIZE,
1717         .halg.base      = {
1718                 .cra_name               = "hmac(sha512)",
1719                 .cra_driver_name        = "omap-hmac-sha512",
1720                 .cra_priority           = 400,
1721                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1722                                                 CRYPTO_ALG_ASYNC |
1723                                                 CRYPTO_ALG_NEED_FALLBACK,
1724                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1725                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1726                                         sizeof(struct omap_sham_hmac_ctx),
1727                 .cra_alignmask          = OMAP_ALIGN_MASK,
1728                 .cra_module             = THIS_MODULE,
1729                 .cra_init               = omap_sham_cra_sha512_init,
1730                 .cra_exit               = omap_sham_cra_exit,
1731         }
1732 },
1733 };
1734
1735 static void omap_sham_done_task(unsigned long data)
1736 {
1737         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1738         int err = 0;
1739
1740         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1741                 omap_sham_handle_queue(dd, NULL);
1742                 return;
1743         }
1744
1745         if (test_bit(FLAGS_CPU, &dd->flags)) {
1746                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1747                         goto finish;
1748         } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1749                 if (test_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1750                         omap_sham_update_dma_stop(dd);
1751                         if (dd->err) {
1752                                 err = dd->err;
1753                                 goto finish;
1754                         }
1755                 }
1756                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1757                         /* hash or semi-hash ready */
1758                         clear_bit(FLAGS_DMA_READY, &dd->flags);
1759                                 goto finish;
1760                 }
1761         }
1762
1763         return;
1764
1765 finish:
1766         dev_dbg(dd->dev, "update done: err: %d\n", err);
1767         /* finish curent request */
1768         omap_sham_finish_req(dd->req, err);
1769
1770         /* If we are not busy, process next req */
1771         if (!test_bit(FLAGS_BUSY, &dd->flags))
1772                 omap_sham_handle_queue(dd, NULL);
1773 }
1774
1775 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1776 {
1777         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1778                 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1779         } else {
1780                 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1781                 tasklet_schedule(&dd->done_task);
1782         }
1783
1784         return IRQ_HANDLED;
1785 }
1786
1787 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1788 {
1789         struct omap_sham_dev *dd = dev_id;
1790
1791         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1792                 /* final -> allow device to go to power-saving mode */
1793                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1794
1795         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1796                                  SHA_REG_CTRL_OUTPUT_READY);
1797         omap_sham_read(dd, SHA_REG_CTRL);
1798
1799         return omap_sham_irq_common(dd);
1800 }
1801
1802 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1803 {
1804         struct omap_sham_dev *dd = dev_id;
1805
1806         omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1807
1808         return omap_sham_irq_common(dd);
1809 }
1810
1811 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1812         {
1813                 .algs_list      = algs_sha1_md5,
1814                 .size           = ARRAY_SIZE(algs_sha1_md5),
1815         },
1816 };
1817
1818 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1819         .algs_info      = omap_sham_algs_info_omap2,
1820         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1821         .flags          = BIT(FLAGS_BE32_SHA1),
1822         .digest_size    = SHA1_DIGEST_SIZE,
1823         .copy_hash      = omap_sham_copy_hash_omap2,
1824         .write_ctrl     = omap_sham_write_ctrl_omap2,
1825         .trigger        = omap_sham_trigger_omap2,
1826         .poll_irq       = omap_sham_poll_irq_omap2,
1827         .intr_hdlr      = omap_sham_irq_omap2,
1828         .idigest_ofs    = 0x00,
1829         .din_ofs        = 0x1c,
1830         .digcnt_ofs     = 0x14,
1831         .rev_ofs        = 0x5c,
1832         .mask_ofs       = 0x60,
1833         .sysstatus_ofs  = 0x64,
1834         .major_mask     = 0xf0,
1835         .major_shift    = 4,
1836         .minor_mask     = 0x0f,
1837         .minor_shift    = 0,
1838 };
1839
1840 #ifdef CONFIG_OF
1841 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1842         {
1843                 .algs_list      = algs_sha1_md5,
1844                 .size           = ARRAY_SIZE(algs_sha1_md5),
1845         },
1846         {
1847                 .algs_list      = algs_sha224_sha256,
1848                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1849         },
1850 };
1851
1852 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1853         .algs_info      = omap_sham_algs_info_omap4,
1854         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1855         .flags          = BIT(FLAGS_AUTO_XOR),
1856         .digest_size    = SHA256_DIGEST_SIZE,
1857         .copy_hash      = omap_sham_copy_hash_omap4,
1858         .write_ctrl     = omap_sham_write_ctrl_omap4,
1859         .trigger        = omap_sham_trigger_omap4,
1860         .poll_irq       = omap_sham_poll_irq_omap4,
1861         .intr_hdlr      = omap_sham_irq_omap4,
1862         .idigest_ofs    = 0x020,
1863         .odigest_ofs    = 0x0,
1864         .din_ofs        = 0x080,
1865         .digcnt_ofs     = 0x040,
1866         .rev_ofs        = 0x100,
1867         .mask_ofs       = 0x110,
1868         .sysstatus_ofs  = 0x114,
1869         .mode_ofs       = 0x44,
1870         .length_ofs     = 0x48,
1871         .major_mask     = 0x0700,
1872         .major_shift    = 8,
1873         .minor_mask     = 0x003f,
1874         .minor_shift    = 0,
1875 };
1876
1877 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1878         {
1879                 .algs_list      = algs_sha1_md5,
1880                 .size           = ARRAY_SIZE(algs_sha1_md5),
1881         },
1882         {
1883                 .algs_list      = algs_sha224_sha256,
1884                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1885         },
1886         {
1887                 .algs_list      = algs_sha384_sha512,
1888                 .size           = ARRAY_SIZE(algs_sha384_sha512),
1889         },
1890 };
1891
1892 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1893         .algs_info      = omap_sham_algs_info_omap5,
1894         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1895         .flags          = BIT(FLAGS_AUTO_XOR),
1896         .digest_size    = SHA512_DIGEST_SIZE,
1897         .copy_hash      = omap_sham_copy_hash_omap4,
1898         .write_ctrl     = omap_sham_write_ctrl_omap4,
1899         .trigger        = omap_sham_trigger_omap4,
1900         .poll_irq       = omap_sham_poll_irq_omap4,
1901         .intr_hdlr      = omap_sham_irq_omap4,
1902         .idigest_ofs    = 0x240,
1903         .odigest_ofs    = 0x200,
1904         .din_ofs        = 0x080,
1905         .digcnt_ofs     = 0x280,
1906         .rev_ofs        = 0x100,
1907         .mask_ofs       = 0x110,
1908         .sysstatus_ofs  = 0x114,
1909         .mode_ofs       = 0x284,
1910         .length_ofs     = 0x288,
1911         .major_mask     = 0x0700,
1912         .major_shift    = 8,
1913         .minor_mask     = 0x003f,
1914         .minor_shift    = 0,
1915 };
1916
1917 static const struct of_device_id omap_sham_of_match[] = {
1918         {
1919                 .compatible     = "ti,omap2-sham",
1920                 .data           = &omap_sham_pdata_omap2,
1921         },
1922         {
1923                 .compatible     = "ti,omap3-sham",
1924                 .data           = &omap_sham_pdata_omap2,
1925         },
1926         {
1927                 .compatible     = "ti,omap4-sham",
1928                 .data           = &omap_sham_pdata_omap4,
1929         },
1930         {
1931                 .compatible     = "ti,omap5-sham",
1932                 .data           = &omap_sham_pdata_omap5,
1933         },
1934         {},
1935 };
1936 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1937
1938 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1939                 struct device *dev, struct resource *res)
1940 {
1941         struct device_node *node = dev->of_node;
1942         const struct of_device_id *match;
1943         int err = 0;
1944
1945         match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
1946         if (!match) {
1947                 dev_err(dev, "no compatible OF match\n");
1948                 err = -EINVAL;
1949                 goto err;
1950         }
1951
1952         err = of_address_to_resource(node, 0, res);
1953         if (err < 0) {
1954                 dev_err(dev, "can't translate OF node address\n");
1955                 err = -EINVAL;
1956                 goto err;
1957         }
1958
1959         dd->irq = irq_of_parse_and_map(node, 0);
1960         if (!dd->irq) {
1961                 dev_err(dev, "can't translate OF irq value\n");
1962                 err = -EINVAL;
1963                 goto err;
1964         }
1965
1966         dd->pdata = match->data;
1967
1968 err:
1969         return err;
1970 }
1971 #else
1972 static const struct of_device_id omap_sham_of_match[] = {
1973         {},
1974 };
1975
1976 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1977                 struct device *dev, struct resource *res)
1978 {
1979         return -EINVAL;
1980 }
1981 #endif
1982
1983 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1984                 struct platform_device *pdev, struct resource *res)
1985 {
1986         struct device *dev = &pdev->dev;
1987         struct resource *r;
1988         int err = 0;
1989
1990         /* Get the base address */
1991         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1992         if (!r) {
1993                 dev_err(dev, "no MEM resource info\n");
1994                 err = -ENODEV;
1995                 goto err;
1996         }
1997         memcpy(res, r, sizeof(*res));
1998
1999         /* Get the IRQ */
2000         dd->irq = platform_get_irq(pdev, 0);
2001         if (dd->irq < 0) {
2002                 dev_err(dev, "no IRQ resource info\n");
2003                 err = dd->irq;
2004                 goto err;
2005         }
2006
2007         /* Only OMAP2/3 can be non-DT */
2008         dd->pdata = &omap_sham_pdata_omap2;
2009
2010 err:
2011         return err;
2012 }
2013
2014 static int omap_sham_probe(struct platform_device *pdev)
2015 {
2016         struct omap_sham_dev *dd;
2017         struct device *dev = &pdev->dev;
2018         struct resource res;
2019         dma_cap_mask_t mask;
2020         int err, i, j;
2021         u32 rev;
2022
2023         dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2024         if (dd == NULL) {
2025                 dev_err(dev, "unable to alloc data struct.\n");
2026                 err = -ENOMEM;
2027                 goto data_err;
2028         }
2029         dd->dev = dev;
2030         platform_set_drvdata(pdev, dd);
2031
2032         INIT_LIST_HEAD(&dd->list);
2033         spin_lock_init(&dd->lock);
2034         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2035         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2036
2037         err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2038                                omap_sham_get_res_pdev(dd, pdev, &res);
2039         if (err)
2040                 goto data_err;
2041
2042         dd->io_base = devm_ioremap_resource(dev, &res);
2043         if (IS_ERR(dd->io_base)) {
2044                 err = PTR_ERR(dd->io_base);
2045                 goto data_err;
2046         }
2047         dd->phys_base = res.start;
2048
2049         err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2050                                IRQF_TRIGGER_NONE, dev_name(dev), dd);
2051         if (err) {
2052                 dev_err(dev, "unable to request irq %d, err = %d\n",
2053                         dd->irq, err);
2054                 goto data_err;
2055         }
2056
2057         dma_cap_zero(mask);
2058         dma_cap_set(DMA_SLAVE, mask);
2059
2060         dd->dma_lch = dma_request_chan(dev, "rx");
2061         if (IS_ERR(dd->dma_lch)) {
2062                 err = PTR_ERR(dd->dma_lch);
2063                 if (err == -EPROBE_DEFER)
2064                         goto data_err;
2065
2066                 dd->polling_mode = 1;
2067                 dev_dbg(dev, "using polling mode instead of dma\n");
2068         }
2069
2070         dd->flags |= dd->pdata->flags;
2071         sham.flags |= dd->pdata->flags;
2072
2073         pm_runtime_use_autosuspend(dev);
2074         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2075
2076         pm_runtime_enable(dev);
2077         pm_runtime_irq_safe(dev);
2078
2079         err = pm_runtime_get_sync(dev);
2080         if (err < 0) {
2081                 dev_err(dev, "failed to get sync: %d\n", err);
2082                 goto err_pm;
2083         }
2084
2085         rev = omap_sham_read(dd, SHA_REG_REV(dd));
2086         pm_runtime_put_sync(&pdev->dev);
2087
2088         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2089                 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2090                 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2091
2092         spin_lock(&sham.lock);
2093         list_add_tail(&dd->list, &sham.dev_list);
2094         spin_unlock(&sham.lock);
2095
2096         for (i = 0; i < dd->pdata->algs_info_size; i++) {
2097                 if (dd->pdata->algs_info[i].registered)
2098                         break;
2099
2100                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2101                         struct ahash_alg *alg;
2102
2103                         alg = &dd->pdata->algs_info[i].algs_list[j];
2104                         alg->export = omap_sham_export;
2105                         alg->import = omap_sham_import;
2106                         alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2107                                               BUFLEN;
2108                         err = crypto_register_ahash(alg);
2109                         if (err)
2110                                 goto err_algs;
2111
2112                         dd->pdata->algs_info[i].registered++;
2113                 }
2114         }
2115
2116         return 0;
2117
2118 err_algs:
2119         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2120                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2121                         crypto_unregister_ahash(
2122                                         &dd->pdata->algs_info[i].algs_list[j]);
2123 err_pm:
2124         pm_runtime_disable(dev);
2125         if (!dd->polling_mode)
2126                 dma_release_channel(dd->dma_lch);
2127 data_err:
2128         dev_err(dev, "initialization failed.\n");
2129
2130         return err;
2131 }
2132
2133 static int omap_sham_remove(struct platform_device *pdev)
2134 {
2135         struct omap_sham_dev *dd;
2136         int i, j;
2137
2138         dd = platform_get_drvdata(pdev);
2139         if (!dd)
2140                 return -ENODEV;
2141         spin_lock(&sham.lock);
2142         list_del(&dd->list);
2143         spin_unlock(&sham.lock);
2144         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2145                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
2146                         crypto_unregister_ahash(
2147                                         &dd->pdata->algs_info[i].algs_list[j]);
2148                         dd->pdata->algs_info[i].registered--;
2149                 }
2150         tasklet_kill(&dd->done_task);
2151         pm_runtime_disable(&pdev->dev);
2152
2153         if (!dd->polling_mode)
2154                 dma_release_channel(dd->dma_lch);
2155
2156         return 0;
2157 }
2158
2159 #ifdef CONFIG_PM_SLEEP
2160 static int omap_sham_suspend(struct device *dev)
2161 {
2162         pm_runtime_put_sync(dev);
2163         return 0;
2164 }
2165
2166 static int omap_sham_resume(struct device *dev)
2167 {
2168         int err = pm_runtime_get_sync(dev);
2169         if (err < 0) {
2170                 dev_err(dev, "failed to get sync: %d\n", err);
2171                 return err;
2172         }
2173         return 0;
2174 }
2175 #endif
2176
2177 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2178
2179 static struct platform_driver omap_sham_driver = {
2180         .probe  = omap_sham_probe,
2181         .remove = omap_sham_remove,
2182         .driver = {
2183                 .name   = "omap-sham",
2184                 .pm     = &omap_sham_pm_ops,
2185                 .of_match_table = omap_sham_of_match,
2186         },
2187 };
2188
2189 module_platform_driver(omap_sham_driver);
2190
2191 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2192 MODULE_LICENSE("GPL v2");
2193 MODULE_AUTHOR("Dmitry Kasatkin");
2194 MODULE_ALIAS("platform:omap-sham");