drivers/crypto/omap-sham.c

   1 /*
   2  * Cryptographic API.
   3  *
   4  * Support for OMAP SHA1/MD5 HW acceleration.
   5  *
   6  * Copyright (c) 2010 Nokia Corporation
   7  * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
   8  * Copyright (c) 2011 Texas Instruments Incorporated
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as published
  12  * by the Free Software Foundation.
  13  *
  14  * Some ideas are from old omap-sha1-md5.c driver.
  15  */
  16
  17 #define pr_fmt(fmt) "%s: " fmt, __func__
  18
  19 #include <linux/err.h>
  20 #include <linux/device.h>
  21 #include <linux/module.h>
  22 #include <linux/init.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/kernel.h>
  26 #include <linux/irq.h>
  27 #include <linux/io.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/scatterlist.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/dmaengine.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/of_address.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/delay.h>
  38 #include <linux/crypto.h>
  39 #include <linux/cryptohash.h>
  40 #include <crypto/scatterwalk.h>
  41 #include <crypto/algapi.h>
  42 #include <crypto/sha.h>
  43 #include <crypto/hash.h>
  44 #include <crypto/internal/hash.h>
  45
  46 #define MD5_DIGEST_SIZE                 16
  47
  48 #define SHA_REG_IDIGEST(dd, x)          ((dd)->pdata->idigest_ofs + ((x)*0x04))
  49 #define SHA_REG_DIN(dd, x)              ((dd)->pdata->din_ofs + ((x) * 0x04))
  50 #define SHA_REG_DIGCNT(dd)              ((dd)->pdata->digcnt_ofs)
  51
  52 #define SHA_REG_ODIGEST(dd, x)          ((dd)->pdata->odigest_ofs + (x * 0x04))
  53
  54 #define SHA_REG_CTRL                    0x18
  55 #define SHA_REG_CTRL_LENGTH             (0xFFFFFFFF << 5)
  56 #define SHA_REG_CTRL_CLOSE_HASH         (1 << 4)
  57 #define SHA_REG_CTRL_ALGO_CONST         (1 << 3)
  58 #define SHA_REG_CTRL_ALGO               (1 << 2)
  59 #define SHA_REG_CTRL_INPUT_READY        (1 << 1)
  60 #define SHA_REG_CTRL_OUTPUT_READY       (1 << 0)
  61
  62 #define SHA_REG_REV(dd)                 ((dd)->pdata->rev_ofs)
  63
  64 #define SHA_REG_MASK(dd)                ((dd)->pdata->mask_ofs)
  65 #define SHA_REG_MASK_DMA_EN             (1 << 3)
  66 #define SHA_REG_MASK_IT_EN              (1 << 2)
  67 #define SHA_REG_MASK_SOFTRESET          (1 << 1)
  68 #define SHA_REG_AUTOIDLE                (1 << 0)
  69
  70 #define SHA_REG_SYSSTATUS(dd)           ((dd)->pdata->sysstatus_ofs)
  71 #define SHA_REG_SYSSTATUS_RESETDONE     (1 << 0)
  72
  73 #define SHA_REG_MODE(dd)                ((dd)->pdata->mode_ofs)
  74 #define SHA_REG_MODE_HMAC_OUTER_HASH    (1 << 7)
  75 #define SHA_REG_MODE_HMAC_KEY_PROC      (1 << 5)
  76 #define SHA_REG_MODE_CLOSE_HASH         (1 << 4)
  77 #define SHA_REG_MODE_ALGO_CONSTANT      (1 << 3)
  78
  79 #define SHA_REG_MODE_ALGO_MASK          (7 << 0)
  80 #define SHA_REG_MODE_ALGO_MD5_128       (0 << 1)
  81 #define SHA_REG_MODE_ALGO_SHA1_160      (1 << 1)
  82 #define SHA_REG_MODE_ALGO_SHA2_224      (2 << 1)
  83 #define SHA_REG_MODE_ALGO_SHA2_256      (3 << 1)
  84 #define SHA_REG_MODE_ALGO_SHA2_384      (1 << 0)
  85 #define SHA_REG_MODE_ALGO_SHA2_512      (3 << 0)
  86
  87 #define SHA_REG_LENGTH(dd)              ((dd)->pdata->length_ofs)
  88
  89 #define SHA_REG_IRQSTATUS               0x118
  90 #define SHA_REG_IRQSTATUS_CTX_RDY       (1 << 3)
  91 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
  92 #define SHA_REG_IRQSTATUS_INPUT_RDY     (1 << 1)
  93 #define SHA_REG_IRQSTATUS_OUTPUT_RDY    (1 << 0)
  94
  95 #define SHA_REG_IRQENA                  0x11C
  96 #define SHA_REG_IRQENA_CTX_RDY          (1 << 3)
  97 #define SHA_REG_IRQENA_PARTHASH_RDY     (1 << 2)
  98 #define SHA_REG_IRQENA_INPUT_RDY        (1 << 1)
  99 #define SHA_REG_IRQENA_OUTPUT_RDY       (1 << 0)
 100
 101 #define DEFAULT_TIMEOUT_INTERVAL        HZ
 102
 103 #define DEFAULT_AUTOSUSPEND_DELAY       1000
 104
 105 /* mostly device flags */
 106 #define FLAGS_BUSY              0
 107 #define FLAGS_FINAL             1
 108 #define FLAGS_DMA_ACTIVE        2
 109 #define FLAGS_OUTPUT_READY      3
 110 #define FLAGS_INIT              4
 111 #define FLAGS_CPU               5
 112 #define FLAGS_DMA_READY         6
 113 #define FLAGS_AUTO_XOR          7
 114 #define FLAGS_BE32_SHA1         8
 115 #define FLAGS_SGS_COPIED        9
 116 #define FLAGS_SGS_ALLOCED       10
 117 /* context flags */
 118 #define FLAGS_FINUP             16
 119
 120 #define FLAGS_MODE_SHIFT        18
 121 #define FLAGS_MODE_MASK         (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
 122 #define FLAGS_MODE_MD5          (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
 123 #define FLAGS_MODE_SHA1         (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
 124 #define FLAGS_MODE_SHA224       (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
 125 #define FLAGS_MODE_SHA256       (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
 126 #define FLAGS_MODE_SHA384       (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
 127 #define FLAGS_MODE_SHA512       (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
 128
 129 #define FLAGS_HMAC              21
 130 #define FLAGS_ERROR             22
 131
 132 #define OP_UPDATE               1
 133 #define OP_FINAL                2
 134
 135 #define OMAP_ALIGN_MASK         (sizeof(u32)-1)
 136 #define OMAP_ALIGNED            __attribute__((aligned(sizeof(u32))))
 137
 138 #define BUFLEN                  SHA512_BLOCK_SIZE
 139 #define OMAP_SHA_DMA_THRESHOLD  256
 140
 141 struct omap_sham_dev;
 142
 143 struct omap_sham_reqctx {
 144         struct omap_sham_dev    *dd;
 145         unsigned long           flags;
 146         unsigned long           op;
 147
 148         u8                      digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
 149         size_t                  digcnt;
 150         size_t                  bufcnt;
 151         size_t                  buflen;
 152
 153         /* walk state */
 154         struct scatterlist      *sg;
 155         struct scatterlist      sgl[2];
 156         int                     offset; /* offset in current sg */
 157         int                     sg_len;
 158         unsigned int            total;  /* total request */
 159
 160         u8                      buffer[0] OMAP_ALIGNED;
 161 };
 162
 163 struct omap_sham_hmac_ctx {
 164         struct crypto_shash     *shash;
 165         u8                      ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 166         u8                      opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
 167 };
 168
 169 struct omap_sham_ctx {
 170         unsigned long           flags;
 171
 172         /* fallback stuff */
 173         struct crypto_shash     *fallback;
 174
 175         struct omap_sham_hmac_ctx base[0];
 176 };
 177
 178 #define OMAP_SHAM_QUEUE_LENGTH  10
 179
 180 struct omap_sham_algs_info {
 181         struct ahash_alg        *algs_list;
 182         unsigned int            size;
 183         unsigned int            registered;
 184 };
 185
 186 struct omap_sham_pdata {
 187         struct omap_sham_algs_info      *algs_info;
 188         unsigned int    algs_info_size;
 189         unsigned long   flags;
 190         int             digest_size;
 191
 192         void            (*copy_hash)(struct ahash_request *req, int out);
 193         void            (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
 194                                       int final, int dma);
 195         void            (*trigger)(struct omap_sham_dev *dd, size_t length);
 196         int             (*poll_irq)(struct omap_sham_dev *dd);
 197         irqreturn_t     (*intr_hdlr)(int irq, void *dev_id);
 198
 199         u32             odigest_ofs;
 200         u32             idigest_ofs;
 201         u32             din_ofs;
 202         u32             digcnt_ofs;
 203         u32             rev_ofs;
 204         u32             mask_ofs;
 205         u32             sysstatus_ofs;
 206         u32             mode_ofs;
 207         u32             length_ofs;
 208
 209         u32             major_mask;
 210         u32             major_shift;
 211         u32             minor_mask;
 212         u32             minor_shift;
 213 };
 214
 215 struct omap_sham_dev {
 216         struct list_head        list;
 217         unsigned long           phys_base;
 218         struct device           *dev;
 219         void __iomem            *io_base;
 220         int                     irq;
 221         spinlock_t              lock;
 222         int                     err;
 223         struct dma_chan         *dma_lch;
 224         struct tasklet_struct   done_task;
 225         u8                      polling_mode;
 226         u8                      xmit_buf[BUFLEN];
 227
 228         unsigned long           flags;
 229         struct crypto_queue     queue;
 230         struct ahash_request    *req;
 231
 232         const struct omap_sham_pdata    *pdata;
 233 };
 234
 235 struct omap_sham_drv {
 236         struct list_head        dev_list;
 237         spinlock_t              lock;
 238         unsigned long           flags;
 239 };
 240
 241 static struct omap_sham_drv sham = {
 242         .dev_list = LIST_HEAD_INIT(sham.dev_list),
 243         .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
 244 };
 245
 246 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
 247 {
 248         return __raw_readl(dd->io_base + offset);
 249 }
 250
 251 static inline void omap_sham_write(struct omap_sham_dev *dd,
 252                                         u32 offset, u32 value)
 253 {
 254         __raw_writel(value, dd->io_base + offset);
 255 }
 256
 257 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
 258                                         u32 value, u32 mask)
 259 {
 260         u32 val;
 261
 262         val = omap_sham_read(dd, address);
 263         val &= ~mask;
 264         val |= value;
 265         omap_sham_write(dd, address, val);
 266 }
 267
 268 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
 269 {
 270         unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
 271
 272         while (!(omap_sham_read(dd, offset) & bit)) {
 273                 if (time_is_before_jiffies(timeout))
 274                         return -ETIMEDOUT;
 275         }
 276
 277         return 0;
 278 }
 279
 280 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
 281 {
 282         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 283         struct omap_sham_dev *dd = ctx->dd;
 284         u32 *hash = (u32 *)ctx->digest;
 285         int i;
 286
 287         for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 288                 if (out)
 289                         hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
 290                 else
 291                         omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
 292         }
 293 }
 294
 295 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
 296 {
 297         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 298         struct omap_sham_dev *dd = ctx->dd;
 299         int i;
 300
 301         if (ctx->flags & BIT(FLAGS_HMAC)) {
 302                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 303                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 304                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 305                 u32 *opad = (u32 *)bctx->opad;
 306
 307                 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
 308                         if (out)
 309                                 opad[i] = omap_sham_read(dd,
 310                                                 SHA_REG_ODIGEST(dd, i));
 311                         else
 312                                 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
 313                                                 opad[i]);
 314                 }
 315         }
 316
 317         omap_sham_copy_hash_omap2(req, out);
 318 }
 319
 320 static void omap_sham_copy_ready_hash(struct ahash_request *req)
 321 {
 322         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 323         u32 *in = (u32 *)ctx->digest;
 324         u32 *hash = (u32 *)req->result;
 325         int i, d, big_endian = 0;
 326
 327         if (!hash)
 328                 return;
 329
 330         switch (ctx->flags & FLAGS_MODE_MASK) {
 331         case FLAGS_MODE_MD5:
 332                 d = MD5_DIGEST_SIZE / sizeof(u32);
 333                 break;
 334         case FLAGS_MODE_SHA1:
 335                 /* OMAP2 SHA1 is big endian */
 336                 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
 337                         big_endian = 1;
 338                 d = SHA1_DIGEST_SIZE / sizeof(u32);
 339                 break;
 340         case FLAGS_MODE_SHA224:
 341                 d = SHA224_DIGEST_SIZE / sizeof(u32);
 342                 break;
 343         case FLAGS_MODE_SHA256:
 344                 d = SHA256_DIGEST_SIZE / sizeof(u32);
 345                 break;
 346         case FLAGS_MODE_SHA384:
 347                 d = SHA384_DIGEST_SIZE / sizeof(u32);
 348                 break;
 349         case FLAGS_MODE_SHA512:
 350                 d = SHA512_DIGEST_SIZE / sizeof(u32);
 351                 break;
 352         default:
 353                 d = 0;
 354         }
 355
 356         if (big_endian)
 357                 for (i = 0; i < d; i++)
 358                         hash[i] = be32_to_cpu(in[i]);
 359         else
 360                 for (i = 0; i < d; i++)
 361                         hash[i] = le32_to_cpu(in[i]);
 362 }
 363
 364 static int omap_sham_hw_init(struct omap_sham_dev *dd)
 365 {
 366         int err;
 367
 368         err = pm_runtime_get_sync(dd->dev);
 369         if (err < 0) {
 370                 dev_err(dd->dev, "failed to get sync: %d\n", err);
 371                 return err;
 372         }
 373
 374         if (!test_bit(FLAGS_INIT, &dd->flags)) {
 375                 set_bit(FLAGS_INIT, &dd->flags);
 376                 dd->err = 0;
 377         }
 378
 379         return 0;
 380 }
 381
 382 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
 383                                  int final, int dma)
 384 {
 385         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 386         u32 val = length << 5, mask;
 387
 388         if (likely(ctx->digcnt))
 389                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 390
 391         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 392                 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
 393                 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 394         /*
 395          * Setting ALGO_CONST only for the first iteration
 396          * and CLOSE_HASH only for the last one.
 397          */
 398         if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
 399                 val |= SHA_REG_CTRL_ALGO;
 400         if (!ctx->digcnt)
 401                 val |= SHA_REG_CTRL_ALGO_CONST;
 402         if (final)
 403                 val |= SHA_REG_CTRL_CLOSE_HASH;
 404
 405         mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
 406                         SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
 407
 408         omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
 409 }
 410
 411 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
 412 {
 413 }
 414
 415 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
 416 {
 417         return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
 418 }
 419
 420 static int get_block_size(struct omap_sham_reqctx *ctx)
 421 {
 422         int d;
 423
 424         switch (ctx->flags & FLAGS_MODE_MASK) {
 425         case FLAGS_MODE_MD5:
 426         case FLAGS_MODE_SHA1:
 427                 d = SHA1_BLOCK_SIZE;
 428                 break;
 429         case FLAGS_MODE_SHA224:
 430         case FLAGS_MODE_SHA256:
 431                 d = SHA256_BLOCK_SIZE;
 432                 break;
 433         case FLAGS_MODE_SHA384:
 434         case FLAGS_MODE_SHA512:
 435                 d = SHA512_BLOCK_SIZE;
 436                 break;
 437         default:
 438                 d = 0;
 439         }
 440
 441         return d;
 442 }
 443
 444 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
 445                                     u32 *value, int count)
 446 {
 447         for (; count--; value++, offset += 4)
 448                 omap_sham_write(dd, offset, *value);
 449 }
 450
 451 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
 452                                  int final, int dma)
 453 {
 454         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 455         u32 val, mask;
 456
 457         if (likely(ctx->digcnt))
 458                 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
 459
 460         /*
 461          * Setting ALGO_CONST only for the first iteration and
 462          * CLOSE_HASH only for the last one. Note that flags mode bits
 463          * correspond to algorithm encoding in mode register.
 464          */
 465         val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
 466         if (!ctx->digcnt) {
 467                 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
 468                 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 469                 struct omap_sham_hmac_ctx *bctx = tctx->base;
 470                 int bs, nr_dr;
 471
 472                 val |= SHA_REG_MODE_ALGO_CONSTANT;
 473
 474                 if (ctx->flags & BIT(FLAGS_HMAC)) {
 475                         bs = get_block_size(ctx);
 476                         nr_dr = bs / (2 * sizeof(u32));
 477                         val |= SHA_REG_MODE_HMAC_KEY_PROC;
 478                         omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
 479                                           (u32 *)bctx->ipad, nr_dr);
 480                         omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
 481                                           (u32 *)bctx->ipad + nr_dr, nr_dr);
 482                         ctx->digcnt += bs;
 483                 }
 484         }
 485
 486         if (final) {
 487                 val |= SHA_REG_MODE_CLOSE_HASH;
 488
 489                 if (ctx->flags & BIT(FLAGS_HMAC))
 490                         val |= SHA_REG_MODE_HMAC_OUTER_HASH;
 491         }
 492
 493         mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
 494                SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
 495                SHA_REG_MODE_HMAC_KEY_PROC;
 496
 497         dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
 498         omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
 499         omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
 500         omap_sham_write_mask(dd, SHA_REG_MASK(dd),
 501                              SHA_REG_MASK_IT_EN |
 502                                      (dma ? SHA_REG_MASK_DMA_EN : 0),
 503                              SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
 504 }
 505
 506 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
 507 {
 508         omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
 509 }
 510
 511 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
 512 {
 513         return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
 514                               SHA_REG_IRQSTATUS_INPUT_RDY);
 515 }
 516
 517 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
 518                               int final)
 519 {
 520         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 521         int count, len32, bs32, offset = 0;
 522         const u32 *buffer;
 523         int mlen;
 524         struct sg_mapping_iter mi;
 525
 526         dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
 527                                                 ctx->digcnt, length, final);
 528
 529         dd->pdata->write_ctrl(dd, length, final, 0);
 530         dd->pdata->trigger(dd, length);
 531
 532         /* should be non-zero before next lines to disable clocks later */
 533         ctx->digcnt += length;
 534         ctx->total -= length;
 535
 536         if (final)
 537                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 538
 539         set_bit(FLAGS_CPU, &dd->flags);
 540
 541         len32 = DIV_ROUND_UP(length, sizeof(u32));
 542         bs32 = get_block_size(ctx) / sizeof(u32);
 543
 544         sg_miter_start(&mi, ctx->sg, ctx->sg_len,
 545                        SG_MITER_FROM_SG | SG_MITER_ATOMIC);
 546
 547         mlen = 0;
 548
 549         while (len32) {
 550                 if (dd->pdata->poll_irq(dd))
 551                         return -ETIMEDOUT;
 552
 553                 for (count = 0; count < min(len32, bs32); count++, offset++) {
 554                         if (!mlen) {
 555                                 sg_miter_next(&mi);
 556                                 mlen = mi.length;
 557                                 if (!mlen) {
 558                                         pr_err("sg miter failure.\n");
 559                                         return -EINVAL;
 560                                 }
 561                                 offset = 0;
 562                                 buffer = mi.addr;
 563                         }
 564                         omap_sham_write(dd, SHA_REG_DIN(dd, count),
 565                                         buffer[offset]);
 566                         mlen -= 4;
 567                 }
 568                 len32 -= min(len32, bs32);
 569         }
 570
 571         sg_miter_stop(&mi);
 572
 573         return -EINPROGRESS;
 574 }
 575
 576 static void omap_sham_dma_callback(void *param)
 577 {
 578         struct omap_sham_dev *dd = param;
 579
 580         set_bit(FLAGS_DMA_READY, &dd->flags);
 581         tasklet_schedule(&dd->done_task);
 582 }
 583
 584 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
 585                               int final)
 586 {
 587         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 588         struct dma_async_tx_descriptor *tx;
 589         struct dma_slave_config cfg;
 590         int ret;
 591
 592         dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
 593                                                 ctx->digcnt, length, final);
 594
 595         if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
 596                 dev_err(dd->dev, "dma_map_sg error\n");
 597                 return -EINVAL;
 598         }
 599
 600         memset(&cfg, 0, sizeof(cfg));
 601
 602         cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
 603         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 604         cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
 605
 606         ret = dmaengine_slave_config(dd->dma_lch, &cfg);
 607         if (ret) {
 608                 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
 609                 return ret;
 610         }
 611
 612         tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
 613                                      DMA_MEM_TO_DEV,
 614                                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 615
 616         if (!tx) {
 617                 dev_err(dd->dev, "prep_slave_sg failed\n");
 618                 return -EINVAL;
 619         }
 620
 621         tx->callback = omap_sham_dma_callback;
 622         tx->callback_param = dd;
 623
 624         dd->pdata->write_ctrl(dd, length, final, 1);
 625
 626         ctx->digcnt += length;
 627         ctx->total -= length;
 628
 629         if (final)
 630                 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
 631
 632         set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 633
 634         dmaengine_submit(tx);
 635         dma_async_issue_pending(dd->dma_lch);
 636
 637         dd->pdata->trigger(dd, length);
 638
 639         return -EINPROGRESS;
 640 }
 641
 642 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
 643                                    struct scatterlist *sg, int bs, int new_len)
 644 {
 645         int n = sg_nents(sg);
 646         struct scatterlist *tmp;
 647         int offset = ctx->offset;
 648
 649         if (ctx->bufcnt)
 650                 n++;
 651
 652         ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
 653         if (!ctx->sg)
 654                 return -ENOMEM;
 655
 656         sg_init_table(ctx->sg, n);
 657
 658         tmp = ctx->sg;
 659
 660         ctx->sg_len = 0;
 661
 662         if (ctx->bufcnt) {
 663                 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
 664                 tmp = sg_next(tmp);
 665                 ctx->sg_len++;
 666         }
 667
 668         while (sg && new_len) {
 669                 int len = sg->length - offset;
 670
 671                 if (offset) {
 672                         offset -= sg->length;
 673                         if (offset < 0)
 674                                 offset = 0;
 675                 }
 676
 677                 if (new_len < len)
 678                         len = new_len;
 679
 680                 if (len > 0) {
 681                         new_len -= len;
 682                         sg_set_page(tmp, sg_page(sg), len, sg->offset);
 683                         if (new_len <= 0)
 684                                 sg_mark_end(tmp);
 685                         tmp = sg_next(tmp);
 686                         ctx->sg_len++;
 687                 }
 688
 689                 sg = sg_next(sg);
 690         }
 691
 692         set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
 693
 694         ctx->bufcnt = 0;
 695
 696         return 0;
 697 }
 698
 699 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
 700                               struct scatterlist *sg, int bs, int new_len)
 701 {
 702         int pages;
 703         void *buf;
 704         int len;
 705
 706         len = new_len + ctx->bufcnt;
 707
 708         pages = get_order(ctx->total);
 709
 710         buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
 711         if (!buf) {
 712                 pr_err("Couldn't allocate pages for unaligned cases.\n");
 713                 return -ENOMEM;
 714         }
 715
 716         if (ctx->bufcnt)
 717                 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
 718
 719         scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
 720                                  ctx->total - ctx->bufcnt, 0);
 721         sg_init_table(ctx->sgl, 1);
 722         sg_set_buf(ctx->sgl, buf, len);
 723         ctx->sg = ctx->sgl;
 724         set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
 725         ctx->sg_len = 1;
 726         ctx->bufcnt = 0;
 727         ctx->offset = 0;
 728
 729         return 0;
 730 }
 731
 732 static int omap_sham_align_sgs(struct scatterlist *sg,
 733                                int nbytes, int bs, bool final,
 734                                struct omap_sham_reqctx *rctx)
 735 {
 736         int n = 0;
 737         bool aligned = true;
 738         bool list_ok = true;
 739         struct scatterlist *sg_tmp = sg;
 740         int new_len;
 741         int offset = rctx->offset;
 742
 743         if (!sg || !sg->length || !nbytes)
 744                 return 0;
 745
 746         new_len = nbytes;
 747
 748         if (offset)
 749                 list_ok = false;
 750
 751         if (final)
 752                 new_len = DIV_ROUND_UP(new_len, bs) * bs;
 753         else
 754                 new_len = (new_len - 1) / bs * bs;
 755
 756         if (nbytes != new_len)
 757                 list_ok = false;
 758
 759         while (nbytes > 0 && sg_tmp) {
 760                 n++;
 761
 762                 if (offset < sg_tmp->length) {
 763                         if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
 764                                 aligned = false;
 765                                 break;
 766                         }
 767
 768                         if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
 769                                 aligned = false;
 770                                 break;
 771                         }
 772                 }
 773
 774                 if (offset) {
 775                         offset -= sg_tmp->length;
 776                         if (offset < 0) {
 777                                 nbytes += offset;
 778                                 offset = 0;
 779                         }
 780                 } else {
 781                         nbytes -= sg_tmp->length;
 782                 }
 783
 784                 sg_tmp = sg_next(sg_tmp);
 785
 786                 if (nbytes < 0) {
 787                         list_ok = false;
 788                         break;
 789                 }
 790         }
 791
 792         if (!aligned)
 793                 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
 794         else if (!list_ok)
 795                 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
 796
 797         rctx->sg_len = n;
 798         rctx->sg = sg;
 799
 800         return 0;
 801 }
 802
 803 static int omap_sham_prepare_request(struct ahash_request *req, bool update)
 804 {
 805         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
 806         int bs;
 807         int ret;
 808         int nbytes;
 809         bool final = rctx->flags & BIT(FLAGS_FINUP);
 810         int xmit_len, hash_later;
 811
 812         if (!req)
 813                 return 0;
 814
 815         bs = get_block_size(rctx);
 816
 817         if (update)
 818                 nbytes = req->nbytes;
 819         else
 820                 nbytes = 0;
 821
 822         rctx->total = nbytes + rctx->bufcnt;
 823
 824         if (!rctx->total)
 825                 return 0;
 826
 827         if (nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
 828                 int len = bs - rctx->bufcnt % bs;
 829
 830                 if (len > nbytes)
 831                         len = nbytes;
 832                 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
 833                                          0, len, 0);
 834                 rctx->bufcnt += len;
 835                 nbytes -= len;
 836                 rctx->offset = len;
 837         }
 838
 839         if (rctx->bufcnt)
 840                 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
 841
 842         ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
 843         if (ret)
 844                 return ret;
 845
 846         xmit_len = rctx->total;
 847
 848         if (!IS_ALIGNED(xmit_len, bs)) {
 849                 if (final)
 850                         xmit_len = DIV_ROUND_UP(xmit_len, bs) * bs;
 851                 else
 852                         xmit_len = xmit_len / bs * bs;
 853         } else if (!final) {
 854                 xmit_len -= bs;
 855         }
 856
 857         hash_later = rctx->total - xmit_len;
 858         if (hash_later < 0)
 859                 hash_later = 0;
 860
 861         if (rctx->bufcnt && nbytes) {
 862                 /* have data from previous operation and current */
 863                 sg_init_table(rctx->sgl, 2);
 864                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
 865
 866                 sg_chain(rctx->sgl, 2, req->src);
 867
 868                 rctx->sg = rctx->sgl;
 869
 870                 rctx->sg_len++;
 871         } else if (rctx->bufcnt) {
 872                 /* have buffered data only */
 873                 sg_init_table(rctx->sgl, 1);
 874                 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, xmit_len);
 875
 876                 rctx->sg = rctx->sgl;
 877
 878                 rctx->sg_len = 1;
 879         }
 880
 881         if (hash_later) {
 882                 int offset = 0;
 883
 884                 if (hash_later > req->nbytes) {
 885                         memcpy(rctx->buffer, rctx->buffer + xmit_len,
 886                                hash_later - req->nbytes);
 887                         offset = hash_later - req->nbytes;
 888                 }
 889
 890                 if (req->nbytes) {
 891                         scatterwalk_map_and_copy(rctx->buffer + offset,
 892                                                  req->src,
 893                                                  offset + req->nbytes -
 894                                                  hash_later, hash_later, 0);
 895                 }
 896
 897                 rctx->bufcnt = hash_later;
 898         } else {
 899                 rctx->bufcnt = 0;
 900         }
 901
 902         if (!final)
 903                 rctx->total = xmit_len;
 904
 905         return 0;
 906 }
 907
 908 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
 909 {
 910         struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
 911
 912         dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
 913
 914         clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
 915
 916         return 0;
 917 }
 918
 919 struct omap_sham_dev *omap_sham_find_dev(struct omap_sham_reqctx *ctx)
 920 {
 921         struct omap_sham_dev *dd;
 922
 923         if (ctx->dd)
 924                 return ctx->dd;
 925
 926         spin_lock_bh(&sham.lock);
 927         dd = list_first_entry(&sham.dev_list, struct omap_sham_dev, list);
 928         list_move_tail(&dd->list, &sham.dev_list);
 929         ctx->dd = dd;
 930         spin_unlock_bh(&sham.lock);
 931
 932         return dd;
 933 }
 934
 935 static int omap_sham_init(struct ahash_request *req)
 936 {
 937         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 938         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
 939         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
 940         struct omap_sham_dev *dd;
 941         int bs = 0;
 942
 943         ctx->dd = NULL;
 944
 945         dd = omap_sham_find_dev(ctx);
 946         if (!dd)
 947                 return -ENODEV;
 948
 949         ctx->flags = 0;
 950
 951         dev_dbg(dd->dev, "init: digest size: %d\n",
 952                 crypto_ahash_digestsize(tfm));
 953
 954         switch (crypto_ahash_digestsize(tfm)) {
 955         case MD5_DIGEST_SIZE:
 956                 ctx->flags |= FLAGS_MODE_MD5;
 957                 bs = SHA1_BLOCK_SIZE;
 958                 break;
 959         case SHA1_DIGEST_SIZE:
 960                 ctx->flags |= FLAGS_MODE_SHA1;
 961                 bs = SHA1_BLOCK_SIZE;
 962                 break;
 963         case SHA224_DIGEST_SIZE:
 964                 ctx->flags |= FLAGS_MODE_SHA224;
 965                 bs = SHA224_BLOCK_SIZE;
 966                 break;
 967         case SHA256_DIGEST_SIZE:
 968                 ctx->flags |= FLAGS_MODE_SHA256;
 969                 bs = SHA256_BLOCK_SIZE;
 970                 break;
 971         case SHA384_DIGEST_SIZE:
 972                 ctx->flags |= FLAGS_MODE_SHA384;
 973                 bs = SHA384_BLOCK_SIZE;
 974                 break;
 975         case SHA512_DIGEST_SIZE:
 976                 ctx->flags |= FLAGS_MODE_SHA512;
 977                 bs = SHA512_BLOCK_SIZE;
 978                 break;
 979         }
 980
 981         ctx->bufcnt = 0;
 982         ctx->digcnt = 0;
 983         ctx->total = 0;
 984         ctx->offset = 0;
 985         ctx->buflen = BUFLEN;
 986
 987         if (tctx->flags & BIT(FLAGS_HMAC)) {
 988                 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
 989                         struct omap_sham_hmac_ctx *bctx = tctx->base;
 990
 991                         memcpy(ctx->buffer, bctx->ipad, bs);
 992                         ctx->bufcnt = bs;
 993                 }
 994
 995                 ctx->flags |= BIT(FLAGS_HMAC);
 996         }
 997
 998         return 0;
 999
1000 }
1001
1002 static int omap_sham_update_req(struct omap_sham_dev *dd)
1003 {
1004         struct ahash_request *req = dd->req;
1005         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1006         int err;
1007         bool final = ctx->flags & BIT(FLAGS_FINUP);
1008
1009         dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
1010                  ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
1011
1012         if (ctx->total < get_block_size(ctx) ||
1013             ctx->total < OMAP_SHA_DMA_THRESHOLD)
1014                 ctx->flags |= BIT(FLAGS_CPU);
1015
1016         if (ctx->flags & BIT(FLAGS_CPU))
1017                 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1018         else
1019                 err = omap_sham_xmit_dma(dd, ctx->total, final);
1020
1021         /* wait for dma completion before can take more data */
1022         dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
1023
1024         return err;
1025 }
1026
1027 static int omap_sham_final_req(struct omap_sham_dev *dd)
1028 {
1029         struct ahash_request *req = dd->req;
1030         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1031         int err = 0, use_dma = 1;
1032
1033         if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1034                 /*
1035                  * faster to handle last block with cpu or
1036                  * use cpu when dma is not present.
1037                  */
1038                 use_dma = 0;
1039
1040         if (use_dma)
1041                 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1042         else
1043                 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1044
1045         ctx->bufcnt = 0;
1046
1047         dev_dbg(dd->dev, "final_req: err: %d\n", err);
1048
1049         return err;
1050 }
1051
1052 static int omap_sham_finish_hmac(struct ahash_request *req)
1053 {
1054         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1055         struct omap_sham_hmac_ctx *bctx = tctx->base;
1056         int bs = crypto_shash_blocksize(bctx->shash);
1057         int ds = crypto_shash_digestsize(bctx->shash);
1058         SHASH_DESC_ON_STACK(shash, bctx->shash);
1059
1060         shash->tfm = bctx->shash;
1061         shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
1062
1063         return crypto_shash_init(shash) ?:
1064                crypto_shash_update(shash, bctx->opad, bs) ?:
1065                crypto_shash_finup(shash, req->result, ds, req->result);
1066 }
1067
1068 static int omap_sham_finish(struct ahash_request *req)
1069 {
1070         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1071         struct omap_sham_dev *dd = ctx->dd;
1072         int err = 0;
1073
1074         if (ctx->digcnt) {
1075                 omap_sham_copy_ready_hash(req);
1076                 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1077                                 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1078                         err = omap_sham_finish_hmac(req);
1079         }
1080
1081         dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
1082
1083         return err;
1084 }
1085
1086 static void omap_sham_finish_req(struct ahash_request *req, int err)
1087 {
1088         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1089         struct omap_sham_dev *dd = ctx->dd;
1090
1091         if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1092                 free_pages((unsigned long)sg_virt(ctx->sg),
1093                            get_order(ctx->sg->length + ctx->bufcnt));
1094
1095         if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1096                 kfree(ctx->sg);
1097
1098         ctx->sg = NULL;
1099
1100         dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED));
1101
1102         if (!err) {
1103                 dd->pdata->copy_hash(req, 1);
1104                 if (test_bit(FLAGS_FINAL, &dd->flags))
1105                         err = omap_sham_finish(req);
1106         } else {
1107                 ctx->flags |= BIT(FLAGS_ERROR);
1108         }
1109
1110         /* atomic operation is not needed here */
1111         dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1112                         BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1113
1114         pm_runtime_mark_last_busy(dd->dev);
1115         pm_runtime_put_autosuspend(dd->dev);
1116
1117         if (req->base.complete)
1118                 req->base.complete(&req->base, err);
1119 }
1120
1121 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1122                                   struct ahash_request *req)
1123 {
1124         struct crypto_async_request *async_req, *backlog;
1125         struct omap_sham_reqctx *ctx;
1126         unsigned long flags;
1127         int err = 0, ret = 0;
1128
1129 retry:
1130         spin_lock_irqsave(&dd->lock, flags);
1131         if (req)
1132                 ret = ahash_enqueue_request(&dd->queue, req);
1133         if (test_bit(FLAGS_BUSY, &dd->flags)) {
1134                 spin_unlock_irqrestore(&dd->lock, flags);
1135                 return ret;
1136         }
1137         backlog = crypto_get_backlog(&dd->queue);
1138         async_req = crypto_dequeue_request(&dd->queue);
1139         if (async_req)
1140                 set_bit(FLAGS_BUSY, &dd->flags);
1141         spin_unlock_irqrestore(&dd->lock, flags);
1142
1143         if (!async_req)
1144                 return ret;
1145
1146         if (backlog)
1147                 backlog->complete(backlog, -EINPROGRESS);
1148
1149         req = ahash_request_cast(async_req);
1150         dd->req = req;
1151         ctx = ahash_request_ctx(req);
1152
1153         err = omap_sham_prepare_request(req, ctx->op == OP_UPDATE);
1154         if (err || !ctx->total)
1155                 goto err1;
1156
1157         dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1158                                                 ctx->op, req->nbytes);
1159
1160         err = omap_sham_hw_init(dd);
1161         if (err)
1162                 goto err1;
1163
1164         if (ctx->digcnt)
1165                 /* request has changed - restore hash */
1166                 dd->pdata->copy_hash(req, 0);
1167
1168         if (ctx->op == OP_UPDATE) {
1169                 err = omap_sham_update_req(dd);
1170                 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
1171                         /* no final() after finup() */
1172                         err = omap_sham_final_req(dd);
1173         } else if (ctx->op == OP_FINAL) {
1174                 err = omap_sham_final_req(dd);
1175         }
1176 err1:
1177         dev_dbg(dd->dev, "exit, err: %d\n", err);
1178
1179         if (err != -EINPROGRESS) {
1180                 /* done_task will not finish it, so do it here */
1181                 omap_sham_finish_req(req, err);
1182                 req = NULL;
1183
1184                 /*
1185                  * Execute next request immediately if there is anything
1186                  * in queue.
1187                  */
1188                 goto retry;
1189         }
1190
1191         return ret;
1192 }
1193
1194 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1195 {
1196         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1197         struct omap_sham_dev *dd = ctx->dd;
1198
1199         ctx->op = op;
1200
1201         return omap_sham_handle_queue(dd, req);
1202 }
1203
1204 static int omap_sham_update(struct ahash_request *req)
1205 {
1206         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1207         struct omap_sham_dev *dd = omap_sham_find_dev(ctx);
1208
1209         if (!req->nbytes)
1210                 return 0;
1211
1212         if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1213                 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1214                                          0, req->nbytes, 0);
1215                 ctx->bufcnt += req->nbytes;
1216                 return 0;
1217         }
1218
1219         if (dd->polling_mode)
1220                 ctx->flags |= BIT(FLAGS_CPU);
1221
1222         return omap_sham_enqueue(req, OP_UPDATE);
1223 }
1224
1225 static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
1226                                   const u8 *data, unsigned int len, u8 *out)
1227 {
1228         SHASH_DESC_ON_STACK(shash, tfm);
1229
1230         shash->tfm = tfm;
1231         shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
1232
1233         return crypto_shash_digest(shash, data, len, out);
1234 }
1235
1236 static int omap_sham_final_shash(struct ahash_request *req)
1237 {
1238         struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1239         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1240         int offset = 0;
1241
1242         /*
1243          * If we are running HMAC on limited hardware support, skip
1244          * the ipad in the beginning of the buffer if we are going for
1245          * software fallback algorithm.
1246          */
1247         if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1248             !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1249                 offset = get_block_size(ctx);
1250
1251         return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1252                                       ctx->buffer + offset,
1253                                       ctx->bufcnt - offset, req->result);
1254 }
1255
1256 static int omap_sham_final(struct ahash_request *req)
1257 {
1258         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1259
1260         ctx->flags |= BIT(FLAGS_FINUP);
1261
1262         if (ctx->flags & BIT(FLAGS_ERROR))
1263                 return 0; /* uncompleted hash is not needed */
1264
1265         /*
1266          * OMAP HW accel works only with buffers >= 9.
1267          * HMAC is always >= 9 because ipad == block size.
1268          * If buffersize is less than DMA_THRESHOLD, we use fallback
1269          * SW encoding, as using DMA + HW in this case doesn't provide
1270          * any benefit.
1271          */
1272         if (!ctx->digcnt && ctx->bufcnt < OMAP_SHA_DMA_THRESHOLD)
1273                 return omap_sham_final_shash(req);
1274         else if (ctx->bufcnt)
1275                 return omap_sham_enqueue(req, OP_FINAL);
1276
1277         /* copy ready hash (+ finalize hmac) */
1278         return omap_sham_finish(req);
1279 }
1280
1281 static int omap_sham_finup(struct ahash_request *req)
1282 {
1283         struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1284         int err1, err2;
1285
1286         ctx->flags |= BIT(FLAGS_FINUP);
1287
1288         err1 = omap_sham_update(req);
1289         if (err1 == -EINPROGRESS || err1 == -EBUSY)
1290                 return err1;
1291         /*
1292          * final() has to be always called to cleanup resources
1293          * even if udpate() failed, except EINPROGRESS
1294          */
1295         err2 = omap_sham_final(req);
1296
1297         return err1 ?: err2;
1298 }
1299
1300 static int omap_sham_digest(struct ahash_request *req)
1301 {
1302         return omap_sham_init(req) ?: omap_sham_finup(req);
1303 }
1304
1305 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1306                       unsigned int keylen)
1307 {
1308         struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1309         struct omap_sham_hmac_ctx *bctx = tctx->base;
1310         int bs = crypto_shash_blocksize(bctx->shash);
1311         int ds = crypto_shash_digestsize(bctx->shash);
1312         int err, i;
1313
1314         err = crypto_shash_setkey(tctx->fallback, key, keylen);
1315         if (err)
1316                 return err;
1317
1318         if (keylen > bs) {
1319                 err = omap_sham_shash_digest(bctx->shash,
1320                                 crypto_shash_get_flags(bctx->shash),
1321                                 key, keylen, bctx->ipad);
1322                 if (err)
1323                         return err;
1324                 keylen = ds;
1325         } else {
1326                 memcpy(bctx->ipad, key, keylen);
1327         }
1328
1329         memset(bctx->ipad + keylen, 0, bs - keylen);
1330
1331         if (!test_bit(FLAGS_AUTO_XOR, &sham.flags)) {
1332                 memcpy(bctx->opad, bctx->ipad, bs);
1333
1334                 for (i = 0; i < bs; i++) {
1335                         bctx->ipad[i] ^= 0x36;
1336                         bctx->opad[i] ^= 0x5c;
1337                 }
1338         }
1339
1340         return err;
1341 }
1342
1343 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1344 {
1345         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1346         const char *alg_name = crypto_tfm_alg_name(tfm);
1347
1348         /* Allocate a fallback and abort if it failed. */
1349         tctx->fallback = crypto_alloc_shash(alg_name, 0,
1350                                             CRYPTO_ALG_NEED_FALLBACK);
1351         if (IS_ERR(tctx->fallback)) {
1352                 pr_err("omap-sham: fallback driver '%s' "
1353                                 "could not be loaded.\n", alg_name);
1354                 return PTR_ERR(tctx->fallback);
1355         }
1356
1357         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1358                                  sizeof(struct omap_sham_reqctx) + BUFLEN);
1359
1360         if (alg_base) {
1361                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1362                 tctx->flags |= BIT(FLAGS_HMAC);
1363                 bctx->shash = crypto_alloc_shash(alg_base, 0,
1364                                                 CRYPTO_ALG_NEED_FALLBACK);
1365                 if (IS_ERR(bctx->shash)) {
1366                         pr_err("omap-sham: base driver '%s' "
1367                                         "could not be loaded.\n", alg_base);
1368                         crypto_free_shash(tctx->fallback);
1369                         return PTR_ERR(bctx->shash);
1370                 }
1371
1372         }
1373
1374         return 0;
1375 }
1376
1377 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1378 {
1379         return omap_sham_cra_init_alg(tfm, NULL);
1380 }
1381
1382 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1383 {
1384         return omap_sham_cra_init_alg(tfm, "sha1");
1385 }
1386
1387 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1388 {
1389         return omap_sham_cra_init_alg(tfm, "sha224");
1390 }
1391
1392 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1393 {
1394         return omap_sham_cra_init_alg(tfm, "sha256");
1395 }
1396
1397 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1398 {
1399         return omap_sham_cra_init_alg(tfm, "md5");
1400 }
1401
1402 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1403 {
1404         return omap_sham_cra_init_alg(tfm, "sha384");
1405 }
1406
1407 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1408 {
1409         return omap_sham_cra_init_alg(tfm, "sha512");
1410 }
1411
1412 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1413 {
1414         struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1415
1416         crypto_free_shash(tctx->fallback);
1417         tctx->fallback = NULL;
1418
1419         if (tctx->flags & BIT(FLAGS_HMAC)) {
1420                 struct omap_sham_hmac_ctx *bctx = tctx->base;
1421                 crypto_free_shash(bctx->shash);
1422         }
1423 }
1424
1425 static int omap_sham_export(struct ahash_request *req, void *out)
1426 {
1427         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1428
1429         memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1430
1431         return 0;
1432 }
1433
1434 static int omap_sham_import(struct ahash_request *req, const void *in)
1435 {
1436         struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1437         const struct omap_sham_reqctx *ctx_in = in;
1438
1439         memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1440
1441         return 0;
1442 }
1443
1444 static struct ahash_alg algs_sha1_md5[] = {
1445 {
1446         .init           = omap_sham_init,
1447         .update         = omap_sham_update,
1448         .final          = omap_sham_final,
1449         .finup          = omap_sham_finup,
1450         .digest         = omap_sham_digest,
1451         .halg.digestsize        = SHA1_DIGEST_SIZE,
1452         .halg.base      = {
1453                 .cra_name               = "sha1",
1454                 .cra_driver_name        = "omap-sha1",
1455                 .cra_priority           = 400,
1456                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1457                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1458                                                 CRYPTO_ALG_ASYNC |
1459                                                 CRYPTO_ALG_NEED_FALLBACK,
1460                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1461                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1462                 .cra_alignmask          = OMAP_ALIGN_MASK,
1463                 .cra_module             = THIS_MODULE,
1464                 .cra_init               = omap_sham_cra_init,
1465                 .cra_exit               = omap_sham_cra_exit,
1466         }
1467 },
1468 {
1469         .init           = omap_sham_init,
1470         .update         = omap_sham_update,
1471         .final          = omap_sham_final,
1472         .finup          = omap_sham_finup,
1473         .digest         = omap_sham_digest,
1474         .halg.digestsize        = MD5_DIGEST_SIZE,
1475         .halg.base      = {
1476                 .cra_name               = "md5",
1477                 .cra_driver_name        = "omap-md5",
1478                 .cra_priority           = 400,
1479                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1480                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1481                                                 CRYPTO_ALG_ASYNC |
1482                                                 CRYPTO_ALG_NEED_FALLBACK,
1483                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1484                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1485                 .cra_alignmask          = OMAP_ALIGN_MASK,
1486                 .cra_module             = THIS_MODULE,
1487                 .cra_init               = omap_sham_cra_init,
1488                 .cra_exit               = omap_sham_cra_exit,
1489         }
1490 },
1491 {
1492         .init           = omap_sham_init,
1493         .update         = omap_sham_update,
1494         .final          = omap_sham_final,
1495         .finup          = omap_sham_finup,
1496         .digest         = omap_sham_digest,
1497         .setkey         = omap_sham_setkey,
1498         .halg.digestsize        = SHA1_DIGEST_SIZE,
1499         .halg.base      = {
1500                 .cra_name               = "hmac(sha1)",
1501                 .cra_driver_name        = "omap-hmac-sha1",
1502                 .cra_priority           = 400,
1503                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1504                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1505                                                 CRYPTO_ALG_ASYNC |
1506                                                 CRYPTO_ALG_NEED_FALLBACK,
1507                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1508                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1509                                         sizeof(struct omap_sham_hmac_ctx),
1510                 .cra_alignmask          = OMAP_ALIGN_MASK,
1511                 .cra_module             = THIS_MODULE,
1512                 .cra_init               = omap_sham_cra_sha1_init,
1513                 .cra_exit               = omap_sham_cra_exit,
1514         }
1515 },
1516 {
1517         .init           = omap_sham_init,
1518         .update         = omap_sham_update,
1519         .final          = omap_sham_final,
1520         .finup          = omap_sham_finup,
1521         .digest         = omap_sham_digest,
1522         .setkey         = omap_sham_setkey,
1523         .halg.digestsize        = MD5_DIGEST_SIZE,
1524         .halg.base      = {
1525                 .cra_name               = "hmac(md5)",
1526                 .cra_driver_name        = "omap-hmac-md5",
1527                 .cra_priority           = 400,
1528                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1529                                                 CRYPTO_ALG_KERN_DRIVER_ONLY |
1530                                                 CRYPTO_ALG_ASYNC |
1531                                                 CRYPTO_ALG_NEED_FALLBACK,
1532                 .cra_blocksize          = SHA1_BLOCK_SIZE,
1533                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1534                                         sizeof(struct omap_sham_hmac_ctx),
1535                 .cra_alignmask          = OMAP_ALIGN_MASK,
1536                 .cra_module             = THIS_MODULE,
1537                 .cra_init               = omap_sham_cra_md5_init,
1538                 .cra_exit               = omap_sham_cra_exit,
1539         }
1540 }
1541 };
1542
1543 /* OMAP4 has some algs in addition to what OMAP2 has */
1544 static struct ahash_alg algs_sha224_sha256[] = {
1545 {
1546         .init           = omap_sham_init,
1547         .update         = omap_sham_update,
1548         .final          = omap_sham_final,
1549         .finup          = omap_sham_finup,
1550         .digest         = omap_sham_digest,
1551         .halg.digestsize        = SHA224_DIGEST_SIZE,
1552         .halg.base      = {
1553                 .cra_name               = "sha224",
1554                 .cra_driver_name        = "omap-sha224",
1555                 .cra_priority           = 400,
1556                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1557                                                 CRYPTO_ALG_ASYNC |
1558                                                 CRYPTO_ALG_NEED_FALLBACK,
1559                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1560                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1561                 .cra_alignmask          = OMAP_ALIGN_MASK,
1562                 .cra_module             = THIS_MODULE,
1563                 .cra_init               = omap_sham_cra_init,
1564                 .cra_exit               = omap_sham_cra_exit,
1565         }
1566 },
1567 {
1568         .init           = omap_sham_init,
1569         .update         = omap_sham_update,
1570         .final          = omap_sham_final,
1571         .finup          = omap_sham_finup,
1572         .digest         = omap_sham_digest,
1573         .halg.digestsize        = SHA256_DIGEST_SIZE,
1574         .halg.base      = {
1575                 .cra_name               = "sha256",
1576                 .cra_driver_name        = "omap-sha256",
1577                 .cra_priority           = 400,
1578                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1579                                                 CRYPTO_ALG_ASYNC |
1580                                                 CRYPTO_ALG_NEED_FALLBACK,
1581                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1582                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1583                 .cra_alignmask          = OMAP_ALIGN_MASK,
1584                 .cra_module             = THIS_MODULE,
1585                 .cra_init               = omap_sham_cra_init,
1586                 .cra_exit               = omap_sham_cra_exit,
1587         }
1588 },
1589 {
1590         .init           = omap_sham_init,
1591         .update         = omap_sham_update,
1592         .final          = omap_sham_final,
1593         .finup          = omap_sham_finup,
1594         .digest         = omap_sham_digest,
1595         .setkey         = omap_sham_setkey,
1596         .halg.digestsize        = SHA224_DIGEST_SIZE,
1597         .halg.base      = {
1598                 .cra_name               = "hmac(sha224)",
1599                 .cra_driver_name        = "omap-hmac-sha224",
1600                 .cra_priority           = 400,
1601                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1602                                                 CRYPTO_ALG_ASYNC |
1603                                                 CRYPTO_ALG_NEED_FALLBACK,
1604                 .cra_blocksize          = SHA224_BLOCK_SIZE,
1605                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1606                                         sizeof(struct omap_sham_hmac_ctx),
1607                 .cra_alignmask          = OMAP_ALIGN_MASK,
1608                 .cra_module             = THIS_MODULE,
1609                 .cra_init               = omap_sham_cra_sha224_init,
1610                 .cra_exit               = omap_sham_cra_exit,
1611         }
1612 },
1613 {
1614         .init           = omap_sham_init,
1615         .update         = omap_sham_update,
1616         .final          = omap_sham_final,
1617         .finup          = omap_sham_finup,
1618         .digest         = omap_sham_digest,
1619         .setkey         = omap_sham_setkey,
1620         .halg.digestsize        = SHA256_DIGEST_SIZE,
1621         .halg.base      = {
1622                 .cra_name               = "hmac(sha256)",
1623                 .cra_driver_name        = "omap-hmac-sha256",
1624                 .cra_priority           = 400,
1625                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1626                                                 CRYPTO_ALG_ASYNC |
1627                                                 CRYPTO_ALG_NEED_FALLBACK,
1628                 .cra_blocksize          = SHA256_BLOCK_SIZE,
1629                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1630                                         sizeof(struct omap_sham_hmac_ctx),
1631                 .cra_alignmask          = OMAP_ALIGN_MASK,
1632                 .cra_module             = THIS_MODULE,
1633                 .cra_init               = omap_sham_cra_sha256_init,
1634                 .cra_exit               = omap_sham_cra_exit,
1635         }
1636 },
1637 };
1638
1639 static struct ahash_alg algs_sha384_sha512[] = {
1640 {
1641         .init           = omap_sham_init,
1642         .update         = omap_sham_update,
1643         .final          = omap_sham_final,
1644         .finup          = omap_sham_finup,
1645         .digest         = omap_sham_digest,
1646         .halg.digestsize        = SHA384_DIGEST_SIZE,
1647         .halg.base      = {
1648                 .cra_name               = "sha384",
1649                 .cra_driver_name        = "omap-sha384",
1650                 .cra_priority           = 400,
1651                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1652                                                 CRYPTO_ALG_ASYNC |
1653                                                 CRYPTO_ALG_NEED_FALLBACK,
1654                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1655                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1656                 .cra_alignmask          = OMAP_ALIGN_MASK,
1657                 .cra_module             = THIS_MODULE,
1658                 .cra_init               = omap_sham_cra_init,
1659                 .cra_exit               = omap_sham_cra_exit,
1660         }
1661 },
1662 {
1663         .init           = omap_sham_init,
1664         .update         = omap_sham_update,
1665         .final          = omap_sham_final,
1666         .finup          = omap_sham_finup,
1667         .digest         = omap_sham_digest,
1668         .halg.digestsize        = SHA512_DIGEST_SIZE,
1669         .halg.base      = {
1670                 .cra_name               = "sha512",
1671                 .cra_driver_name        = "omap-sha512",
1672                 .cra_priority           = 400,
1673                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1674                                                 CRYPTO_ALG_ASYNC |
1675                                                 CRYPTO_ALG_NEED_FALLBACK,
1676                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1677                 .cra_ctxsize            = sizeof(struct omap_sham_ctx),
1678                 .cra_alignmask          = OMAP_ALIGN_MASK,
1679                 .cra_module             = THIS_MODULE,
1680                 .cra_init               = omap_sham_cra_init,
1681                 .cra_exit               = omap_sham_cra_exit,
1682         }
1683 },
1684 {
1685         .init           = omap_sham_init,
1686         .update         = omap_sham_update,
1687         .final          = omap_sham_final,
1688         .finup          = omap_sham_finup,
1689         .digest         = omap_sham_digest,
1690         .setkey         = omap_sham_setkey,
1691         .halg.digestsize        = SHA384_DIGEST_SIZE,
1692         .halg.base      = {
1693                 .cra_name               = "hmac(sha384)",
1694                 .cra_driver_name        = "omap-hmac-sha384",
1695                 .cra_priority           = 400,
1696                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1697                                                 CRYPTO_ALG_ASYNC |
1698                                                 CRYPTO_ALG_NEED_FALLBACK,
1699                 .cra_blocksize          = SHA384_BLOCK_SIZE,
1700                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1701                                         sizeof(struct omap_sham_hmac_ctx),
1702                 .cra_alignmask          = OMAP_ALIGN_MASK,
1703                 .cra_module             = THIS_MODULE,
1704                 .cra_init               = omap_sham_cra_sha384_init,
1705                 .cra_exit               = omap_sham_cra_exit,
1706         }
1707 },
1708 {
1709         .init           = omap_sham_init,
1710         .update         = omap_sham_update,
1711         .final          = omap_sham_final,
1712         .finup          = omap_sham_finup,
1713         .digest         = omap_sham_digest,
1714         .setkey         = omap_sham_setkey,
1715         .halg.digestsize        = SHA512_DIGEST_SIZE,
1716         .halg.base      = {
1717                 .cra_name               = "hmac(sha512)",
1718                 .cra_driver_name        = "omap-hmac-sha512",
1719                 .cra_priority           = 400,
1720                 .cra_flags              = CRYPTO_ALG_TYPE_AHASH |
1721                                                 CRYPTO_ALG_ASYNC |
1722                                                 CRYPTO_ALG_NEED_FALLBACK,
1723                 .cra_blocksize          = SHA512_BLOCK_SIZE,
1724                 .cra_ctxsize            = sizeof(struct omap_sham_ctx) +
1725                                         sizeof(struct omap_sham_hmac_ctx),
1726                 .cra_alignmask          = OMAP_ALIGN_MASK,
1727                 .cra_module             = THIS_MODULE,
1728                 .cra_init               = omap_sham_cra_sha512_init,
1729                 .cra_exit               = omap_sham_cra_exit,
1730         }
1731 },
1732 };
1733
1734 static void omap_sham_done_task(unsigned long data)
1735 {
1736         struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1737         int err = 0;
1738
1739         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1740                 omap_sham_handle_queue(dd, NULL);
1741                 return;
1742         }
1743
1744         if (test_bit(FLAGS_CPU, &dd->flags)) {
1745                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1746                         goto finish;
1747         } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1748                 if (test_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1749                         omap_sham_update_dma_stop(dd);
1750                         if (dd->err) {
1751                                 err = dd->err;
1752                                 goto finish;
1753                         }
1754                 }
1755                 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1756                         /* hash or semi-hash ready */
1757                         clear_bit(FLAGS_DMA_READY, &dd->flags);
1758                                 goto finish;
1759                 }
1760         }
1761
1762         return;
1763
1764 finish:
1765         dev_dbg(dd->dev, "update done: err: %d\n", err);
1766         /* finish curent request */
1767         omap_sham_finish_req(dd->req, err);
1768
1769         /* If we are not busy, process next req */
1770         if (!test_bit(FLAGS_BUSY, &dd->flags))
1771                 omap_sham_handle_queue(dd, NULL);
1772 }
1773
1774 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1775 {
1776         if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1777                 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1778         } else {
1779                 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1780                 tasklet_schedule(&dd->done_task);
1781         }
1782
1783         return IRQ_HANDLED;
1784 }
1785
1786 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1787 {
1788         struct omap_sham_dev *dd = dev_id;
1789
1790         if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1791                 /* final -> allow device to go to power-saving mode */
1792                 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1793
1794         omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1795                                  SHA_REG_CTRL_OUTPUT_READY);
1796         omap_sham_read(dd, SHA_REG_CTRL);
1797
1798         return omap_sham_irq_common(dd);
1799 }
1800
1801 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1802 {
1803         struct omap_sham_dev *dd = dev_id;
1804
1805         omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1806
1807         return omap_sham_irq_common(dd);
1808 }
1809
1810 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1811         {
1812                 .algs_list      = algs_sha1_md5,
1813                 .size           = ARRAY_SIZE(algs_sha1_md5),
1814         },
1815 };
1816
1817 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1818         .algs_info      = omap_sham_algs_info_omap2,
1819         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1820         .flags          = BIT(FLAGS_BE32_SHA1),
1821         .digest_size    = SHA1_DIGEST_SIZE,
1822         .copy_hash      = omap_sham_copy_hash_omap2,
1823         .write_ctrl     = omap_sham_write_ctrl_omap2,
1824         .trigger        = omap_sham_trigger_omap2,
1825         .poll_irq       = omap_sham_poll_irq_omap2,
1826         .intr_hdlr      = omap_sham_irq_omap2,
1827         .idigest_ofs    = 0x00,
1828         .din_ofs        = 0x1c,
1829         .digcnt_ofs     = 0x14,
1830         .rev_ofs        = 0x5c,
1831         .mask_ofs       = 0x60,
1832         .sysstatus_ofs  = 0x64,
1833         .major_mask     = 0xf0,
1834         .major_shift    = 4,
1835         .minor_mask     = 0x0f,
1836         .minor_shift    = 0,
1837 };
1838
1839 #ifdef CONFIG_OF
1840 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1841         {
1842                 .algs_list      = algs_sha1_md5,
1843                 .size           = ARRAY_SIZE(algs_sha1_md5),
1844         },
1845         {
1846                 .algs_list      = algs_sha224_sha256,
1847                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1848         },
1849 };
1850
1851 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1852         .algs_info      = omap_sham_algs_info_omap4,
1853         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1854         .flags          = BIT(FLAGS_AUTO_XOR),
1855         .digest_size    = SHA256_DIGEST_SIZE,
1856         .copy_hash      = omap_sham_copy_hash_omap4,
1857         .write_ctrl     = omap_sham_write_ctrl_omap4,
1858         .trigger        = omap_sham_trigger_omap4,
1859         .poll_irq       = omap_sham_poll_irq_omap4,
1860         .intr_hdlr      = omap_sham_irq_omap4,
1861         .idigest_ofs    = 0x020,
1862         .odigest_ofs    = 0x0,
1863         .din_ofs        = 0x080,
1864         .digcnt_ofs     = 0x040,
1865         .rev_ofs        = 0x100,
1866         .mask_ofs       = 0x110,
1867         .sysstatus_ofs  = 0x114,
1868         .mode_ofs       = 0x44,
1869         .length_ofs     = 0x48,
1870         .major_mask     = 0x0700,
1871         .major_shift    = 8,
1872         .minor_mask     = 0x003f,
1873         .minor_shift    = 0,
1874 };
1875
1876 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1877         {
1878                 .algs_list      = algs_sha1_md5,
1879                 .size           = ARRAY_SIZE(algs_sha1_md5),
1880         },
1881         {
1882                 .algs_list      = algs_sha224_sha256,
1883                 .size           = ARRAY_SIZE(algs_sha224_sha256),
1884         },
1885         {
1886                 .algs_list      = algs_sha384_sha512,
1887                 .size           = ARRAY_SIZE(algs_sha384_sha512),
1888         },
1889 };
1890
1891 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1892         .algs_info      = omap_sham_algs_info_omap5,
1893         .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1894         .flags          = BIT(FLAGS_AUTO_XOR),
1895         .digest_size    = SHA512_DIGEST_SIZE,
1896         .copy_hash      = omap_sham_copy_hash_omap4,
1897         .write_ctrl     = omap_sham_write_ctrl_omap4,
1898         .trigger        = omap_sham_trigger_omap4,
1899         .poll_irq       = omap_sham_poll_irq_omap4,
1900         .intr_hdlr      = omap_sham_irq_omap4,
1901         .idigest_ofs    = 0x240,
1902         .odigest_ofs    = 0x200,
1903         .din_ofs        = 0x080,
1904         .digcnt_ofs     = 0x280,
1905         .rev_ofs        = 0x100,
1906         .mask_ofs       = 0x110,
1907         .sysstatus_ofs  = 0x114,
1908         .mode_ofs       = 0x284,
1909         .length_ofs     = 0x288,
1910         .major_mask     = 0x0700,
1911         .major_shift    = 8,
1912         .minor_mask     = 0x003f,
1913         .minor_shift    = 0,
1914 };
1915
1916 static const struct of_device_id omap_sham_of_match[] = {
1917         {
1918                 .compatible     = "ti,omap2-sham",
1919                 .data           = &omap_sham_pdata_omap2,
1920         },
1921         {
1922                 .compatible     = "ti,omap3-sham",
1923                 .data           = &omap_sham_pdata_omap2,
1924         },
1925         {
1926                 .compatible     = "ti,omap4-sham",
1927                 .data           = &omap_sham_pdata_omap4,
1928         },
1929         {
1930                 .compatible     = "ti,omap5-sham",
1931                 .data           = &omap_sham_pdata_omap5,
1932         },
1933         {},
1934 };
1935 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1936
1937 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1938                 struct device *dev, struct resource *res)
1939 {
1940         struct device_node *node = dev->of_node;
1941         const struct of_device_id *match;
1942         int err = 0;
1943
1944         match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
1945         if (!match) {
1946                 dev_err(dev, "no compatible OF match\n");
1947                 err = -EINVAL;
1948                 goto err;
1949         }
1950
1951         err = of_address_to_resource(node, 0, res);
1952         if (err < 0) {
1953                 dev_err(dev, "can't translate OF node address\n");
1954                 err = -EINVAL;
1955                 goto err;
1956         }
1957
1958         dd->irq = irq_of_parse_and_map(node, 0);
1959         if (!dd->irq) {
1960                 dev_err(dev, "can't translate OF irq value\n");
1961                 err = -EINVAL;
1962                 goto err;
1963         }
1964
1965         dd->pdata = match->data;
1966
1967 err:
1968         return err;
1969 }
1970 #else
1971 static const struct of_device_id omap_sham_of_match[] = {
1972         {},
1973 };
1974
1975 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1976                 struct device *dev, struct resource *res)
1977 {
1978         return -EINVAL;
1979 }
1980 #endif
1981
1982 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1983                 struct platform_device *pdev, struct resource *res)
1984 {
1985         struct device *dev = &pdev->dev;
1986         struct resource *r;
1987         int err = 0;
1988
1989         /* Get the base address */
1990         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1991         if (!r) {
1992                 dev_err(dev, "no MEM resource info\n");
1993                 err = -ENODEV;
1994                 goto err;
1995         }
1996         memcpy(res, r, sizeof(*res));
1997
1998         /* Get the IRQ */
1999         dd->irq = platform_get_irq(pdev, 0);
2000         if (dd->irq < 0) {
2001                 dev_err(dev, "no IRQ resource info\n");
2002                 err = dd->irq;
2003                 goto err;
2004         }
2005
2006         /* Only OMAP2/3 can be non-DT */
2007         dd->pdata = &omap_sham_pdata_omap2;
2008
2009 err:
2010         return err;
2011 }
2012
2013 static int omap_sham_probe(struct platform_device *pdev)
2014 {
2015         struct omap_sham_dev *dd;
2016         struct device *dev = &pdev->dev;
2017         struct resource res;
2018         dma_cap_mask_t mask;
2019         int err, i, j;
2020         u32 rev;
2021
2022         dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2023         if (dd == NULL) {
2024                 dev_err(dev, "unable to alloc data struct.\n");
2025                 err = -ENOMEM;
2026                 goto data_err;
2027         }
2028         dd->dev = dev;
2029         platform_set_drvdata(pdev, dd);
2030
2031         INIT_LIST_HEAD(&dd->list);
2032         spin_lock_init(&dd->lock);
2033         tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2034         crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2035
2036         err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2037                                omap_sham_get_res_pdev(dd, pdev, &res);
2038         if (err)
2039                 goto data_err;
2040
2041         dd->io_base = devm_ioremap_resource(dev, &res);
2042         if (IS_ERR(dd->io_base)) {
2043                 err = PTR_ERR(dd->io_base);
2044                 goto data_err;
2045         }
2046         dd->phys_base = res.start;
2047
2048         err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2049                                IRQF_TRIGGER_NONE, dev_name(dev), dd);
2050         if (err) {
2051                 dev_err(dev, "unable to request irq %d, err = %d\n",
2052                         dd->irq, err);
2053                 goto data_err;
2054         }
2055
2056         dma_cap_zero(mask);
2057         dma_cap_set(DMA_SLAVE, mask);
2058
2059         dd->dma_lch = dma_request_chan(dev, "rx");
2060         if (IS_ERR(dd->dma_lch)) {
2061                 err = PTR_ERR(dd->dma_lch);
2062                 if (err == -EPROBE_DEFER)
2063                         goto data_err;
2064
2065                 dd->polling_mode = 1;
2066                 dev_dbg(dev, "using polling mode instead of dma\n");
2067         }
2068
2069         dd->flags |= dd->pdata->flags;
2070         sham.flags |= dd->pdata->flags;
2071
2072         pm_runtime_use_autosuspend(dev);
2073         pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2074
2075         pm_runtime_enable(dev);
2076         pm_runtime_irq_safe(dev);
2077
2078         err = pm_runtime_get_sync(dev);
2079         if (err < 0) {
2080                 dev_err(dev, "failed to get sync: %d\n", err);
2081                 goto err_pm;
2082         }
2083
2084         rev = omap_sham_read(dd, SHA_REG_REV(dd));
2085         pm_runtime_put_sync(&pdev->dev);
2086
2087         dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2088                 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2089                 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2090
2091         spin_lock(&sham.lock);
2092         list_add_tail(&dd->list, &sham.dev_list);
2093         spin_unlock(&sham.lock);
2094
2095         for (i = 0; i < dd->pdata->algs_info_size; i++) {
2096                 if (dd->pdata->algs_info[i].registered)
2097                         break;
2098
2099                 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2100                         struct ahash_alg *alg;
2101
2102                         alg = &dd->pdata->algs_info[i].algs_list[j];
2103                         alg->export = omap_sham_export;
2104                         alg->import = omap_sham_import;
2105                         alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2106                                               BUFLEN;
2107                         err = crypto_register_ahash(alg);
2108                         if (err)
2109                                 goto err_algs;
2110
2111                         dd->pdata->algs_info[i].registered++;
2112                 }
2113         }
2114
2115         return 0;
2116
2117 err_algs:
2118         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2119                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2120                         crypto_unregister_ahash(
2121                                         &dd->pdata->algs_info[i].algs_list[j]);
2122 err_pm:
2123         pm_runtime_disable(dev);
2124         if (!dd->polling_mode)
2125                 dma_release_channel(dd->dma_lch);
2126 data_err:
2127         dev_err(dev, "initialization failed.\n");
2128
2129         return err;
2130 }
2131
2132 static int omap_sham_remove(struct platform_device *pdev)
2133 {
2134         static struct omap_sham_dev *dd;
2135         int i, j;
2136
2137         dd = platform_get_drvdata(pdev);
2138         if (!dd)
2139                 return -ENODEV;
2140         spin_lock(&sham.lock);
2141         list_del(&dd->list);
2142         spin_unlock(&sham.lock);
2143         for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2144                 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
2145                         crypto_unregister_ahash(
2146                                         &dd->pdata->algs_info[i].algs_list[j]);
2147                         dd->pdata->algs_info[i].registered--;
2148                 }
2149         tasklet_kill(&dd->done_task);
2150         pm_runtime_disable(&pdev->dev);
2151
2152         if (!dd->polling_mode)
2153                 dma_release_channel(dd->dma_lch);
2154
2155         return 0;
2156 }
2157
2158 #ifdef CONFIG_PM_SLEEP
2159 static int omap_sham_suspend(struct device *dev)
2160 {
2161         pm_runtime_put_sync(dev);
2162         return 0;
2163 }
2164
2165 static int omap_sham_resume(struct device *dev)
2166 {
2167         int err = pm_runtime_get_sync(dev);
2168         if (err < 0) {
2169                 dev_err(dev, "failed to get sync: %d\n", err);
2170                 return err;
2171         }
2172         return 0;
2173 }
2174 #endif
2175
2176 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2177
2178 static struct platform_driver omap_sham_driver = {
2179         .probe  = omap_sham_probe,
2180         .remove = omap_sham_remove,
2181         .driver = {
2182                 .name   = "omap-sham",
2183                 .pm     = &omap_sham_pm_ops,
2184                 .of_match_table = omap_sham_of_match,
2185         },
2186 };
2187
2188 module_platform_driver(omap_sham_driver);
2189
2190 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2191 MODULE_LICENSE("GPL v2");
2192 MODULE_AUTHOR("Dmitry Kasatkin");
2193 MODULE_ALIAS("platform:omap-sham");