1 // SPDX-License-Identifier: GPL-2.0-only
5 * Support for OMAP SHA1/MD5 HW acceleration.
7 * Copyright (c) 2010 Nokia Corporation
8 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
9 * Copyright (c) 2011 Texas Instruments Incorporated
11 * Some ideas are from old omap-sha1-md5.c driver.
14 #define pr_fmt(fmt) "%s: " fmt, __func__
16 #include <linux/err.h>
17 #include <linux/device.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmaengine.h>
29 #include <linux/pm_runtime.h>
31 #include <linux/of_device.h>
32 #include <linux/of_address.h>
33 #include <linux/of_irq.h>
34 #include <linux/delay.h>
35 #include <linux/crypto.h>
36 #include <crypto/scatterwalk.h>
37 #include <crypto/algapi.h>
38 #include <crypto/sha.h>
39 #include <crypto/hash.h>
40 #include <crypto/hmac.h>
41 #include <crypto/internal/hash.h>
42 #include <crypto/engine.h>
44 #define MD5_DIGEST_SIZE 16
46 #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04))
47 #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04))
48 #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs)
50 #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04))
52 #define SHA_REG_CTRL 0x18
53 #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
54 #define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
55 #define SHA_REG_CTRL_ALGO_CONST (1 << 3)
56 #define SHA_REG_CTRL_ALGO (1 << 2)
57 #define SHA_REG_CTRL_INPUT_READY (1 << 1)
58 #define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
60 #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs)
62 #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs)
63 #define SHA_REG_MASK_DMA_EN (1 << 3)
64 #define SHA_REG_MASK_IT_EN (1 << 2)
65 #define SHA_REG_MASK_SOFTRESET (1 << 1)
66 #define SHA_REG_AUTOIDLE (1 << 0)
68 #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs)
69 #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
71 #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs)
72 #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7)
73 #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5)
74 #define SHA_REG_MODE_CLOSE_HASH (1 << 4)
75 #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3)
77 #define SHA_REG_MODE_ALGO_MASK (7 << 0)
78 #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1)
79 #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1)
80 #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1)
81 #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1)
82 #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0)
83 #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0)
85 #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs)
87 #define SHA_REG_IRQSTATUS 0x118
88 #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3)
89 #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
90 #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1)
91 #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0)
93 #define SHA_REG_IRQENA 0x11C
94 #define SHA_REG_IRQENA_CTX_RDY (1 << 3)
95 #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2)
96 #define SHA_REG_IRQENA_INPUT_RDY (1 << 1)
97 #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0)
99 #define DEFAULT_TIMEOUT_INTERVAL HZ
101 #define DEFAULT_AUTOSUSPEND_DELAY 1000
103 /* mostly device flags */
104 #define FLAGS_FINAL 1
105 #define FLAGS_DMA_ACTIVE 2
106 #define FLAGS_OUTPUT_READY 3
109 #define FLAGS_DMA_READY 6
110 #define FLAGS_AUTO_XOR 7
111 #define FLAGS_BE32_SHA1 8
112 #define FLAGS_SGS_COPIED 9
113 #define FLAGS_SGS_ALLOCED 10
114 #define FLAGS_HUGE 11
117 #define FLAGS_FINUP 16
119 #define FLAGS_MODE_SHIFT 18
120 #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
121 #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
122 #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
123 #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
124 #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
125 #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
126 #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
128 #define FLAGS_HMAC 21
129 #define FLAGS_ERROR 22
134 #define OMAP_ALIGN_MASK (sizeof(u32)-1)
135 #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
137 #define BUFLEN SHA512_BLOCK_SIZE
138 #define OMAP_SHA_DMA_THRESHOLD 256
140 #define OMAP_SHA_MAX_DMA_LEN (1024 * 2048)
142 struct omap_sham_dev;
144 struct omap_sham_reqctx {
145 struct omap_sham_dev *dd;
149 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
155 struct scatterlist *sg;
156 struct scatterlist sgl[2];
157 int offset; /* offset in current sg */
159 unsigned int total; /* total request */
161 u8 buffer[] OMAP_ALIGNED;
164 struct omap_sham_hmac_ctx {
165 struct crypto_shash *shash;
166 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
167 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
170 struct omap_sham_ctx {
171 struct crypto_engine_ctx enginectx;
175 struct crypto_shash *fallback;
177 struct omap_sham_hmac_ctx base[];
180 #define OMAP_SHAM_QUEUE_LENGTH 10
182 struct omap_sham_algs_info {
183 struct ahash_alg *algs_list;
185 unsigned int registered;
188 struct omap_sham_pdata {
189 struct omap_sham_algs_info *algs_info;
190 unsigned int algs_info_size;
194 void (*copy_hash)(struct ahash_request *req, int out);
195 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
197 void (*trigger)(struct omap_sham_dev *dd, size_t length);
198 int (*poll_irq)(struct omap_sham_dev *dd);
199 irqreturn_t (*intr_hdlr)(int irq, void *dev_id);
217 struct omap_sham_dev {
218 struct list_head list;
219 unsigned long phys_base;
221 void __iomem *io_base;
224 struct dma_chan *dma_lch;
225 struct tasklet_struct done_task;
227 u8 xmit_buf[BUFLEN] OMAP_ALIGNED;
231 struct crypto_queue queue;
232 struct ahash_request *req;
233 struct crypto_engine *engine;
235 const struct omap_sham_pdata *pdata;
238 struct omap_sham_drv {
239 struct list_head dev_list;
244 static struct omap_sham_drv sham = {
245 .dev_list = LIST_HEAD_INIT(sham.dev_list),
246 .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
249 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op);
250 static void omap_sham_finish_req(struct ahash_request *req, int err);
252 static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
254 return __raw_readl(dd->io_base + offset);
257 static inline void omap_sham_write(struct omap_sham_dev *dd,
258 u32 offset, u32 value)
260 __raw_writel(value, dd->io_base + offset);
263 static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
268 val = omap_sham_read(dd, address);
271 omap_sham_write(dd, address, val);
274 static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
276 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
278 while (!(omap_sham_read(dd, offset) & bit)) {
279 if (time_is_before_jiffies(timeout))
286 static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
288 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
289 struct omap_sham_dev *dd = ctx->dd;
290 u32 *hash = (u32 *)ctx->digest;
293 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
295 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
297 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
301 static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
303 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
304 struct omap_sham_dev *dd = ctx->dd;
307 if (ctx->flags & BIT(FLAGS_HMAC)) {
308 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
309 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
310 struct omap_sham_hmac_ctx *bctx = tctx->base;
311 u32 *opad = (u32 *)bctx->opad;
313 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
315 opad[i] = omap_sham_read(dd,
316 SHA_REG_ODIGEST(dd, i));
318 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
323 omap_sham_copy_hash_omap2(req, out);
326 static void omap_sham_copy_ready_hash(struct ahash_request *req)
328 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
329 u32 *in = (u32 *)ctx->digest;
330 u32 *hash = (u32 *)req->result;
331 int i, d, big_endian = 0;
336 switch (ctx->flags & FLAGS_MODE_MASK) {
338 d = MD5_DIGEST_SIZE / sizeof(u32);
340 case FLAGS_MODE_SHA1:
341 /* OMAP2 SHA1 is big endian */
342 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
344 d = SHA1_DIGEST_SIZE / sizeof(u32);
346 case FLAGS_MODE_SHA224:
347 d = SHA224_DIGEST_SIZE / sizeof(u32);
349 case FLAGS_MODE_SHA256:
350 d = SHA256_DIGEST_SIZE / sizeof(u32);
352 case FLAGS_MODE_SHA384:
353 d = SHA384_DIGEST_SIZE / sizeof(u32);
355 case FLAGS_MODE_SHA512:
356 d = SHA512_DIGEST_SIZE / sizeof(u32);
363 for (i = 0; i < d; i++)
364 hash[i] = be32_to_cpup((__be32 *)in + i);
366 for (i = 0; i < d; i++)
367 hash[i] = le32_to_cpup((__le32 *)in + i);
370 static int omap_sham_hw_init(struct omap_sham_dev *dd)
374 err = pm_runtime_resume_and_get(dd->dev);
376 dev_err(dd->dev, "failed to get sync: %d\n", err);
380 if (!test_bit(FLAGS_INIT, &dd->flags)) {
381 set_bit(FLAGS_INIT, &dd->flags);
388 static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
391 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
392 u32 val = length << 5, mask;
394 if (likely(ctx->digcnt))
395 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
397 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
398 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
399 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
401 * Setting ALGO_CONST only for the first iteration
402 * and CLOSE_HASH only for the last one.
404 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
405 val |= SHA_REG_CTRL_ALGO;
407 val |= SHA_REG_CTRL_ALGO_CONST;
409 val |= SHA_REG_CTRL_CLOSE_HASH;
411 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
412 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
414 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
417 static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
421 static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
423 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
426 static int get_block_size(struct omap_sham_reqctx *ctx)
430 switch (ctx->flags & FLAGS_MODE_MASK) {
432 case FLAGS_MODE_SHA1:
435 case FLAGS_MODE_SHA224:
436 case FLAGS_MODE_SHA256:
437 d = SHA256_BLOCK_SIZE;
439 case FLAGS_MODE_SHA384:
440 case FLAGS_MODE_SHA512:
441 d = SHA512_BLOCK_SIZE;
450 static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
451 u32 *value, int count)
453 for (; count--; value++, offset += 4)
454 omap_sham_write(dd, offset, *value);
457 static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
460 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
463 if (likely(ctx->digcnt))
464 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
467 * Setting ALGO_CONST only for the first iteration and
468 * CLOSE_HASH only for the last one. Note that flags mode bits
469 * correspond to algorithm encoding in mode register.
471 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
473 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
474 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
475 struct omap_sham_hmac_ctx *bctx = tctx->base;
478 val |= SHA_REG_MODE_ALGO_CONSTANT;
480 if (ctx->flags & BIT(FLAGS_HMAC)) {
481 bs = get_block_size(ctx);
482 nr_dr = bs / (2 * sizeof(u32));
483 val |= SHA_REG_MODE_HMAC_KEY_PROC;
484 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
485 (u32 *)bctx->ipad, nr_dr);
486 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
487 (u32 *)bctx->ipad + nr_dr, nr_dr);
493 val |= SHA_REG_MODE_CLOSE_HASH;
495 if (ctx->flags & BIT(FLAGS_HMAC))
496 val |= SHA_REG_MODE_HMAC_OUTER_HASH;
499 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
500 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
501 SHA_REG_MODE_HMAC_KEY_PROC;
503 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
504 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
505 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
506 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
508 (dma ? SHA_REG_MASK_DMA_EN : 0),
509 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
512 static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
514 omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
517 static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
519 return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
520 SHA_REG_IRQSTATUS_INPUT_RDY);
523 static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
526 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
527 int count, len32, bs32, offset = 0;
530 struct sg_mapping_iter mi;
532 dev_dbg(dd->dev, "xmit_cpu: digcnt: %zd, length: %zd, final: %d\n",
533 ctx->digcnt, length, final);
535 dd->pdata->write_ctrl(dd, length, final, 0);
536 dd->pdata->trigger(dd, length);
538 /* should be non-zero before next lines to disable clocks later */
539 ctx->digcnt += length;
540 ctx->total -= length;
543 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
545 set_bit(FLAGS_CPU, &dd->flags);
547 len32 = DIV_ROUND_UP(length, sizeof(u32));
548 bs32 = get_block_size(ctx) / sizeof(u32);
550 sg_miter_start(&mi, ctx->sg, ctx->sg_len,
551 SG_MITER_FROM_SG | SG_MITER_ATOMIC);
556 if (dd->pdata->poll_irq(dd))
559 for (count = 0; count < min(len32, bs32); count++, offset++) {
564 pr_err("sg miter failure.\n");
570 omap_sham_write(dd, SHA_REG_DIN(dd, count),
574 len32 -= min(len32, bs32);
582 static void omap_sham_dma_callback(void *param)
584 struct omap_sham_dev *dd = param;
586 set_bit(FLAGS_DMA_READY, &dd->flags);
587 tasklet_schedule(&dd->done_task);
590 static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
593 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
594 struct dma_async_tx_descriptor *tx;
595 struct dma_slave_config cfg;
598 dev_dbg(dd->dev, "xmit_dma: digcnt: %zd, length: %zd, final: %d\n",
599 ctx->digcnt, length, final);
601 if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
602 dev_err(dd->dev, "dma_map_sg error\n");
606 memset(&cfg, 0, sizeof(cfg));
608 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
609 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
610 cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
612 ret = dmaengine_slave_config(dd->dma_lch, &cfg);
614 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
618 tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
620 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
623 dev_err(dd->dev, "prep_slave_sg failed\n");
627 tx->callback = omap_sham_dma_callback;
628 tx->callback_param = dd;
630 dd->pdata->write_ctrl(dd, length, final, 1);
632 ctx->digcnt += length;
633 ctx->total -= length;
636 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
638 set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
640 dmaengine_submit(tx);
641 dma_async_issue_pending(dd->dma_lch);
643 dd->pdata->trigger(dd, length);
648 static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
649 struct scatterlist *sg, int bs, int new_len)
651 int n = sg_nents(sg);
652 struct scatterlist *tmp;
653 int offset = ctx->offset;
655 ctx->total = new_len;
660 ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
664 sg_init_table(ctx->sg, n);
671 sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
674 new_len -= ctx->bufcnt;
677 while (sg && new_len) {
678 int len = sg->length - offset;
681 offset -= sg->length;
691 sg_set_page(tmp, sg_page(sg), len, sg->offset + offset);
706 set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
708 ctx->offset += new_len - ctx->bufcnt;
714 static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
715 struct scatterlist *sg, int bs,
716 unsigned int new_len)
721 pages = get_order(new_len);
723 buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
725 pr_err("Couldn't allocate pages for unaligned cases.\n");
730 memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
732 scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
733 min(new_len, ctx->total) - ctx->bufcnt, 0);
734 sg_init_table(ctx->sgl, 1);
735 sg_set_buf(ctx->sgl, buf, new_len);
737 set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
739 ctx->offset += new_len - ctx->bufcnt;
741 ctx->total = new_len;
746 static int omap_sham_align_sgs(struct scatterlist *sg,
747 int nbytes, int bs, bool final,
748 struct omap_sham_reqctx *rctx)
753 struct scatterlist *sg_tmp = sg;
755 int offset = rctx->offset;
756 int bufcnt = rctx->bufcnt;
758 if (!sg || !sg->length || !nbytes) {
760 bufcnt = DIV_ROUND_UP(bufcnt, bs) * bs;
761 sg_init_table(rctx->sgl, 1);
762 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, bufcnt);
763 rctx->sg = rctx->sgl;
776 new_len = DIV_ROUND_UP(new_len, bs) * bs;
778 new_len = (new_len - 1) / bs * bs;
783 if (nbytes != new_len)
786 while (nbytes > 0 && sg_tmp) {
790 if (!IS_ALIGNED(bufcnt, bs)) {
802 #ifdef CONFIG_ZONE_DMA
803 if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) {
809 if (offset < sg_tmp->length) {
810 if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
815 if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
822 offset -= sg_tmp->length;
828 nbytes -= sg_tmp->length;
831 sg_tmp = sg_next(sg_tmp);
839 if (new_len > OMAP_SHA_MAX_DMA_LEN) {
840 new_len = OMAP_SHA_MAX_DMA_LEN;
845 return omap_sham_copy_sgs(rctx, sg, bs, new_len);
847 return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
849 rctx->total = new_len;
850 rctx->offset += new_len;
853 sg_init_table(rctx->sgl, 2);
854 sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
855 sg_chain(rctx->sgl, 2, sg);
856 rctx->sg = rctx->sgl;
864 static int omap_sham_prepare_request(struct crypto_engine *engine, void *areq)
866 struct ahash_request *req = container_of(areq, struct ahash_request,
868 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
872 bool final = rctx->flags & BIT(FLAGS_FINUP);
873 bool update = rctx->op == OP_UPDATE;
876 bs = get_block_size(rctx);
878 nbytes = rctx->bufcnt;
881 nbytes += req->nbytes - rctx->offset;
883 dev_dbg(rctx->dd->dev,
884 "%s: nbytes=%d, bs=%d, total=%d, offset=%d, bufcnt=%zd\n",
885 __func__, nbytes, bs, rctx->total, rctx->offset,
891 rctx->total = nbytes;
893 if (update && req->nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
894 int len = bs - rctx->bufcnt % bs;
896 if (len > req->nbytes)
898 scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
905 memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
907 ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
911 hash_later = nbytes - rctx->total;
915 if (hash_later && hash_later <= rctx->buflen) {
916 scatterwalk_map_and_copy(rctx->buffer,
918 req->nbytes - hash_later,
921 rctx->bufcnt = hash_later;
926 if (hash_later > rctx->buflen)
927 set_bit(FLAGS_HUGE, &rctx->dd->flags);
929 rctx->total = min(nbytes, rctx->total);
934 static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
936 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
938 dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
940 clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
945 static struct omap_sham_dev *omap_sham_find_dev(struct omap_sham_reqctx *ctx)
947 struct omap_sham_dev *dd;
952 spin_lock_bh(&sham.lock);
953 dd = list_first_entry(&sham.dev_list, struct omap_sham_dev, list);
954 list_move_tail(&dd->list, &sham.dev_list);
956 spin_unlock_bh(&sham.lock);
961 static int omap_sham_init(struct ahash_request *req)
963 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
964 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
965 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
966 struct omap_sham_dev *dd;
971 dd = omap_sham_find_dev(ctx);
977 dev_dbg(dd->dev, "init: digest size: %d\n",
978 crypto_ahash_digestsize(tfm));
980 switch (crypto_ahash_digestsize(tfm)) {
981 case MD5_DIGEST_SIZE:
982 ctx->flags |= FLAGS_MODE_MD5;
983 bs = SHA1_BLOCK_SIZE;
985 case SHA1_DIGEST_SIZE:
986 ctx->flags |= FLAGS_MODE_SHA1;
987 bs = SHA1_BLOCK_SIZE;
989 case SHA224_DIGEST_SIZE:
990 ctx->flags |= FLAGS_MODE_SHA224;
991 bs = SHA224_BLOCK_SIZE;
993 case SHA256_DIGEST_SIZE:
994 ctx->flags |= FLAGS_MODE_SHA256;
995 bs = SHA256_BLOCK_SIZE;
997 case SHA384_DIGEST_SIZE:
998 ctx->flags |= FLAGS_MODE_SHA384;
999 bs = SHA384_BLOCK_SIZE;
1001 case SHA512_DIGEST_SIZE:
1002 ctx->flags |= FLAGS_MODE_SHA512;
1003 bs = SHA512_BLOCK_SIZE;
1011 ctx->buflen = BUFLEN;
1013 if (tctx->flags & BIT(FLAGS_HMAC)) {
1014 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1015 struct omap_sham_hmac_ctx *bctx = tctx->base;
1017 memcpy(ctx->buffer, bctx->ipad, bs);
1021 ctx->flags |= BIT(FLAGS_HMAC);
1028 static int omap_sham_update_req(struct omap_sham_dev *dd)
1030 struct ahash_request *req = dd->req;
1031 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1033 bool final = (ctx->flags & BIT(FLAGS_FINUP)) &&
1034 !(dd->flags & BIT(FLAGS_HUGE));
1036 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %zd, final: %d",
1037 ctx->total, ctx->digcnt, final);
1039 if (ctx->total < get_block_size(ctx) ||
1040 ctx->total < dd->fallback_sz)
1041 ctx->flags |= BIT(FLAGS_CPU);
1043 if (ctx->flags & BIT(FLAGS_CPU))
1044 err = omap_sham_xmit_cpu(dd, ctx->total, final);
1046 err = omap_sham_xmit_dma(dd, ctx->total, final);
1048 /* wait for dma completion before can take more data */
1049 dev_dbg(dd->dev, "update: err: %d, digcnt: %zd\n", err, ctx->digcnt);
1054 static int omap_sham_final_req(struct omap_sham_dev *dd)
1056 struct ahash_request *req = dd->req;
1057 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1058 int err = 0, use_dma = 1;
1060 if (dd->flags & BIT(FLAGS_HUGE))
1063 if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
1065 * faster to handle last block with cpu or
1066 * use cpu when dma is not present.
1071 err = omap_sham_xmit_dma(dd, ctx->total, 1);
1073 err = omap_sham_xmit_cpu(dd, ctx->total, 1);
1077 dev_dbg(dd->dev, "final_req: err: %d\n", err);
1082 static int omap_sham_hash_one_req(struct crypto_engine *engine, void *areq)
1084 struct ahash_request *req = container_of(areq, struct ahash_request,
1086 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1087 struct omap_sham_dev *dd = ctx->dd;
1089 bool final = (ctx->flags & BIT(FLAGS_FINUP)) &&
1090 !(dd->flags & BIT(FLAGS_HUGE));
1092 dev_dbg(dd->dev, "hash-one: op: %u, total: %u, digcnt: %zd, final: %d",
1093 ctx->op, ctx->total, ctx->digcnt, final);
1097 err = omap_sham_hw_init(dd);
1102 dd->pdata->copy_hash(req, 0);
1104 if (ctx->op == OP_UPDATE)
1105 err = omap_sham_update_req(dd);
1106 else if (ctx->op == OP_FINAL)
1107 err = omap_sham_final_req(dd);
1109 if (err != -EINPROGRESS)
1110 omap_sham_finish_req(req, err);
1115 static int omap_sham_finish_hmac(struct ahash_request *req)
1117 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1118 struct omap_sham_hmac_ctx *bctx = tctx->base;
1119 int bs = crypto_shash_blocksize(bctx->shash);
1120 int ds = crypto_shash_digestsize(bctx->shash);
1121 SHASH_DESC_ON_STACK(shash, bctx->shash);
1123 shash->tfm = bctx->shash;
1125 return crypto_shash_init(shash) ?:
1126 crypto_shash_update(shash, bctx->opad, bs) ?:
1127 crypto_shash_finup(shash, req->result, ds, req->result);
1130 static int omap_sham_finish(struct ahash_request *req)
1132 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1133 struct omap_sham_dev *dd = ctx->dd;
1137 omap_sham_copy_ready_hash(req);
1138 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
1139 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
1140 err = omap_sham_finish_hmac(req);
1143 dev_dbg(dd->dev, "digcnt: %zd, bufcnt: %zd\n", ctx->digcnt, ctx->bufcnt);
1148 static void omap_sham_finish_req(struct ahash_request *req, int err)
1150 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1151 struct omap_sham_dev *dd = ctx->dd;
1153 if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
1154 free_pages((unsigned long)sg_virt(ctx->sg),
1155 get_order(ctx->sg->length));
1157 if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
1162 dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED) |
1163 BIT(FLAGS_CPU) | BIT(FLAGS_DMA_READY) |
1164 BIT(FLAGS_OUTPUT_READY));
1167 dd->pdata->copy_hash(req, 1);
1169 if (dd->flags & BIT(FLAGS_HUGE)) {
1170 /* Re-enqueue the request */
1171 omap_sham_enqueue(req, ctx->op);
1176 if (test_bit(FLAGS_FINAL, &dd->flags))
1177 err = omap_sham_finish(req);
1179 ctx->flags |= BIT(FLAGS_ERROR);
1182 /* atomic operation is not needed here */
1183 dd->flags &= ~(BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1184 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
1186 pm_runtime_mark_last_busy(dd->dev);
1187 pm_runtime_put_autosuspend(dd->dev);
1191 crypto_finalize_hash_request(dd->engine, req, err);
1194 static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1195 struct ahash_request *req)
1197 return crypto_transfer_hash_request_to_engine(dd->engine, req);
1200 static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1202 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1203 struct omap_sham_dev *dd = ctx->dd;
1207 return omap_sham_handle_queue(dd, req);
1210 static int omap_sham_update(struct ahash_request *req)
1212 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1213 struct omap_sham_dev *dd = omap_sham_find_dev(ctx);
1218 if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
1219 scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
1221 ctx->bufcnt += req->nbytes;
1225 if (dd->polling_mode)
1226 ctx->flags |= BIT(FLAGS_CPU);
1228 return omap_sham_enqueue(req, OP_UPDATE);
1231 static int omap_sham_final_shash(struct ahash_request *req)
1233 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1234 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1238 * If we are running HMAC on limited hardware support, skip
1239 * the ipad in the beginning of the buffer if we are going for
1240 * software fallback algorithm.
1242 if (test_bit(FLAGS_HMAC, &ctx->flags) &&
1243 !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
1244 offset = get_block_size(ctx);
1246 return crypto_shash_tfm_digest(tctx->fallback, ctx->buffer + offset,
1247 ctx->bufcnt - offset, req->result);
1250 static int omap_sham_final(struct ahash_request *req)
1252 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1254 ctx->flags |= BIT(FLAGS_FINUP);
1256 if (ctx->flags & BIT(FLAGS_ERROR))
1257 return 0; /* uncompleted hash is not needed */
1260 * OMAP HW accel works only with buffers >= 9.
1261 * HMAC is always >= 9 because ipad == block size.
1262 * If buffersize is less than fallback_sz, we use fallback
1263 * SW encoding, as using DMA + HW in this case doesn't provide
1266 if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz)
1267 return omap_sham_final_shash(req);
1268 else if (ctx->bufcnt)
1269 return omap_sham_enqueue(req, OP_FINAL);
1271 /* copy ready hash (+ finalize hmac) */
1272 return omap_sham_finish(req);
1275 static int omap_sham_finup(struct ahash_request *req)
1277 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1280 ctx->flags |= BIT(FLAGS_FINUP);
1282 err1 = omap_sham_update(req);
1283 if (err1 == -EINPROGRESS || err1 == -EBUSY)
1286 * final() has to be always called to cleanup resources
1287 * even if udpate() failed, except EINPROGRESS
1289 err2 = omap_sham_final(req);
1291 return err1 ?: err2;
1294 static int omap_sham_digest(struct ahash_request *req)
1296 return omap_sham_init(req) ?: omap_sham_finup(req);
1299 static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1300 unsigned int keylen)
1302 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1303 struct omap_sham_hmac_ctx *bctx = tctx->base;
1304 int bs = crypto_shash_blocksize(bctx->shash);
1305 int ds = crypto_shash_digestsize(bctx->shash);
1308 err = crypto_shash_setkey(tctx->fallback, key, keylen);
1313 err = crypto_shash_tfm_digest(bctx->shash, key, keylen,
1319 memcpy(bctx->ipad, key, keylen);
1322 memset(bctx->ipad + keylen, 0, bs - keylen);
1324 if (!test_bit(FLAGS_AUTO_XOR, &sham.flags)) {
1325 memcpy(bctx->opad, bctx->ipad, bs);
1327 for (i = 0; i < bs; i++) {
1328 bctx->ipad[i] ^= HMAC_IPAD_VALUE;
1329 bctx->opad[i] ^= HMAC_OPAD_VALUE;
1336 static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1338 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1339 const char *alg_name = crypto_tfm_alg_name(tfm);
1341 /* Allocate a fallback and abort if it failed. */
1342 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1343 CRYPTO_ALG_NEED_FALLBACK);
1344 if (IS_ERR(tctx->fallback)) {
1345 pr_err("omap-sham: fallback driver '%s' "
1346 "could not be loaded.\n", alg_name);
1347 return PTR_ERR(tctx->fallback);
1350 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1351 sizeof(struct omap_sham_reqctx) + BUFLEN);
1354 struct omap_sham_hmac_ctx *bctx = tctx->base;
1355 tctx->flags |= BIT(FLAGS_HMAC);
1356 bctx->shash = crypto_alloc_shash(alg_base, 0,
1357 CRYPTO_ALG_NEED_FALLBACK);
1358 if (IS_ERR(bctx->shash)) {
1359 pr_err("omap-sham: base driver '%s' "
1360 "could not be loaded.\n", alg_base);
1361 crypto_free_shash(tctx->fallback);
1362 return PTR_ERR(bctx->shash);
1367 tctx->enginectx.op.do_one_request = omap_sham_hash_one_req;
1368 tctx->enginectx.op.prepare_request = omap_sham_prepare_request;
1369 tctx->enginectx.op.unprepare_request = NULL;
1374 static int omap_sham_cra_init(struct crypto_tfm *tfm)
1376 return omap_sham_cra_init_alg(tfm, NULL);
1379 static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1381 return omap_sham_cra_init_alg(tfm, "sha1");
1384 static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1386 return omap_sham_cra_init_alg(tfm, "sha224");
1389 static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1391 return omap_sham_cra_init_alg(tfm, "sha256");
1394 static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1396 return omap_sham_cra_init_alg(tfm, "md5");
1399 static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1401 return omap_sham_cra_init_alg(tfm, "sha384");
1404 static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1406 return omap_sham_cra_init_alg(tfm, "sha512");
1409 static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1411 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1413 crypto_free_shash(tctx->fallback);
1414 tctx->fallback = NULL;
1416 if (tctx->flags & BIT(FLAGS_HMAC)) {
1417 struct omap_sham_hmac_ctx *bctx = tctx->base;
1418 crypto_free_shash(bctx->shash);
1422 static int omap_sham_export(struct ahash_request *req, void *out)
1424 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1426 memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
1431 static int omap_sham_import(struct ahash_request *req, const void *in)
1433 struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
1434 const struct omap_sham_reqctx *ctx_in = in;
1436 memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
1441 static struct ahash_alg algs_sha1_md5[] = {
1443 .init = omap_sham_init,
1444 .update = omap_sham_update,
1445 .final = omap_sham_final,
1446 .finup = omap_sham_finup,
1447 .digest = omap_sham_digest,
1448 .halg.digestsize = SHA1_DIGEST_SIZE,
1451 .cra_driver_name = "omap-sha1",
1452 .cra_priority = 400,
1453 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1455 CRYPTO_ALG_NEED_FALLBACK,
1456 .cra_blocksize = SHA1_BLOCK_SIZE,
1457 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1458 .cra_alignmask = OMAP_ALIGN_MASK,
1459 .cra_module = THIS_MODULE,
1460 .cra_init = omap_sham_cra_init,
1461 .cra_exit = omap_sham_cra_exit,
1465 .init = omap_sham_init,
1466 .update = omap_sham_update,
1467 .final = omap_sham_final,
1468 .finup = omap_sham_finup,
1469 .digest = omap_sham_digest,
1470 .halg.digestsize = MD5_DIGEST_SIZE,
1473 .cra_driver_name = "omap-md5",
1474 .cra_priority = 400,
1475 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1477 CRYPTO_ALG_NEED_FALLBACK,
1478 .cra_blocksize = SHA1_BLOCK_SIZE,
1479 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1480 .cra_alignmask = OMAP_ALIGN_MASK,
1481 .cra_module = THIS_MODULE,
1482 .cra_init = omap_sham_cra_init,
1483 .cra_exit = omap_sham_cra_exit,
1487 .init = omap_sham_init,
1488 .update = omap_sham_update,
1489 .final = omap_sham_final,
1490 .finup = omap_sham_finup,
1491 .digest = omap_sham_digest,
1492 .setkey = omap_sham_setkey,
1493 .halg.digestsize = SHA1_DIGEST_SIZE,
1495 .cra_name = "hmac(sha1)",
1496 .cra_driver_name = "omap-hmac-sha1",
1497 .cra_priority = 400,
1498 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1500 CRYPTO_ALG_NEED_FALLBACK,
1501 .cra_blocksize = SHA1_BLOCK_SIZE,
1502 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1503 sizeof(struct omap_sham_hmac_ctx),
1504 .cra_alignmask = OMAP_ALIGN_MASK,
1505 .cra_module = THIS_MODULE,
1506 .cra_init = omap_sham_cra_sha1_init,
1507 .cra_exit = omap_sham_cra_exit,
1511 .init = omap_sham_init,
1512 .update = omap_sham_update,
1513 .final = omap_sham_final,
1514 .finup = omap_sham_finup,
1515 .digest = omap_sham_digest,
1516 .setkey = omap_sham_setkey,
1517 .halg.digestsize = MD5_DIGEST_SIZE,
1519 .cra_name = "hmac(md5)",
1520 .cra_driver_name = "omap-hmac-md5",
1521 .cra_priority = 400,
1522 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1524 CRYPTO_ALG_NEED_FALLBACK,
1525 .cra_blocksize = SHA1_BLOCK_SIZE,
1526 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1527 sizeof(struct omap_sham_hmac_ctx),
1528 .cra_alignmask = OMAP_ALIGN_MASK,
1529 .cra_module = THIS_MODULE,
1530 .cra_init = omap_sham_cra_md5_init,
1531 .cra_exit = omap_sham_cra_exit,
1536 /* OMAP4 has some algs in addition to what OMAP2 has */
1537 static struct ahash_alg algs_sha224_sha256[] = {
1539 .init = omap_sham_init,
1540 .update = omap_sham_update,
1541 .final = omap_sham_final,
1542 .finup = omap_sham_finup,
1543 .digest = omap_sham_digest,
1544 .halg.digestsize = SHA224_DIGEST_SIZE,
1546 .cra_name = "sha224",
1547 .cra_driver_name = "omap-sha224",
1548 .cra_priority = 400,
1549 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1551 CRYPTO_ALG_NEED_FALLBACK,
1552 .cra_blocksize = SHA224_BLOCK_SIZE,
1553 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1554 .cra_alignmask = OMAP_ALIGN_MASK,
1555 .cra_module = THIS_MODULE,
1556 .cra_init = omap_sham_cra_init,
1557 .cra_exit = omap_sham_cra_exit,
1561 .init = omap_sham_init,
1562 .update = omap_sham_update,
1563 .final = omap_sham_final,
1564 .finup = omap_sham_finup,
1565 .digest = omap_sham_digest,
1566 .halg.digestsize = SHA256_DIGEST_SIZE,
1568 .cra_name = "sha256",
1569 .cra_driver_name = "omap-sha256",
1570 .cra_priority = 400,
1571 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1573 CRYPTO_ALG_NEED_FALLBACK,
1574 .cra_blocksize = SHA256_BLOCK_SIZE,
1575 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1576 .cra_alignmask = OMAP_ALIGN_MASK,
1577 .cra_module = THIS_MODULE,
1578 .cra_init = omap_sham_cra_init,
1579 .cra_exit = omap_sham_cra_exit,
1583 .init = omap_sham_init,
1584 .update = omap_sham_update,
1585 .final = omap_sham_final,
1586 .finup = omap_sham_finup,
1587 .digest = omap_sham_digest,
1588 .setkey = omap_sham_setkey,
1589 .halg.digestsize = SHA224_DIGEST_SIZE,
1591 .cra_name = "hmac(sha224)",
1592 .cra_driver_name = "omap-hmac-sha224",
1593 .cra_priority = 400,
1594 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1596 CRYPTO_ALG_NEED_FALLBACK,
1597 .cra_blocksize = SHA224_BLOCK_SIZE,
1598 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1599 sizeof(struct omap_sham_hmac_ctx),
1600 .cra_alignmask = OMAP_ALIGN_MASK,
1601 .cra_module = THIS_MODULE,
1602 .cra_init = omap_sham_cra_sha224_init,
1603 .cra_exit = omap_sham_cra_exit,
1607 .init = omap_sham_init,
1608 .update = omap_sham_update,
1609 .final = omap_sham_final,
1610 .finup = omap_sham_finup,
1611 .digest = omap_sham_digest,
1612 .setkey = omap_sham_setkey,
1613 .halg.digestsize = SHA256_DIGEST_SIZE,
1615 .cra_name = "hmac(sha256)",
1616 .cra_driver_name = "omap-hmac-sha256",
1617 .cra_priority = 400,
1618 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1620 CRYPTO_ALG_NEED_FALLBACK,
1621 .cra_blocksize = SHA256_BLOCK_SIZE,
1622 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1623 sizeof(struct omap_sham_hmac_ctx),
1624 .cra_alignmask = OMAP_ALIGN_MASK,
1625 .cra_module = THIS_MODULE,
1626 .cra_init = omap_sham_cra_sha256_init,
1627 .cra_exit = omap_sham_cra_exit,
1632 static struct ahash_alg algs_sha384_sha512[] = {
1634 .init = omap_sham_init,
1635 .update = omap_sham_update,
1636 .final = omap_sham_final,
1637 .finup = omap_sham_finup,
1638 .digest = omap_sham_digest,
1639 .halg.digestsize = SHA384_DIGEST_SIZE,
1641 .cra_name = "sha384",
1642 .cra_driver_name = "omap-sha384",
1643 .cra_priority = 400,
1644 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1646 CRYPTO_ALG_NEED_FALLBACK,
1647 .cra_blocksize = SHA384_BLOCK_SIZE,
1648 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1649 .cra_alignmask = OMAP_ALIGN_MASK,
1650 .cra_module = THIS_MODULE,
1651 .cra_init = omap_sham_cra_init,
1652 .cra_exit = omap_sham_cra_exit,
1656 .init = omap_sham_init,
1657 .update = omap_sham_update,
1658 .final = omap_sham_final,
1659 .finup = omap_sham_finup,
1660 .digest = omap_sham_digest,
1661 .halg.digestsize = SHA512_DIGEST_SIZE,
1663 .cra_name = "sha512",
1664 .cra_driver_name = "omap-sha512",
1665 .cra_priority = 400,
1666 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1668 CRYPTO_ALG_NEED_FALLBACK,
1669 .cra_blocksize = SHA512_BLOCK_SIZE,
1670 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1671 .cra_alignmask = OMAP_ALIGN_MASK,
1672 .cra_module = THIS_MODULE,
1673 .cra_init = omap_sham_cra_init,
1674 .cra_exit = omap_sham_cra_exit,
1678 .init = omap_sham_init,
1679 .update = omap_sham_update,
1680 .final = omap_sham_final,
1681 .finup = omap_sham_finup,
1682 .digest = omap_sham_digest,
1683 .setkey = omap_sham_setkey,
1684 .halg.digestsize = SHA384_DIGEST_SIZE,
1686 .cra_name = "hmac(sha384)",
1687 .cra_driver_name = "omap-hmac-sha384",
1688 .cra_priority = 400,
1689 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1691 CRYPTO_ALG_NEED_FALLBACK,
1692 .cra_blocksize = SHA384_BLOCK_SIZE,
1693 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1694 sizeof(struct omap_sham_hmac_ctx),
1695 .cra_alignmask = OMAP_ALIGN_MASK,
1696 .cra_module = THIS_MODULE,
1697 .cra_init = omap_sham_cra_sha384_init,
1698 .cra_exit = omap_sham_cra_exit,
1702 .init = omap_sham_init,
1703 .update = omap_sham_update,
1704 .final = omap_sham_final,
1705 .finup = omap_sham_finup,
1706 .digest = omap_sham_digest,
1707 .setkey = omap_sham_setkey,
1708 .halg.digestsize = SHA512_DIGEST_SIZE,
1710 .cra_name = "hmac(sha512)",
1711 .cra_driver_name = "omap-hmac-sha512",
1712 .cra_priority = 400,
1713 .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1715 CRYPTO_ALG_NEED_FALLBACK,
1716 .cra_blocksize = SHA512_BLOCK_SIZE,
1717 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1718 sizeof(struct omap_sham_hmac_ctx),
1719 .cra_alignmask = OMAP_ALIGN_MASK,
1720 .cra_module = THIS_MODULE,
1721 .cra_init = omap_sham_cra_sha512_init,
1722 .cra_exit = omap_sham_cra_exit,
1727 static void omap_sham_done_task(unsigned long data)
1729 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
1732 dev_dbg(dd->dev, "%s: flags=%lx\n", __func__, dd->flags);
1734 if (test_bit(FLAGS_CPU, &dd->flags)) {
1735 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
1737 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1738 if (test_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1739 omap_sham_update_dma_stop(dd);
1745 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1746 /* hash or semi-hash ready */
1747 clear_bit(FLAGS_DMA_READY, &dd->flags);
1755 dev_dbg(dd->dev, "update done: err: %d\n", err);
1756 /* finish curent request */
1757 omap_sham_finish_req(dd->req, err);
1760 static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1762 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1763 tasklet_schedule(&dd->done_task);
1768 static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
1770 struct omap_sham_dev *dd = dev_id;
1772 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
1773 /* final -> allow device to go to power-saving mode */
1774 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1776 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1777 SHA_REG_CTRL_OUTPUT_READY);
1778 omap_sham_read(dd, SHA_REG_CTRL);
1780 return omap_sham_irq_common(dd);
1783 static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
1785 struct omap_sham_dev *dd = dev_id;
1787 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
1789 return omap_sham_irq_common(dd);
1792 static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1794 .algs_list = algs_sha1_md5,
1795 .size = ARRAY_SIZE(algs_sha1_md5),
1799 static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
1800 .algs_info = omap_sham_algs_info_omap2,
1801 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
1802 .flags = BIT(FLAGS_BE32_SHA1),
1803 .digest_size = SHA1_DIGEST_SIZE,
1804 .copy_hash = omap_sham_copy_hash_omap2,
1805 .write_ctrl = omap_sham_write_ctrl_omap2,
1806 .trigger = omap_sham_trigger_omap2,
1807 .poll_irq = omap_sham_poll_irq_omap2,
1808 .intr_hdlr = omap_sham_irq_omap2,
1809 .idigest_ofs = 0x00,
1814 .sysstatus_ofs = 0x64,
1822 static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1824 .algs_list = algs_sha1_md5,
1825 .size = ARRAY_SIZE(algs_sha1_md5),
1828 .algs_list = algs_sha224_sha256,
1829 .size = ARRAY_SIZE(algs_sha224_sha256),
1833 static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
1834 .algs_info = omap_sham_algs_info_omap4,
1835 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
1836 .flags = BIT(FLAGS_AUTO_XOR),
1837 .digest_size = SHA256_DIGEST_SIZE,
1838 .copy_hash = omap_sham_copy_hash_omap4,
1839 .write_ctrl = omap_sham_write_ctrl_omap4,
1840 .trigger = omap_sham_trigger_omap4,
1841 .poll_irq = omap_sham_poll_irq_omap4,
1842 .intr_hdlr = omap_sham_irq_omap4,
1843 .idigest_ofs = 0x020,
1846 .digcnt_ofs = 0x040,
1849 .sysstatus_ofs = 0x114,
1852 .major_mask = 0x0700,
1854 .minor_mask = 0x003f,
1858 static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1860 .algs_list = algs_sha1_md5,
1861 .size = ARRAY_SIZE(algs_sha1_md5),
1864 .algs_list = algs_sha224_sha256,
1865 .size = ARRAY_SIZE(algs_sha224_sha256),
1868 .algs_list = algs_sha384_sha512,
1869 .size = ARRAY_SIZE(algs_sha384_sha512),
1873 static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1874 .algs_info = omap_sham_algs_info_omap5,
1875 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1876 .flags = BIT(FLAGS_AUTO_XOR),
1877 .digest_size = SHA512_DIGEST_SIZE,
1878 .copy_hash = omap_sham_copy_hash_omap4,
1879 .write_ctrl = omap_sham_write_ctrl_omap4,
1880 .trigger = omap_sham_trigger_omap4,
1881 .poll_irq = omap_sham_poll_irq_omap4,
1882 .intr_hdlr = omap_sham_irq_omap4,
1883 .idigest_ofs = 0x240,
1884 .odigest_ofs = 0x200,
1886 .digcnt_ofs = 0x280,
1889 .sysstatus_ofs = 0x114,
1891 .length_ofs = 0x288,
1892 .major_mask = 0x0700,
1894 .minor_mask = 0x003f,
1898 static const struct of_device_id omap_sham_of_match[] = {
1900 .compatible = "ti,omap2-sham",
1901 .data = &omap_sham_pdata_omap2,
1904 .compatible = "ti,omap3-sham",
1905 .data = &omap_sham_pdata_omap2,
1908 .compatible = "ti,omap4-sham",
1909 .data = &omap_sham_pdata_omap4,
1912 .compatible = "ti,omap5-sham",
1913 .data = &omap_sham_pdata_omap5,
1917 MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1919 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1920 struct device *dev, struct resource *res)
1922 struct device_node *node = dev->of_node;
1925 dd->pdata = of_device_get_match_data(dev);
1927 dev_err(dev, "no compatible OF match\n");
1932 err = of_address_to_resource(node, 0, res);
1934 dev_err(dev, "can't translate OF node address\n");
1939 dd->irq = irq_of_parse_and_map(node, 0);
1941 dev_err(dev, "can't translate OF irq value\n");
1950 static const struct of_device_id omap_sham_of_match[] = {
1954 static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1955 struct device *dev, struct resource *res)
1961 static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1962 struct platform_device *pdev, struct resource *res)
1964 struct device *dev = &pdev->dev;
1968 /* Get the base address */
1969 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1971 dev_err(dev, "no MEM resource info\n");
1975 memcpy(res, r, sizeof(*res));
1978 dd->irq = platform_get_irq(pdev, 0);
1984 /* Only OMAP2/3 can be non-DT */
1985 dd->pdata = &omap_sham_pdata_omap2;
1991 static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
1994 struct omap_sham_dev *dd = dev_get_drvdata(dev);
1996 return sprintf(buf, "%d\n", dd->fallback_sz);
1999 static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
2000 const char *buf, size_t size)
2002 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2006 status = kstrtol(buf, 0, &value);
2010 /* HW accelerator only works with buffers > 9 */
2012 dev_err(dev, "minimum fallback size 9\n");
2016 dd->fallback_sz = value;
2021 static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
2024 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2026 return sprintf(buf, "%d\n", dd->queue.max_qlen);
2029 static ssize_t queue_len_store(struct device *dev,
2030 struct device_attribute *attr, const char *buf,
2033 struct omap_sham_dev *dd = dev_get_drvdata(dev);
2037 status = kstrtol(buf, 0, &value);
2045 * Changing the queue size in fly is safe, if size becomes smaller
2046 * than current size, it will just not accept new entries until
2047 * it has shrank enough.
2049 dd->queue.max_qlen = value;
2054 static DEVICE_ATTR_RW(queue_len);
2055 static DEVICE_ATTR_RW(fallback);
2057 static struct attribute *omap_sham_attrs[] = {
2058 &dev_attr_queue_len.attr,
2059 &dev_attr_fallback.attr,
2063 static struct attribute_group omap_sham_attr_group = {
2064 .attrs = omap_sham_attrs,
2067 static int omap_sham_probe(struct platform_device *pdev)
2069 struct omap_sham_dev *dd;
2070 struct device *dev = &pdev->dev;
2071 struct resource res;
2072 dma_cap_mask_t mask;
2076 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
2078 dev_err(dev, "unable to alloc data struct.\n");
2083 platform_set_drvdata(pdev, dd);
2085 INIT_LIST_HEAD(&dd->list);
2086 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
2087 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
2089 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
2090 omap_sham_get_res_pdev(dd, pdev, &res);
2094 dd->io_base = devm_ioremap_resource(dev, &res);
2095 if (IS_ERR(dd->io_base)) {
2096 err = PTR_ERR(dd->io_base);
2099 dd->phys_base = res.start;
2101 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
2102 IRQF_TRIGGER_NONE, dev_name(dev), dd);
2104 dev_err(dev, "unable to request irq %d, err = %d\n",
2110 dma_cap_set(DMA_SLAVE, mask);
2112 dd->dma_lch = dma_request_chan(dev, "rx");
2113 if (IS_ERR(dd->dma_lch)) {
2114 err = PTR_ERR(dd->dma_lch);
2115 if (err == -EPROBE_DEFER)
2118 dd->polling_mode = 1;
2119 dev_dbg(dev, "using polling mode instead of dma\n");
2122 dd->flags |= dd->pdata->flags;
2123 sham.flags |= dd->pdata->flags;
2125 pm_runtime_use_autosuspend(dev);
2126 pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
2128 dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD;
2130 pm_runtime_enable(dev);
2131 pm_runtime_irq_safe(dev);
2133 err = pm_runtime_resume_and_get(dev);
2135 dev_err(dev, "failed to get sync: %d\n", err);
2139 rev = omap_sham_read(dd, SHA_REG_REV(dd));
2140 pm_runtime_put_sync(&pdev->dev);
2142 dev_info(dev, "hw accel on OMAP rev %u.%u\n",
2143 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
2144 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
2146 spin_lock_bh(&sham.lock);
2147 list_add_tail(&dd->list, &sham.dev_list);
2148 spin_unlock_bh(&sham.lock);
2150 dd->engine = crypto_engine_alloc_init(dev, 1);
2156 err = crypto_engine_start(dd->engine);
2158 goto err_engine_start;
2160 for (i = 0; i < dd->pdata->algs_info_size; i++) {
2161 if (dd->pdata->algs_info[i].registered)
2164 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
2165 struct ahash_alg *alg;
2167 alg = &dd->pdata->algs_info[i].algs_list[j];
2168 alg->export = omap_sham_export;
2169 alg->import = omap_sham_import;
2170 alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
2172 err = crypto_register_ahash(alg);
2176 dd->pdata->algs_info[i].registered++;
2180 err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group);
2182 dev_err(dev, "could not create sysfs device attrs\n");
2189 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2190 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2191 crypto_unregister_ahash(
2192 &dd->pdata->algs_info[i].algs_list[j]);
2194 crypto_engine_exit(dd->engine);
2196 spin_lock_bh(&sham.lock);
2197 list_del(&dd->list);
2198 spin_unlock_bh(&sham.lock);
2200 pm_runtime_disable(dev);
2201 if (!dd->polling_mode)
2202 dma_release_channel(dd->dma_lch);
2204 dev_err(dev, "initialization failed.\n");
2209 static int omap_sham_remove(struct platform_device *pdev)
2211 struct omap_sham_dev *dd;
2214 dd = platform_get_drvdata(pdev);
2217 spin_lock_bh(&sham.lock);
2218 list_del(&dd->list);
2219 spin_unlock_bh(&sham.lock);
2220 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2221 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
2222 crypto_unregister_ahash(
2223 &dd->pdata->algs_info[i].algs_list[j]);
2224 dd->pdata->algs_info[i].registered--;
2226 tasklet_kill(&dd->done_task);
2227 pm_runtime_disable(&pdev->dev);
2229 if (!dd->polling_mode)
2230 dma_release_channel(dd->dma_lch);
2232 sysfs_remove_group(&dd->dev->kobj, &omap_sham_attr_group);
2237 #ifdef CONFIG_PM_SLEEP
2238 static int omap_sham_suspend(struct device *dev)
2240 pm_runtime_put_sync(dev);
2244 static int omap_sham_resume(struct device *dev)
2246 int err = pm_runtime_resume_and_get(dev);
2248 dev_err(dev, "failed to get sync: %d\n", err);
2255 static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
2257 static struct platform_driver omap_sham_driver = {
2258 .probe = omap_sham_probe,
2259 .remove = omap_sham_remove,
2261 .name = "omap-sham",
2262 .pm = &omap_sham_pm_ops,
2263 .of_match_table = omap_sham_of_match,
2267 module_platform_driver(omap_sham_driver);
2269 MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2270 MODULE_LICENSE("GPL v2");
2271 MODULE_AUTHOR("Dmitry Kasatkin");
2272 MODULE_ALIAS("platform:omap-sham");