2 * Provide TDMA helper functions used by cipher and hash algorithm
5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
6 * Author: Arnaud Ebalard <arno@natisbad.org>
8 * This work is based on an initial version written by
9 * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
18 bool mv_cesa_req_dma_iter_next_transfer(struct mv_cesa_dma_iter *iter,
19 struct mv_cesa_sg_dma_iter *sgiter,
25 sgiter->op_offset += len;
26 sgiter->offset += len;
27 if (sgiter->offset == sg_dma_len(sgiter->sg)) {
28 if (sg_is_last(sgiter->sg))
31 sgiter->sg = sg_next(sgiter->sg);
34 if (sgiter->op_offset == iter->op_len)
40 void mv_cesa_dma_step(struct mv_cesa_req *dreq)
42 struct mv_cesa_engine *engine = dreq->engine;
44 writel_relaxed(0, engine->regs + CESA_SA_CFG);
46 mv_cesa_set_int_mask(engine, CESA_SA_INT_ACC0_IDMA_DONE);
47 writel_relaxed(CESA_TDMA_DST_BURST_128B | CESA_TDMA_SRC_BURST_128B |
48 CESA_TDMA_NO_BYTE_SWAP | CESA_TDMA_EN,
49 engine->regs + CESA_TDMA_CONTROL);
51 writel_relaxed(CESA_SA_CFG_ACT_CH0_IDMA | CESA_SA_CFG_MULTI_PKT |
52 CESA_SA_CFG_CH0_W_IDMA | CESA_SA_CFG_PARA_DIS,
53 engine->regs + CESA_SA_CFG);
54 writel_relaxed(dreq->chain.first->cur_dma,
55 engine->regs + CESA_TDMA_NEXT_ADDR);
56 BUG_ON(readl(engine->regs + CESA_SA_CMD) &
57 CESA_SA_CMD_EN_CESA_SA_ACCL0);
58 writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
61 void mv_cesa_dma_cleanup(struct mv_cesa_req *dreq)
63 struct mv_cesa_tdma_desc *tdma;
65 for (tdma = dreq->chain.first; tdma;) {
66 struct mv_cesa_tdma_desc *old_tdma = tdma;
67 u32 type = tdma->flags & CESA_TDMA_TYPE_MSK;
69 if (type == CESA_TDMA_OP)
70 dma_pool_free(cesa_dev->dma->op_pool, tdma->op,
71 le32_to_cpu(tdma->src));
72 else if (type == CESA_TDMA_IV)
73 dma_pool_free(cesa_dev->dma->iv_pool, tdma->data,
74 le32_to_cpu(tdma->dst));
77 dma_pool_free(cesa_dev->dma->tdma_desc_pool, old_tdma,
81 dreq->chain.first = NULL;
82 dreq->chain.last = NULL;
85 void mv_cesa_dma_prepare(struct mv_cesa_req *dreq,
86 struct mv_cesa_engine *engine)
88 struct mv_cesa_tdma_desc *tdma;
90 for (tdma = dreq->chain.first; tdma; tdma = tdma->next) {
91 if (tdma->flags & CESA_TDMA_DST_IN_SRAM)
92 tdma->dst = cpu_to_le32(tdma->dst + engine->sram_dma);
94 if (tdma->flags & CESA_TDMA_SRC_IN_SRAM)
95 tdma->src = cpu_to_le32(tdma->src + engine->sram_dma);
97 if ((tdma->flags & CESA_TDMA_TYPE_MSK) == CESA_TDMA_OP)
98 mv_cesa_adjust_op(engine, tdma->op);
102 void mv_cesa_tdma_chain(struct mv_cesa_engine *engine,
103 struct mv_cesa_req *dreq)
105 if (engine->chain.first == NULL && engine->chain.last == NULL) {
106 engine->chain.first = dreq->chain.first;
107 engine->chain.last = dreq->chain.last;
109 struct mv_cesa_tdma_desc *last;
111 last = engine->chain.last;
112 last->next = dreq->chain.first;
113 engine->chain.last = dreq->chain.last;
116 * Break the DMA chain if the CESA_TDMA_BREAK_CHAIN is set on
117 * the last element of the current chain, or if the request
118 * being queued needs the IV regs to be set before lauching
121 if (!(last->flags & CESA_TDMA_BREAK_CHAIN) &&
122 !(dreq->chain.first->flags & CESA_TDMA_SET_STATE))
123 last->next_dma = dreq->chain.first->cur_dma;
127 int mv_cesa_tdma_process(struct mv_cesa_engine *engine, u32 status)
129 struct crypto_async_request *req = NULL;
130 struct mv_cesa_tdma_desc *tdma = NULL, *next = NULL;
134 tdma_cur = readl(engine->regs + CESA_TDMA_CUR);
136 for (tdma = engine->chain.first; tdma; tdma = next) {
137 spin_lock_bh(&engine->lock);
139 spin_unlock_bh(&engine->lock);
141 if (tdma->flags & CESA_TDMA_END_OF_REQ) {
142 struct crypto_async_request *backlog = NULL;
143 struct mv_cesa_ctx *ctx;
146 spin_lock_bh(&engine->lock);
148 * if req is NULL, this means we're processing the
149 * request in engine->req.
154 req = mv_cesa_dequeue_req_locked(engine,
157 /* Re-chaining to the next request */
158 engine->chain.first = tdma->next;
161 /* If this is the last request, clear the chain */
162 if (engine->chain.first == NULL)
163 engine->chain.last = NULL;
164 spin_unlock_bh(&engine->lock);
166 ctx = crypto_tfm_ctx(req->tfm);
167 current_status = (tdma->cur_dma == tdma_cur) ?
168 status : CESA_SA_INT_ACC0_IDMA_DONE;
169 res = ctx->ops->process(req, current_status);
170 ctx->ops->complete(req);
173 mv_cesa_engine_enqueue_complete_request(engine,
177 backlog->complete(backlog, -EINPROGRESS);
180 if (res || tdma->cur_dma == tdma_cur)
184 /* Save the last request in error to engine->req, so that the core
185 * knows which request was fautly */
187 spin_lock_bh(&engine->lock);
189 spin_unlock_bh(&engine->lock);
195 static struct mv_cesa_tdma_desc *
196 mv_cesa_dma_add_desc(struct mv_cesa_tdma_chain *chain, gfp_t flags)
198 struct mv_cesa_tdma_desc *new_tdma = NULL;
199 dma_addr_t dma_handle;
201 new_tdma = dma_pool_zalloc(cesa_dev->dma->tdma_desc_pool, flags,
204 return ERR_PTR(-ENOMEM);
206 new_tdma->cur_dma = dma_handle;
208 chain->last->next_dma = cpu_to_le32(dma_handle);
209 chain->last->next = new_tdma;
211 chain->first = new_tdma;
214 chain->last = new_tdma;
219 int mv_cesa_dma_add_iv_op(struct mv_cesa_tdma_chain *chain, dma_addr_t src,
220 u32 size, u32 flags, gfp_t gfp_flags)
223 struct mv_cesa_tdma_desc *tdma;
225 dma_addr_t dma_handle;
227 tdma = mv_cesa_dma_add_desc(chain, gfp_flags);
229 return PTR_ERR(tdma);
231 iv = dma_pool_alloc(cesa_dev->dma->iv_pool, gfp_flags, &dma_handle);
235 tdma->byte_cnt = cpu_to_le32(size | BIT(31));
237 tdma->dst = cpu_to_le32(dma_handle);
240 flags &= (CESA_TDMA_DST_IN_SRAM | CESA_TDMA_SRC_IN_SRAM);
241 tdma->flags = flags | CESA_TDMA_IV;
245 struct mv_cesa_op_ctx *mv_cesa_dma_add_op(struct mv_cesa_tdma_chain *chain,
246 const struct mv_cesa_op_ctx *op_templ,
250 struct mv_cesa_tdma_desc *tdma;
251 struct mv_cesa_op_ctx *op;
252 dma_addr_t dma_handle;
255 tdma = mv_cesa_dma_add_desc(chain, flags);
257 return ERR_CAST(tdma);
259 op = dma_pool_alloc(cesa_dev->dma->op_pool, flags, &dma_handle);
261 return ERR_PTR(-ENOMEM);
265 size = skip_ctx ? sizeof(op->desc) : sizeof(*op);
269 tdma->byte_cnt = cpu_to_le32(size | BIT(31));
270 tdma->src = cpu_to_le32(dma_handle);
271 tdma->dst = CESA_SA_CFG_SRAM_OFFSET;
272 tdma->flags = CESA_TDMA_DST_IN_SRAM | CESA_TDMA_OP;
277 int mv_cesa_dma_add_data_transfer(struct mv_cesa_tdma_chain *chain,
278 dma_addr_t dst, dma_addr_t src, u32 size,
279 u32 flags, gfp_t gfp_flags)
281 struct mv_cesa_tdma_desc *tdma;
283 tdma = mv_cesa_dma_add_desc(chain, gfp_flags);
285 return PTR_ERR(tdma);
287 tdma->byte_cnt = cpu_to_le32(size | BIT(31));
291 flags &= (CESA_TDMA_DST_IN_SRAM | CESA_TDMA_SRC_IN_SRAM);
292 tdma->flags = flags | CESA_TDMA_DATA;
297 int mv_cesa_dma_add_dummy_launch(struct mv_cesa_tdma_chain *chain, gfp_t flags)
299 struct mv_cesa_tdma_desc *tdma;
301 tdma = mv_cesa_dma_add_desc(chain, flags);
303 return PTR_ERR(tdma);
308 int mv_cesa_dma_add_dummy_end(struct mv_cesa_tdma_chain *chain, gfp_t flags)
310 struct mv_cesa_tdma_desc *tdma;
312 tdma = mv_cesa_dma_add_desc(chain, flags);
314 return PTR_ERR(tdma);
316 tdma->byte_cnt = cpu_to_le32(BIT(31));
321 int mv_cesa_dma_add_op_transfers(struct mv_cesa_tdma_chain *chain,
322 struct mv_cesa_dma_iter *dma_iter,
323 struct mv_cesa_sg_dma_iter *sgiter,
326 u32 flags = sgiter->dir == DMA_TO_DEVICE ?
327 CESA_TDMA_DST_IN_SRAM : CESA_TDMA_SRC_IN_SRAM;
334 len = mv_cesa_req_dma_iter_transfer_len(dma_iter, sgiter);
335 if (sgiter->dir == DMA_TO_DEVICE) {
336 dst = CESA_SA_DATA_SRAM_OFFSET + sgiter->op_offset;
337 src = sg_dma_address(sgiter->sg) + sgiter->offset;
339 dst = sg_dma_address(sgiter->sg) + sgiter->offset;
340 src = CESA_SA_DATA_SRAM_OFFSET + sgiter->op_offset;
343 ret = mv_cesa_dma_add_data_transfer(chain, dst, src, len,
348 } while (mv_cesa_req_dma_iter_next_transfer(dma_iter, sgiter, len));