1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2020 Marvell. */
4 #include "otx2_cpt_common.h"
5 #include "otx2_cptvf.h"
6 #include "otx2_cptlf.h"
7 #include "otx2_cptvf_algs.h"
11 #define OTX2_CPTVF_DRV_NAME "rvu_cptvf"
13 static void cptvf_enable_pfvf_mbox_intrs(struct otx2_cptvf_dev *cptvf)
15 /* Clear interrupt if any */
16 otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, OTX2_RVU_VF_INT,
19 /* Enable PF-VF interrupt */
20 otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0,
21 OTX2_RVU_VF_INT_ENA_W1S, 0x1ULL);
24 static void cptvf_disable_pfvf_mbox_intrs(struct otx2_cptvf_dev *cptvf)
26 /* Disable PF-VF interrupt */
27 otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0,
28 OTX2_RVU_VF_INT_ENA_W1C, 0x1ULL);
30 /* Clear interrupt if any */
31 otx2_cpt_write64(cptvf->reg_base, BLKADDR_RVUM, 0, OTX2_RVU_VF_INT,
35 static int cptvf_register_interrupts(struct otx2_cptvf_dev *cptvf)
40 num_vec = pci_msix_vec_count(cptvf->pdev);
45 ret = pci_alloc_irq_vectors(cptvf->pdev, num_vec, num_vec,
48 dev_err(&cptvf->pdev->dev,
49 "Request for %d msix vectors failed\n", num_vec);
52 irq = pci_irq_vector(cptvf->pdev, OTX2_CPT_VF_INT_VEC_E_MBOX);
53 /* Register VF<=>PF mailbox interrupt handler */
54 ret = devm_request_irq(&cptvf->pdev->dev, irq,
55 otx2_cptvf_pfvf_mbox_intr, 0,
56 "CPTPFVF Mbox", cptvf);
59 /* Enable PF-VF mailbox interrupts */
60 cptvf_enable_pfvf_mbox_intrs(cptvf);
62 ret = otx2_cpt_send_ready_msg(&cptvf->pfvf_mbox, cptvf->pdev);
64 dev_warn(&cptvf->pdev->dev,
65 "PF not responding to mailbox, deferring probe\n");
66 cptvf_disable_pfvf_mbox_intrs(cptvf);
72 static int cptvf_pfvf_mbox_init(struct otx2_cptvf_dev *cptvf)
74 struct pci_dev *pdev = cptvf->pdev;
75 resource_size_t offset, size;
78 cptvf->pfvf_mbox_wq = alloc_workqueue("cpt_pfvf_mailbox",
79 WQ_UNBOUND | WQ_HIGHPRI |
81 if (!cptvf->pfvf_mbox_wq)
84 if (test_bit(CN10K_MBOX, &cptvf->cap_flag)) {
85 /* For cn10k platform, VF mailbox region is in its BAR2
88 cptvf->pfvf_mbox_base = cptvf->reg_base +
89 CN10K_CPT_VF_MBOX_REGION;
91 offset = pci_resource_start(pdev, PCI_MBOX_BAR_NUM);
92 size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);
93 /* Map PF-VF mailbox memory */
94 cptvf->pfvf_mbox_base = devm_ioremap_wc(&pdev->dev, offset,
96 if (!cptvf->pfvf_mbox_base) {
97 dev_err(&pdev->dev, "Unable to map BAR4\n");
103 ret = otx2_mbox_init(&cptvf->pfvf_mbox, cptvf->pfvf_mbox_base,
104 pdev, cptvf->reg_base, MBOX_DIR_VFPF, 1);
108 ret = otx2_cpt_mbox_bbuf_init(cptvf, pdev);
112 INIT_WORK(&cptvf->pfvf_mbox_work, otx2_cptvf_pfvf_mbox_handler);
116 otx2_mbox_destroy(&cptvf->pfvf_mbox);
118 destroy_workqueue(cptvf->pfvf_mbox_wq);
122 static void cptvf_pfvf_mbox_destroy(struct otx2_cptvf_dev *cptvf)
124 destroy_workqueue(cptvf->pfvf_mbox_wq);
125 otx2_mbox_destroy(&cptvf->pfvf_mbox);
128 static void cptlf_work_handler(unsigned long data)
130 otx2_cpt_post_process((struct otx2_cptlf_wqe *) data);
133 static void cleanup_tasklet_work(struct otx2_cptlfs_info *lfs)
137 for (i = 0; i < lfs->lfs_num; i++) {
141 tasklet_kill(&lfs->lf[i].wqe->work);
142 kfree(lfs->lf[i].wqe);
143 lfs->lf[i].wqe = NULL;
147 static int init_tasklet_work(struct otx2_cptlfs_info *lfs)
149 struct otx2_cptlf_wqe *wqe;
152 for (i = 0; i < lfs->lfs_num; i++) {
153 wqe = kzalloc(sizeof(struct otx2_cptlf_wqe), GFP_KERNEL);
156 goto cleanup_tasklet;
159 tasklet_init(&wqe->work, cptlf_work_handler, (u64) wqe);
162 lfs->lf[i].wqe = wqe;
167 cleanup_tasklet_work(lfs);
171 static void free_pending_queues(struct otx2_cptlfs_info *lfs)
175 for (i = 0; i < lfs->lfs_num; i++) {
176 kfree(lfs->lf[i].pqueue.head);
177 lfs->lf[i].pqueue.head = NULL;
181 static int alloc_pending_queues(struct otx2_cptlfs_info *lfs)
188 for (i = 0; i < lfs->lfs_num; i++) {
189 lfs->lf[i].pqueue.qlen = OTX2_CPT_INST_QLEN_MSGS;
190 size = lfs->lf[i].pqueue.qlen *
191 sizeof(struct otx2_cpt_pending_entry);
193 lfs->lf[i].pqueue.head = kzalloc(size, GFP_KERNEL);
194 if (!lfs->lf[i].pqueue.head) {
199 /* Initialize spin lock */
200 spin_lock_init(&lfs->lf[i].pqueue.lock);
205 free_pending_queues(lfs);
209 static void lf_sw_cleanup(struct otx2_cptlfs_info *lfs)
211 cleanup_tasklet_work(lfs);
212 free_pending_queues(lfs);
215 static int lf_sw_init(struct otx2_cptlfs_info *lfs)
219 ret = alloc_pending_queues(lfs);
221 dev_err(&lfs->pdev->dev,
222 "Allocating pending queues failed\n");
225 ret = init_tasklet_work(lfs);
227 dev_err(&lfs->pdev->dev,
228 "Tasklet work init failed\n");
229 goto pending_queues_free;
234 free_pending_queues(lfs);
238 static void cptvf_lf_shutdown(struct otx2_cptlfs_info *lfs)
240 atomic_set(&lfs->state, OTX2_CPTLF_IN_RESET);
242 /* Remove interrupts affinity */
243 otx2_cptlf_free_irqs_affinity(lfs);
244 /* Disable instruction queue */
245 otx2_cptlf_disable_iqueues(lfs);
246 /* Unregister crypto algorithms */
247 otx2_cpt_crypto_exit(lfs->pdev, THIS_MODULE);
248 /* Unregister LFs interrupts */
249 otx2_cptlf_unregister_interrupts(lfs);
250 /* Cleanup LFs software side */
252 /* Send request to detach LFs */
253 otx2_cpt_detach_rsrcs_msg(lfs);
256 static int cptvf_lf_init(struct otx2_cptvf_dev *cptvf)
258 struct otx2_cptlfs_info *lfs = &cptvf->lfs;
259 struct device *dev = &cptvf->pdev->dev;
263 /* Get engine group number for symmetric crypto */
264 cptvf->lfs.kcrypto_eng_grp_num = OTX2_CPT_INVALID_CRYPTO_ENG_GRP;
265 ret = otx2_cptvf_send_eng_grp_num_msg(cptvf, OTX2_CPT_SE_TYPES);
269 if (cptvf->lfs.kcrypto_eng_grp_num == OTX2_CPT_INVALID_CRYPTO_ENG_GRP) {
270 dev_err(dev, "Engine group for kernel crypto not available\n");
274 eng_grp_msk = 1 << cptvf->lfs.kcrypto_eng_grp_num;
276 ret = otx2_cptvf_send_kvf_limits_msg(cptvf);
280 lfs->reg_base = cptvf->reg_base;
281 lfs->pdev = cptvf->pdev;
282 lfs->mbox = &cptvf->pfvf_mbox;
284 lfs_num = cptvf->lfs.kvf_limits ? cptvf->lfs.kvf_limits :
286 ret = otx2_cptlf_init(lfs, eng_grp_msk, OTX2_CPT_QUEUE_HI_PRIO,
291 /* Get msix offsets for attached LFs */
292 ret = otx2_cpt_msix_offset_msg(lfs);
296 /* Initialize LFs software side */
297 ret = lf_sw_init(lfs);
301 /* Register LFs interrupts */
302 ret = otx2_cptlf_register_interrupts(lfs);
306 /* Set interrupts affinity */
307 ret = otx2_cptlf_set_irqs_affinity(lfs);
309 goto unregister_intr;
311 atomic_set(&lfs->state, OTX2_CPTLF_STARTED);
312 /* Register crypto algorithms */
313 ret = otx2_cpt_crypto_init(lfs->pdev, THIS_MODULE, lfs_num, 1);
315 dev_err(&lfs->pdev->dev, "algorithms registration failed\n");
321 otx2_cptlf_free_irqs_affinity(lfs);
323 otx2_cptlf_unregister_interrupts(lfs);
327 otx2_cptlf_shutdown(lfs);
332 static int otx2_cptvf_probe(struct pci_dev *pdev,
333 const struct pci_device_id *ent)
335 struct device *dev = &pdev->dev;
336 struct otx2_cptvf_dev *cptvf;
339 cptvf = devm_kzalloc(dev, sizeof(*cptvf), GFP_KERNEL);
343 ret = pcim_enable_device(pdev);
345 dev_err(dev, "Failed to enable PCI device\n");
349 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
351 dev_err(dev, "Unable to get usable DMA configuration\n");
354 /* Map VF's configuration registers */
355 ret = pcim_iomap_regions_request_all(pdev, 1 << PCI_PF_REG_BAR_NUM,
356 OTX2_CPTVF_DRV_NAME);
358 dev_err(dev, "Couldn't get PCI resources 0x%x\n", ret);
361 pci_set_master(pdev);
362 pci_set_drvdata(pdev, cptvf);
365 cptvf->reg_base = pcim_iomap_table(pdev)[PCI_PF_REG_BAR_NUM];
367 otx2_cpt_set_hw_caps(pdev, &cptvf->cap_flag);
369 ret = cn10k_cptvf_lmtst_init(cptvf);
373 /* Initialize PF<=>VF mailbox */
374 ret = cptvf_pfvf_mbox_init(cptvf);
378 /* Register interrupts */
379 ret = cptvf_register_interrupts(cptvf);
381 goto destroy_pfvf_mbox;
383 /* Initialize CPT LFs */
384 ret = cptvf_lf_init(cptvf);
386 goto unregister_interrupts;
390 unregister_interrupts:
391 cptvf_disable_pfvf_mbox_intrs(cptvf);
393 cptvf_pfvf_mbox_destroy(cptvf);
395 pci_set_drvdata(pdev, NULL);
400 static void otx2_cptvf_remove(struct pci_dev *pdev)
402 struct otx2_cptvf_dev *cptvf = pci_get_drvdata(pdev);
405 dev_err(&pdev->dev, "Invalid CPT VF device.\n");
408 cptvf_lf_shutdown(&cptvf->lfs);
409 /* Disable PF-VF mailbox interrupt */
410 cptvf_disable_pfvf_mbox_intrs(cptvf);
411 /* Destroy PF-VF mbox */
412 cptvf_pfvf_mbox_destroy(cptvf);
413 pci_set_drvdata(pdev, NULL);
416 /* Supported devices */
417 static const struct pci_device_id otx2_cptvf_id_table[] = {
418 {PCI_VDEVICE(CAVIUM, OTX2_CPT_PCI_VF_DEVICE_ID), 0},
419 {PCI_VDEVICE(CAVIUM, CN10K_CPT_PCI_VF_DEVICE_ID), 0},
420 { 0, } /* end of table */
423 static struct pci_driver otx2_cptvf_pci_driver = {
424 .name = OTX2_CPTVF_DRV_NAME,
425 .id_table = otx2_cptvf_id_table,
426 .probe = otx2_cptvf_probe,
427 .remove = otx2_cptvf_remove,
430 module_pci_driver(otx2_cptvf_pci_driver);
432 MODULE_AUTHOR("Marvell");
433 MODULE_DESCRIPTION("Marvell RVU CPT Virtual Function Driver");
434 MODULE_LICENSE("GPL v2");
435 MODULE_DEVICE_TABLE(pci, otx2_cptvf_id_table);