1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2020 Marvell. */
4 #include <linux/ctype.h>
5 #include <linux/firmware.h>
6 #include "otx2_cptpf_ucode.h"
7 #include "otx2_cpt_common.h"
8 #include "otx2_cptpf.h"
9 #include "otx2_cptlf.h"
10 #include "otx2_cpt_reqmgr.h"
15 #define LOADFVC_RLEN 8
16 #define LOADFVC_MAJOR_OP 0x01
17 #define LOADFVC_MINOR_OP 0x08
19 #define CTX_FLUSH_TIMER_CNT 0xFFFFFF
22 struct list_head ucodes;
25 static struct otx2_cpt_bitmap get_cores_bmap(struct device *dev,
26 struct otx2_cpt_eng_grp_info *eng_grp)
28 struct otx2_cpt_bitmap bmap = { {0} };
32 if (eng_grp->g->engs_num < 0 ||
33 eng_grp->g->engs_num > OTX2_CPT_MAX_ENGINES) {
34 dev_err(dev, "unsupported number of engines %d on octeontx2\n",
35 eng_grp->g->engs_num);
39 for (i = 0; i < OTX2_CPT_MAX_ETYPES_PER_GRP; i++) {
40 if (eng_grp->engs[i].type) {
41 bitmap_or(bmap.bits, bmap.bits,
42 eng_grp->engs[i].bmap,
43 eng_grp->g->engs_num);
44 bmap.size = eng_grp->g->engs_num;
50 dev_err(dev, "No engines reserved for engine group %d\n",
55 static int is_eng_type(int val, int eng_type)
57 return val & (1 << eng_type);
60 static int is_2nd_ucode_used(struct otx2_cpt_eng_grp_info *eng_grp)
62 if (eng_grp->ucode[1].type)
68 static void set_ucode_filename(struct otx2_cpt_ucode *ucode,
71 strlcpy(ucode->filename, filename, OTX2_CPT_NAME_LENGTH);
74 static char *get_eng_type_str(int eng_type)
76 char *str = "unknown";
79 case OTX2_CPT_SE_TYPES:
83 case OTX2_CPT_IE_TYPES:
87 case OTX2_CPT_AE_TYPES:
94 static char *get_ucode_type_str(int ucode_type)
96 char *str = "unknown";
99 case (1 << OTX2_CPT_SE_TYPES):
103 case (1 << OTX2_CPT_IE_TYPES):
107 case (1 << OTX2_CPT_AE_TYPES):
111 case (1 << OTX2_CPT_SE_TYPES | 1 << OTX2_CPT_IE_TYPES):
118 static int get_ucode_type(struct device *dev,
119 struct otx2_cpt_ucode_hdr *ucode_hdr,
122 struct otx2_cptpf_dev *cptpf = dev_get_drvdata(dev);
123 char ver_str_prefix[OTX2_CPT_UCODE_VER_STR_SZ];
124 char tmp_ver_str[OTX2_CPT_UCODE_VER_STR_SZ];
125 struct pci_dev *pdev = cptpf->pdev;
129 strlcpy(tmp_ver_str, ucode_hdr->ver_str, OTX2_CPT_UCODE_VER_STR_SZ);
130 for (i = 0; i < strlen(tmp_ver_str); i++)
131 tmp_ver_str[i] = tolower(tmp_ver_str[i]);
133 sprintf(ver_str_prefix, "ocpt-%02d", pdev->revision);
134 if (!strnstr(tmp_ver_str, ver_str_prefix, OTX2_CPT_UCODE_VER_STR_SZ))
137 nn = ucode_hdr->ver_num.nn;
138 if (strnstr(tmp_ver_str, "se-", OTX2_CPT_UCODE_VER_STR_SZ) &&
139 (nn == OTX2_CPT_SE_UC_TYPE1 || nn == OTX2_CPT_SE_UC_TYPE2 ||
140 nn == OTX2_CPT_SE_UC_TYPE3))
141 val |= 1 << OTX2_CPT_SE_TYPES;
142 if (strnstr(tmp_ver_str, "ie-", OTX2_CPT_UCODE_VER_STR_SZ) &&
143 (nn == OTX2_CPT_IE_UC_TYPE1 || nn == OTX2_CPT_IE_UC_TYPE2 ||
144 nn == OTX2_CPT_IE_UC_TYPE3))
145 val |= 1 << OTX2_CPT_IE_TYPES;
146 if (strnstr(tmp_ver_str, "ae", OTX2_CPT_UCODE_VER_STR_SZ) &&
147 nn == OTX2_CPT_AE_UC_TYPE)
148 val |= 1 << OTX2_CPT_AE_TYPES;
158 static int __write_ucode_base(struct otx2_cptpf_dev *cptpf, int eng,
159 dma_addr_t dma_addr, int blkaddr)
161 return otx2_cpt_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
162 CPT_AF_EXEX_UCODE_BASE(eng),
163 (u64)dma_addr, blkaddr);
166 static int cptx_set_ucode_base(struct otx2_cpt_eng_grp_info *eng_grp,
167 struct otx2_cptpf_dev *cptpf, int blkaddr)
169 struct otx2_cpt_engs_rsvd *engs;
173 /* Set PF number for microcode fetches */
174 ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
176 cptpf->pf_id << RVU_PFVF_PF_SHIFT, blkaddr);
180 for (i = 0; i < OTX2_CPT_MAX_ETYPES_PER_GRP; i++) {
181 engs = &eng_grp->engs[i];
185 dma_addr = engs->ucode->dma;
188 * Set UCODE_BASE only for the cores which are not used,
189 * other cores should have already valid UCODE_BASE set
191 for_each_set_bit(bit, engs->bmap, eng_grp->g->engs_num)
192 if (!eng_grp->g->eng_ref_cnt[bit]) {
193 ret = __write_ucode_base(cptpf, bit, dma_addr,
202 static int cpt_set_ucode_base(struct otx2_cpt_eng_grp_info *eng_grp, void *obj)
204 struct otx2_cptpf_dev *cptpf = obj;
207 if (cptpf->has_cpt1) {
208 ret = cptx_set_ucode_base(eng_grp, cptpf, BLKADDR_CPT1);
212 return cptx_set_ucode_base(eng_grp, cptpf, BLKADDR_CPT0);
215 static int cptx_detach_and_disable_cores(struct otx2_cpt_eng_grp_info *eng_grp,
216 struct otx2_cptpf_dev *cptpf,
217 struct otx2_cpt_bitmap bmap,
224 /* Detach the cores from group */
225 for_each_set_bit(i, bmap.bits, bmap.size) {
226 ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
227 CPT_AF_EXEX_CTL2(i), ®, blkaddr);
231 if (reg & (1ull << eng_grp->idx)) {
232 eng_grp->g->eng_ref_cnt[i]--;
233 reg &= ~(1ull << eng_grp->idx);
235 ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox,
237 CPT_AF_EXEX_CTL2(i), reg,
244 /* Wait for cores to become idle */
247 usleep_range(10000, 20000);
251 for_each_set_bit(i, bmap.bits, bmap.size) {
252 ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox,
254 CPT_AF_EXEX_STS(i), ®,
266 /* Disable the cores only if they are not used anymore */
267 for_each_set_bit(i, bmap.bits, bmap.size) {
268 if (!eng_grp->g->eng_ref_cnt[i]) {
269 ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox,
271 CPT_AF_EXEX_CTL(i), 0x0,
281 static int cpt_detach_and_disable_cores(struct otx2_cpt_eng_grp_info *eng_grp,
284 struct otx2_cptpf_dev *cptpf = obj;
285 struct otx2_cpt_bitmap bmap;
288 bmap = get_cores_bmap(&cptpf->pdev->dev, eng_grp);
292 if (cptpf->has_cpt1) {
293 ret = cptx_detach_and_disable_cores(eng_grp, cptpf, bmap,
298 return cptx_detach_and_disable_cores(eng_grp, cptpf, bmap,
302 static int cptx_attach_and_enable_cores(struct otx2_cpt_eng_grp_info *eng_grp,
303 struct otx2_cptpf_dev *cptpf,
304 struct otx2_cpt_bitmap bmap,
310 /* Attach the cores to the group */
311 for_each_set_bit(i, bmap.bits, bmap.size) {
312 ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
313 CPT_AF_EXEX_CTL2(i), ®, blkaddr);
317 if (!(reg & (1ull << eng_grp->idx))) {
318 eng_grp->g->eng_ref_cnt[i]++;
319 reg |= 1ull << eng_grp->idx;
321 ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox,
323 CPT_AF_EXEX_CTL2(i), reg,
330 /* Enable the cores */
331 for_each_set_bit(i, bmap.bits, bmap.size) {
332 ret = otx2_cpt_add_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
333 CPT_AF_EXEX_CTL(i), 0x1,
338 return otx2_cpt_send_af_reg_requests(&cptpf->afpf_mbox, cptpf->pdev);
341 static int cpt_attach_and_enable_cores(struct otx2_cpt_eng_grp_info *eng_grp,
344 struct otx2_cptpf_dev *cptpf = obj;
345 struct otx2_cpt_bitmap bmap;
348 bmap = get_cores_bmap(&cptpf->pdev->dev, eng_grp);
352 if (cptpf->has_cpt1) {
353 ret = cptx_attach_and_enable_cores(eng_grp, cptpf, bmap,
358 return cptx_attach_and_enable_cores(eng_grp, cptpf, bmap, BLKADDR_CPT0);
361 static int load_fw(struct device *dev, struct fw_info_t *fw_info,
364 struct otx2_cpt_ucode_hdr *ucode_hdr;
365 struct otx2_cpt_uc_info_t *uc_info;
366 int ucode_type, ucode_size;
369 uc_info = kzalloc(sizeof(*uc_info), GFP_KERNEL);
373 ret = reject_firmware(&uc_info->fw, filename, dev);
377 ucode_hdr = (struct otx2_cpt_ucode_hdr *)uc_info->fw->data;
378 ret = get_ucode_type(dev, ucode_hdr, &ucode_type);
382 ucode_size = ntohl(ucode_hdr->code_length) * 2;
384 dev_err(dev, "Ucode %s invalid size\n", filename);
389 set_ucode_filename(&uc_info->ucode, filename);
390 memcpy(uc_info->ucode.ver_str, ucode_hdr->ver_str,
391 OTX2_CPT_UCODE_VER_STR_SZ);
392 uc_info->ucode.ver_num = ucode_hdr->ver_num;
393 uc_info->ucode.type = ucode_type;
394 uc_info->ucode.size = ucode_size;
395 list_add_tail(&uc_info->list, &fw_info->ucodes);
400 release_firmware(uc_info->fw);
406 static void cpt_ucode_release_fw(struct fw_info_t *fw_info)
408 struct otx2_cpt_uc_info_t *curr, *temp;
413 list_for_each_entry_safe(curr, temp, &fw_info->ucodes, list) {
414 list_del(&curr->list);
415 release_firmware(curr->fw);
420 static struct otx2_cpt_uc_info_t *get_ucode(struct fw_info_t *fw_info,
423 struct otx2_cpt_uc_info_t *curr;
425 list_for_each_entry(curr, &fw_info->ucodes, list) {
426 if (!is_eng_type(curr->ucode.type, ucode_type))
434 static void print_uc_info(struct fw_info_t *fw_info)
436 struct otx2_cpt_uc_info_t *curr;
438 list_for_each_entry(curr, &fw_info->ucodes, list) {
439 pr_debug("Ucode filename %s\n", curr->ucode.filename);
440 pr_debug("Ucode version string %s\n", curr->ucode.ver_str);
441 pr_debug("Ucode version %d.%d.%d.%d\n",
442 curr->ucode.ver_num.nn, curr->ucode.ver_num.xx,
443 curr->ucode.ver_num.yy, curr->ucode.ver_num.zz);
444 pr_debug("Ucode type (%d) %s\n", curr->ucode.type,
445 get_ucode_type_str(curr->ucode.type));
446 pr_debug("Ucode size %d\n", curr->ucode.size);
447 pr_debug("Ucode ptr %p\n", curr->fw->data);
451 static int cpt_ucode_load_fw(struct pci_dev *pdev, struct fw_info_t *fw_info)
453 char filename[OTX2_CPT_NAME_LENGTH];
454 char eng_type[8] = {0};
457 INIT_LIST_HEAD(&fw_info->ucodes);
459 for (e = 1; e < OTX2_CPT_MAX_ENG_TYPES; e++) {
460 strcpy(eng_type, get_eng_type_str(e));
461 for (i = 0; i < strlen(eng_type); i++)
462 eng_type[i] = tolower(eng_type[i]);
464 snprintf(filename, sizeof(filename), "/*(DEBLOBBED)*/",
465 pdev->revision, eng_type);
466 /* Request firmware for each engine type */
467 ret = load_fw(&pdev->dev, fw_info, filename);
471 print_uc_info(fw_info);
475 cpt_ucode_release_fw(fw_info);
479 static struct otx2_cpt_engs_rsvd *find_engines_by_type(
480 struct otx2_cpt_eng_grp_info *eng_grp,
485 for (i = 0; i < OTX2_CPT_MAX_ETYPES_PER_GRP; i++) {
486 if (!eng_grp->engs[i].type)
489 if (eng_grp->engs[i].type == eng_type)
490 return &eng_grp->engs[i];
495 static int eng_grp_has_eng_type(struct otx2_cpt_eng_grp_info *eng_grp,
498 struct otx2_cpt_engs_rsvd *engs;
500 engs = find_engines_by_type(eng_grp, eng_type);
502 return (engs != NULL ? 1 : 0);
505 static int update_engines_avail_count(struct device *dev,
506 struct otx2_cpt_engs_available *avail,
507 struct otx2_cpt_engs_rsvd *engs, int val)
509 switch (engs->type) {
510 case OTX2_CPT_SE_TYPES:
511 avail->se_cnt += val;
514 case OTX2_CPT_IE_TYPES:
515 avail->ie_cnt += val;
518 case OTX2_CPT_AE_TYPES:
519 avail->ae_cnt += val;
523 dev_err(dev, "Invalid engine type %d\n", engs->type);
529 static int update_engines_offset(struct device *dev,
530 struct otx2_cpt_engs_available *avail,
531 struct otx2_cpt_engs_rsvd *engs)
533 switch (engs->type) {
534 case OTX2_CPT_SE_TYPES:
538 case OTX2_CPT_IE_TYPES:
539 engs->offset = avail->max_se_cnt;
542 case OTX2_CPT_AE_TYPES:
543 engs->offset = avail->max_se_cnt + avail->max_ie_cnt;
547 dev_err(dev, "Invalid engine type %d\n", engs->type);
553 static int release_engines(struct device *dev,
554 struct otx2_cpt_eng_grp_info *grp)
558 for (i = 0; i < OTX2_CPT_MAX_ETYPES_PER_GRP; i++) {
559 if (!grp->engs[i].type)
562 if (grp->engs[i].count > 0) {
563 ret = update_engines_avail_count(dev, &grp->g->avail,
570 grp->engs[i].type = 0;
571 grp->engs[i].count = 0;
572 grp->engs[i].offset = 0;
573 grp->engs[i].ucode = NULL;
574 bitmap_zero(grp->engs[i].bmap, grp->g->engs_num);
579 static int do_reserve_engines(struct device *dev,
580 struct otx2_cpt_eng_grp_info *grp,
581 struct otx2_cpt_engines *req_engs)
583 struct otx2_cpt_engs_rsvd *engs = NULL;
586 for (i = 0; i < OTX2_CPT_MAX_ETYPES_PER_GRP; i++) {
587 if (!grp->engs[i].type) {
588 engs = &grp->engs[i];
596 engs->type = req_engs->type;
597 engs->count = req_engs->count;
599 ret = update_engines_offset(dev, &grp->g->avail, engs);
603 if (engs->count > 0) {
604 ret = update_engines_avail_count(dev, &grp->g->avail, engs,
613 static int check_engines_availability(struct device *dev,
614 struct otx2_cpt_eng_grp_info *grp,
615 struct otx2_cpt_engines *req_eng)
619 switch (req_eng->type) {
620 case OTX2_CPT_SE_TYPES:
621 avail_cnt = grp->g->avail.se_cnt;
624 case OTX2_CPT_IE_TYPES:
625 avail_cnt = grp->g->avail.ie_cnt;
628 case OTX2_CPT_AE_TYPES:
629 avail_cnt = grp->g->avail.ae_cnt;
633 dev_err(dev, "Invalid engine type %d\n", req_eng->type);
637 if (avail_cnt < req_eng->count) {
639 "Error available %s engines %d < than requested %d\n",
640 get_eng_type_str(req_eng->type),
641 avail_cnt, req_eng->count);
647 static int reserve_engines(struct device *dev,
648 struct otx2_cpt_eng_grp_info *grp,
649 struct otx2_cpt_engines *req_engs, int ucodes_cnt)
653 /* Validate if a number of requested engines are available */
654 for (i = 0; i < ucodes_cnt; i++) {
655 ret = check_engines_availability(dev, grp, &req_engs[i]);
660 /* Reserve requested engines for this engine group */
661 for (i = 0; i < ucodes_cnt; i++) {
662 ret = do_reserve_engines(dev, grp, &req_engs[i]);
669 static void ucode_unload(struct device *dev, struct otx2_cpt_ucode *ucode)
672 dma_free_coherent(dev, OTX2_CPT_UCODE_SZ, ucode->va,
679 memset(&ucode->ver_str, 0, OTX2_CPT_UCODE_VER_STR_SZ);
680 memset(&ucode->ver_num, 0, sizeof(struct otx2_cpt_ucode_ver_num));
681 set_ucode_filename(ucode, "");
685 static int copy_ucode_to_dma_mem(struct device *dev,
686 struct otx2_cpt_ucode *ucode,
687 const u8 *ucode_data)
691 /* Allocate DMAable space */
692 ucode->va = dma_alloc_coherent(dev, OTX2_CPT_UCODE_SZ, &ucode->dma,
697 memcpy(ucode->va, ucode_data + sizeof(struct otx2_cpt_ucode_hdr),
700 /* Byte swap 64-bit */
701 for (i = 0; i < (ucode->size / 8); i++)
702 cpu_to_be64s(&((u64 *)ucode->va)[i]);
703 /* Ucode needs 16-bit swap */
704 for (i = 0; i < (ucode->size / 2); i++)
705 cpu_to_be16s(&((u16 *)ucode->va)[i]);
709 static int enable_eng_grp(struct otx2_cpt_eng_grp_info *eng_grp,
714 /* Point microcode to each core of the group */
715 ret = cpt_set_ucode_base(eng_grp, obj);
719 /* Attach the cores to the group and enable them */
720 ret = cpt_attach_and_enable_cores(eng_grp, obj);
725 static int disable_eng_grp(struct device *dev,
726 struct otx2_cpt_eng_grp_info *eng_grp,
731 /* Disable all engines used by this group */
732 ret = cpt_detach_and_disable_cores(eng_grp, obj);
736 /* Unload ucode used by this engine group */
737 ucode_unload(dev, &eng_grp->ucode[0]);
738 ucode_unload(dev, &eng_grp->ucode[1]);
740 for (i = 0; i < OTX2_CPT_MAX_ETYPES_PER_GRP; i++) {
741 if (!eng_grp->engs[i].type)
744 eng_grp->engs[i].ucode = &eng_grp->ucode[0];
747 /* Clear UCODE_BASE register for each engine used by this group */
748 ret = cpt_set_ucode_base(eng_grp, obj);
753 static void setup_eng_grp_mirroring(struct otx2_cpt_eng_grp_info *dst_grp,
754 struct otx2_cpt_eng_grp_info *src_grp)
756 /* Setup fields for engine group which is mirrored */
757 src_grp->mirror.is_ena = false;
758 src_grp->mirror.idx = 0;
759 src_grp->mirror.ref_count++;
761 /* Setup fields for mirroring engine group */
762 dst_grp->mirror.is_ena = true;
763 dst_grp->mirror.idx = src_grp->idx;
764 dst_grp->mirror.ref_count = 0;
767 static void remove_eng_grp_mirroring(struct otx2_cpt_eng_grp_info *dst_grp)
769 struct otx2_cpt_eng_grp_info *src_grp;
771 if (!dst_grp->mirror.is_ena)
774 src_grp = &dst_grp->g->grp[dst_grp->mirror.idx];
776 src_grp->mirror.ref_count--;
777 dst_grp->mirror.is_ena = false;
778 dst_grp->mirror.idx = 0;
779 dst_grp->mirror.ref_count = 0;
782 static void update_requested_engs(struct otx2_cpt_eng_grp_info *mirror_eng_grp,
783 struct otx2_cpt_engines *engs, int engs_cnt)
785 struct otx2_cpt_engs_rsvd *mirrored_engs;
788 for (i = 0; i < engs_cnt; i++) {
789 mirrored_engs = find_engines_by_type(mirror_eng_grp,
795 * If mirrored group has this type of engines attached then
796 * there are 3 scenarios possible:
797 * 1) mirrored_engs.count == engs[i].count then all engines
798 * from mirrored engine group will be shared with this engine
800 * 2) mirrored_engs.count > engs[i].count then only a subset of
801 * engines from mirrored engine group will be shared with this
803 * 3) mirrored_engs.count < engs[i].count then all engines
804 * from mirrored engine group will be shared with this group
805 * and additional engines will be reserved for exclusively use
806 * by this engine group
808 engs[i].count -= mirrored_engs->count;
812 static struct otx2_cpt_eng_grp_info *find_mirrored_eng_grp(
813 struct otx2_cpt_eng_grp_info *grp)
815 struct otx2_cpt_eng_grps *eng_grps = grp->g;
818 for (i = 0; i < OTX2_CPT_MAX_ENGINE_GROUPS; i++) {
819 if (!eng_grps->grp[i].is_enabled)
821 if (eng_grps->grp[i].ucode[0].type &&
822 eng_grps->grp[i].ucode[1].type)
826 if (!strncasecmp(eng_grps->grp[i].ucode[0].ver_str,
827 grp->ucode[0].ver_str,
828 OTX2_CPT_UCODE_VER_STR_SZ))
829 return &eng_grps->grp[i];
835 static struct otx2_cpt_eng_grp_info *find_unused_eng_grp(
836 struct otx2_cpt_eng_grps *eng_grps)
840 for (i = 0; i < OTX2_CPT_MAX_ENGINE_GROUPS; i++) {
841 if (!eng_grps->grp[i].is_enabled)
842 return &eng_grps->grp[i];
847 static int eng_grp_update_masks(struct device *dev,
848 struct otx2_cpt_eng_grp_info *eng_grp)
850 struct otx2_cpt_engs_rsvd *engs, *mirrored_engs;
851 struct otx2_cpt_bitmap tmp_bmap = { {0} };
852 int i, j, cnt, max_cnt;
855 for (i = 0; i < OTX2_CPT_MAX_ETYPES_PER_GRP; i++) {
856 engs = &eng_grp->engs[i];
859 if (engs->count <= 0)
862 switch (engs->type) {
863 case OTX2_CPT_SE_TYPES:
864 max_cnt = eng_grp->g->avail.max_se_cnt;
867 case OTX2_CPT_IE_TYPES:
868 max_cnt = eng_grp->g->avail.max_ie_cnt;
871 case OTX2_CPT_AE_TYPES:
872 max_cnt = eng_grp->g->avail.max_ae_cnt;
876 dev_err(dev, "Invalid engine type %d\n", engs->type);
881 WARN_ON(engs->offset + max_cnt > OTX2_CPT_MAX_ENGINES);
882 bitmap_zero(tmp_bmap.bits, eng_grp->g->engs_num);
883 for (j = engs->offset; j < engs->offset + max_cnt; j++) {
884 if (!eng_grp->g->eng_ref_cnt[j]) {
885 bitmap_set(tmp_bmap.bits, j, 1);
895 bitmap_copy(engs->bmap, tmp_bmap.bits, eng_grp->g->engs_num);
898 if (!eng_grp->mirror.is_ena)
901 for (i = 0; i < OTX2_CPT_MAX_ETYPES_PER_GRP; i++) {
902 engs = &eng_grp->engs[i];
906 mirrored_engs = find_engines_by_type(
907 &eng_grp->g->grp[eng_grp->mirror.idx],
909 WARN_ON(!mirrored_engs && engs->count <= 0);
913 bitmap_copy(tmp_bmap.bits, mirrored_engs->bmap,
914 eng_grp->g->engs_num);
915 if (engs->count < 0) {
916 bit = find_first_bit(mirrored_engs->bmap,
917 eng_grp->g->engs_num);
918 bitmap_clear(tmp_bmap.bits, bit, -engs->count);
920 bitmap_or(engs->bmap, engs->bmap, tmp_bmap.bits,
921 eng_grp->g->engs_num);
926 static int delete_engine_group(struct device *dev,
927 struct otx2_cpt_eng_grp_info *eng_grp)
931 if (!eng_grp->is_enabled)
934 if (eng_grp->mirror.ref_count)
937 /* Removing engine group mirroring if enabled */
938 remove_eng_grp_mirroring(eng_grp);
940 /* Disable engine group */
941 ret = disable_eng_grp(dev, eng_grp, eng_grp->g->obj);
945 /* Release all engines held by this engine group */
946 ret = release_engines(dev, eng_grp);
950 eng_grp->is_enabled = false;
955 static void update_ucode_ptrs(struct otx2_cpt_eng_grp_info *eng_grp)
957 struct otx2_cpt_ucode *ucode;
959 if (eng_grp->mirror.is_ena)
960 ucode = &eng_grp->g->grp[eng_grp->mirror.idx].ucode[0];
962 ucode = &eng_grp->ucode[0];
963 WARN_ON(!eng_grp->engs[0].type);
964 eng_grp->engs[0].ucode = ucode;
966 if (eng_grp->engs[1].type) {
967 if (is_2nd_ucode_used(eng_grp))
968 eng_grp->engs[1].ucode = &eng_grp->ucode[1];
970 eng_grp->engs[1].ucode = ucode;
974 static int create_engine_group(struct device *dev,
975 struct otx2_cpt_eng_grps *eng_grps,
976 struct otx2_cpt_engines *engs, int ucodes_cnt,
977 void *ucode_data[], int is_print)
979 struct otx2_cpt_eng_grp_info *mirrored_eng_grp;
980 struct otx2_cpt_eng_grp_info *eng_grp;
981 struct otx2_cpt_uc_info_t *uc_info;
984 /* Find engine group which is not used */
985 eng_grp = find_unused_eng_grp(eng_grps);
987 dev_err(dev, "Error all engine groups are being used\n");
991 for (i = 0; i < ucodes_cnt; i++) {
992 uc_info = (struct otx2_cpt_uc_info_t *) ucode_data[i];
993 eng_grp->ucode[i] = uc_info->ucode;
994 ret = copy_ucode_to_dma_mem(dev, &eng_grp->ucode[i],
1000 /* Check if this group mirrors another existing engine group */
1001 mirrored_eng_grp = find_mirrored_eng_grp(eng_grp);
1002 if (mirrored_eng_grp) {
1003 /* Setup mirroring */
1004 setup_eng_grp_mirroring(eng_grp, mirrored_eng_grp);
1007 * Update count of requested engines because some
1008 * of them might be shared with mirrored group
1010 update_requested_engs(mirrored_eng_grp, engs, ucodes_cnt);
1012 ret = reserve_engines(dev, eng_grp, engs, ucodes_cnt);
1016 /* Update ucode pointers used by engines */
1017 update_ucode_ptrs(eng_grp);
1019 /* Update engine masks used by this group */
1020 ret = eng_grp_update_masks(dev, eng_grp);
1024 /* Enable engine group */
1025 ret = enable_eng_grp(eng_grp, eng_grps->obj);
1030 * If this engine group mirrors another engine group
1031 * then we need to unload ucode as we will use ucode
1032 * from mirrored engine group
1034 if (eng_grp->mirror.is_ena)
1035 ucode_unload(dev, &eng_grp->ucode[0]);
1037 eng_grp->is_enabled = true;
1042 if (mirrored_eng_grp)
1044 "Engine_group%d: reuse microcode %s from group %d\n",
1045 eng_grp->idx, mirrored_eng_grp->ucode[0].ver_str,
1046 mirrored_eng_grp->idx);
1048 dev_info(dev, "Engine_group%d: microcode loaded %s\n",
1049 eng_grp->idx, eng_grp->ucode[0].ver_str);
1050 if (is_2nd_ucode_used(eng_grp))
1051 dev_info(dev, "Engine_group%d: microcode loaded %s\n",
1052 eng_grp->idx, eng_grp->ucode[1].ver_str);
1057 release_engines(dev, eng_grp);
1059 ucode_unload(dev, &eng_grp->ucode[0]);
1060 ucode_unload(dev, &eng_grp->ucode[1]);
1064 static void delete_engine_grps(struct pci_dev *pdev,
1065 struct otx2_cpt_eng_grps *eng_grps)
1069 /* First delete all mirroring engine groups */
1070 for (i = 0; i < OTX2_CPT_MAX_ENGINE_GROUPS; i++)
1071 if (eng_grps->grp[i].mirror.is_ena)
1072 delete_engine_group(&pdev->dev, &eng_grps->grp[i]);
1074 /* Delete remaining engine groups */
1075 for (i = 0; i < OTX2_CPT_MAX_ENGINE_GROUPS; i++)
1076 delete_engine_group(&pdev->dev, &eng_grps->grp[i]);
1079 int otx2_cpt_get_eng_grp(struct otx2_cpt_eng_grps *eng_grps, int eng_type)
1082 int eng_grp_num = OTX2_CPT_INVALID_CRYPTO_ENG_GRP;
1083 struct otx2_cpt_eng_grp_info *grp;
1086 for (i = 0; i < OTX2_CPT_MAX_ENGINE_GROUPS; i++) {
1087 grp = &eng_grps->grp[i];
1088 if (!grp->is_enabled)
1091 if (eng_type == OTX2_CPT_SE_TYPES) {
1092 if (eng_grp_has_eng_type(grp, eng_type) &&
1093 !eng_grp_has_eng_type(grp, OTX2_CPT_IE_TYPES)) {
1098 if (eng_grp_has_eng_type(grp, eng_type)) {
1107 int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev *cptpf,
1108 struct otx2_cpt_eng_grps *eng_grps)
1110 struct otx2_cpt_uc_info_t *uc_info[OTX2_CPT_MAX_ETYPES_PER_GRP] = { };
1111 struct otx2_cpt_engines engs[OTX2_CPT_MAX_ETYPES_PER_GRP] = { {0} };
1112 struct pci_dev *pdev = cptpf->pdev;
1113 struct fw_info_t fw_info;
1117 * We don't create engine groups if it was already
1118 * made (when user enabled VFs for the first time)
1120 if (eng_grps->is_grps_created)
1123 ret = cpt_ucode_load_fw(pdev, &fw_info);
1128 * Create engine group with SE engines for kernel
1129 * crypto functionality (symmetric crypto)
1131 uc_info[0] = get_ucode(&fw_info, OTX2_CPT_SE_TYPES);
1132 if (uc_info[0] == NULL) {
1133 dev_err(&pdev->dev, "Unable to find firmware for SE\n");
1137 engs[0].type = OTX2_CPT_SE_TYPES;
1138 engs[0].count = eng_grps->avail.max_se_cnt;
1140 ret = create_engine_group(&pdev->dev, eng_grps, engs, 1,
1141 (void **) uc_info, 1);
1146 * Create engine group with SE+IE engines for IPSec.
1147 * All SE engines will be shared with engine group 0.
1149 uc_info[0] = get_ucode(&fw_info, OTX2_CPT_SE_TYPES);
1150 uc_info[1] = get_ucode(&fw_info, OTX2_CPT_IE_TYPES);
1152 if (uc_info[1] == NULL) {
1153 dev_err(&pdev->dev, "Unable to find firmware for IE");
1155 goto delete_eng_grp;
1157 engs[0].type = OTX2_CPT_SE_TYPES;
1158 engs[0].count = eng_grps->avail.max_se_cnt;
1159 engs[1].type = OTX2_CPT_IE_TYPES;
1160 engs[1].count = eng_grps->avail.max_ie_cnt;
1162 ret = create_engine_group(&pdev->dev, eng_grps, engs, 2,
1163 (void **) uc_info, 1);
1165 goto delete_eng_grp;
1168 * Create engine group with AE engines for asymmetric
1169 * crypto functionality.
1171 uc_info[0] = get_ucode(&fw_info, OTX2_CPT_AE_TYPES);
1172 if (uc_info[0] == NULL) {
1173 dev_err(&pdev->dev, "Unable to find firmware for AE");
1175 goto delete_eng_grp;
1177 engs[0].type = OTX2_CPT_AE_TYPES;
1178 engs[0].count = eng_grps->avail.max_ae_cnt;
1180 ret = create_engine_group(&pdev->dev, eng_grps, engs, 1,
1181 (void **) uc_info, 1);
1183 goto delete_eng_grp;
1185 eng_grps->is_grps_created = true;
1187 cpt_ucode_release_fw(&fw_info);
1189 if (is_dev_otx2(pdev))
1192 * Configure engine group mask to allow context prefetching
1195 otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTL,
1196 OTX2_CPT_ALL_ENG_GRPS_MASK << 3 | BIT_ULL(16),
1199 * Set interval to periodically flush dirty data for the next
1200 * CTX cache entry. Set the interval count to maximum supported
1203 otx2_cpt_write_af_reg(&cptpf->afpf_mbox, pdev, CPT_AF_CTX_FLUSH_TIMER,
1204 CTX_FLUSH_TIMER_CNT, BLKADDR_CPT0);
1208 delete_engine_grps(pdev, eng_grps);
1210 cpt_ucode_release_fw(&fw_info);
1214 static int cptx_disable_all_cores(struct otx2_cptpf_dev *cptpf, int total_cores,
1217 int timeout = 10, ret;
1221 /* Disengage the cores from groups */
1222 for (i = 0; i < total_cores; i++) {
1223 ret = otx2_cpt_add_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
1224 CPT_AF_EXEX_CTL2(i), 0x0,
1229 cptpf->eng_grps.eng_ref_cnt[i] = 0;
1231 ret = otx2_cpt_send_af_reg_requests(&cptpf->afpf_mbox, cptpf->pdev);
1235 /* Wait for cores to become idle */
1238 usleep_range(10000, 20000);
1242 for (i = 0; i < total_cores; i++) {
1243 ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox,
1245 CPT_AF_EXEX_STS(i), ®,
1257 /* Disable the cores */
1258 for (i = 0; i < total_cores; i++) {
1259 ret = otx2_cpt_add_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev,
1260 CPT_AF_EXEX_CTL(i), 0x0,
1265 return otx2_cpt_send_af_reg_requests(&cptpf->afpf_mbox, cptpf->pdev);
1268 int otx2_cpt_disable_all_cores(struct otx2_cptpf_dev *cptpf)
1270 int total_cores, ret;
1272 total_cores = cptpf->eng_grps.avail.max_se_cnt +
1273 cptpf->eng_grps.avail.max_ie_cnt +
1274 cptpf->eng_grps.avail.max_ae_cnt;
1276 if (cptpf->has_cpt1) {
1277 ret = cptx_disable_all_cores(cptpf, total_cores, BLKADDR_CPT1);
1281 return cptx_disable_all_cores(cptpf, total_cores, BLKADDR_CPT0);
1284 void otx2_cpt_cleanup_eng_grps(struct pci_dev *pdev,
1285 struct otx2_cpt_eng_grps *eng_grps)
1287 struct otx2_cpt_eng_grp_info *grp;
1290 delete_engine_grps(pdev, eng_grps);
1291 /* Release memory */
1292 for (i = 0; i < OTX2_CPT_MAX_ENGINE_GROUPS; i++) {
1293 grp = &eng_grps->grp[i];
1294 for (j = 0; j < OTX2_CPT_MAX_ETYPES_PER_GRP; j++) {
1295 kfree(grp->engs[j].bmap);
1296 grp->engs[j].bmap = NULL;
1301 int otx2_cpt_init_eng_grps(struct pci_dev *pdev,
1302 struct otx2_cpt_eng_grps *eng_grps)
1304 struct otx2_cpt_eng_grp_info *grp;
1307 eng_grps->obj = pci_get_drvdata(pdev);
1308 eng_grps->avail.se_cnt = eng_grps->avail.max_se_cnt;
1309 eng_grps->avail.ie_cnt = eng_grps->avail.max_ie_cnt;
1310 eng_grps->avail.ae_cnt = eng_grps->avail.max_ae_cnt;
1312 eng_grps->engs_num = eng_grps->avail.max_se_cnt +
1313 eng_grps->avail.max_ie_cnt +
1314 eng_grps->avail.max_ae_cnt;
1315 if (eng_grps->engs_num > OTX2_CPT_MAX_ENGINES) {
1317 "Number of engines %d > than max supported %d\n",
1318 eng_grps->engs_num, OTX2_CPT_MAX_ENGINES);
1320 goto cleanup_eng_grps;
1323 for (i = 0; i < OTX2_CPT_MAX_ENGINE_GROUPS; i++) {
1324 grp = &eng_grps->grp[i];
1328 for (j = 0; j < OTX2_CPT_MAX_ETYPES_PER_GRP; j++) {
1330 kcalloc(BITS_TO_LONGS(eng_grps->engs_num),
1331 sizeof(long), GFP_KERNEL);
1332 if (!grp->engs[j].bmap) {
1334 goto cleanup_eng_grps;
1341 otx2_cpt_cleanup_eng_grps(pdev, eng_grps);
1345 static int create_eng_caps_discovery_grps(struct pci_dev *pdev,
1346 struct otx2_cpt_eng_grps *eng_grps)
1348 struct otx2_cpt_uc_info_t *uc_info[OTX2_CPT_MAX_ETYPES_PER_GRP] = { };
1349 struct otx2_cpt_engines engs[OTX2_CPT_MAX_ETYPES_PER_GRP] = { {0} };
1350 struct fw_info_t fw_info;
1353 ret = cpt_ucode_load_fw(pdev, &fw_info);
1357 uc_info[0] = get_ucode(&fw_info, OTX2_CPT_SE_TYPES);
1358 if (uc_info[0] == NULL) {
1359 dev_err(&pdev->dev, "Unable to find firmware for AE\n");
1363 engs[0].type = OTX2_CPT_AE_TYPES;
1366 ret = create_engine_group(&pdev->dev, eng_grps, engs, 1,
1367 (void **) uc_info, 0);
1371 uc_info[0] = get_ucode(&fw_info, OTX2_CPT_SE_TYPES);
1372 if (uc_info[0] == NULL) {
1373 dev_err(&pdev->dev, "Unable to find firmware for SE\n");
1375 goto delete_eng_grp;
1377 engs[0].type = OTX2_CPT_SE_TYPES;
1380 ret = create_engine_group(&pdev->dev, eng_grps, engs, 1,
1381 (void **) uc_info, 0);
1383 goto delete_eng_grp;
1385 uc_info[0] = get_ucode(&fw_info, OTX2_CPT_IE_TYPES);
1386 if (uc_info[0] == NULL) {
1387 dev_err(&pdev->dev, "Unable to find firmware for IE\n");
1389 goto delete_eng_grp;
1391 engs[0].type = OTX2_CPT_IE_TYPES;
1394 ret = create_engine_group(&pdev->dev, eng_grps, engs, 1,
1395 (void **) uc_info, 0);
1397 goto delete_eng_grp;
1399 cpt_ucode_release_fw(&fw_info);
1403 delete_engine_grps(pdev, eng_grps);
1405 cpt_ucode_release_fw(&fw_info);
1410 * Get CPT HW capabilities using LOAD_FVC operation.
1412 int otx2_cpt_discover_eng_capabilities(struct otx2_cptpf_dev *cptpf)
1414 struct otx2_cptlfs_info *lfs = &cptpf->lfs;
1415 struct otx2_cpt_iq_command iq_cmd;
1416 union otx2_cpt_opcode opcode;
1417 union otx2_cpt_res_s *result;
1418 union otx2_cpt_inst_s inst;
1419 dma_addr_t rptr_baddr;
1420 struct pci_dev *pdev;
1421 u32 len, compl_rlen;
1426 * We don't get capabilities if it was already done
1427 * (when user enabled VFs for the first time)
1429 if (cptpf->is_eng_caps_discovered)
1434 * Create engine groups for each type to submit LOAD_FVC op and
1435 * get engine's capabilities.
1437 ret = create_eng_caps_discovery_grps(pdev, &cptpf->eng_grps);
1442 lfs->reg_base = cptpf->reg_base;
1443 lfs->mbox = &cptpf->afpf_mbox;
1444 lfs->blkaddr = BLKADDR_CPT0;
1445 ret = otx2_cptlf_init(&cptpf->lfs, OTX2_CPT_ALL_ENG_GRPS_MASK,
1446 OTX2_CPT_QUEUE_HI_PRIO, 1);
1450 compl_rlen = ALIGN(sizeof(union otx2_cpt_res_s), OTX2_CPT_DMA_MINALIGN);
1451 len = compl_rlen + LOADFVC_RLEN;
1453 result = kzalloc(len, GFP_KERNEL);
1458 rptr_baddr = dma_map_single(&pdev->dev, (void *)result, len,
1460 if (dma_mapping_error(&pdev->dev, rptr_baddr)) {
1461 dev_err(&pdev->dev, "DMA mapping failed\n");
1465 rptr = (u8 *)result + compl_rlen;
1467 /* Fill in the command */
1468 opcode.s.major = LOADFVC_MAJOR_OP;
1469 opcode.s.minor = LOADFVC_MINOR_OP;
1472 iq_cmd.cmd.s.opcode = cpu_to_be16(opcode.flags);
1474 /* 64-bit swap for microcode data reads, not needed for addresses */
1475 cpu_to_be64s(&iq_cmd.cmd.u);
1477 iq_cmd.rptr = rptr_baddr + compl_rlen;
1480 for (etype = 1; etype < OTX2_CPT_MAX_ENG_TYPES; etype++) {
1481 result->s.compcode = OTX2_CPT_COMPLETION_CODE_INIT;
1482 iq_cmd.cptr.s.grp = otx2_cpt_get_eng_grp(&cptpf->eng_grps,
1484 otx2_cpt_fill_inst(&inst, &iq_cmd, rptr_baddr);
1485 lfs->ops->send_cmd(&inst, 1, &cptpf->lfs.lf[0]);
1487 while (lfs->ops->cpt_get_compcode(result) ==
1488 OTX2_CPT_COMPLETION_CODE_INIT)
1491 cptpf->eng_caps[etype].u = be64_to_cpup(rptr);
1493 dma_unmap_single(&pdev->dev, rptr_baddr, len, DMA_BIDIRECTIONAL);
1494 cptpf->is_eng_caps_discovered = true;
1499 otx2_cptlf_shutdown(&cptpf->lfs);
1501 delete_engine_grps(pdev, &cptpf->eng_grps);