1 /* SPDX-License-Identifier: GPL-2.0-only
2 * Copyright (C) 2020 Marvell.
8 #include "otx2_cpt_common.h"
9 #include "otx2_cptpf_ucode.h"
10 #include "otx2_cptlf.h"
12 struct otx2_cptpf_dev;
13 struct otx2_cptvf_info {
14 struct otx2_cptpf_dev *cptpf; /* PF pointer this VF belongs to */
15 struct work_struct vfpf_mbox_work;
16 struct pci_dev *vf_dev;
21 struct cptpf_flr_work {
22 struct work_struct work;
23 struct otx2_cptpf_dev *pf;
26 struct otx2_cptpf_dev {
27 void __iomem *reg_base; /* CPT PF registers start address */
28 void __iomem *afpf_mbox_base; /* PF-AF mbox start address */
29 void __iomem *vfpf_mbox_base; /* VF-PF mbox start address */
30 struct pci_dev *pdev; /* PCI device handle */
31 struct otx2_cptvf_info vf[OTX2_CPT_MAX_VFS_NUM];
32 struct otx2_cpt_eng_grps eng_grps;/* Engine groups information */
33 struct otx2_cptlfs_info lfs; /* CPT LFs attached to this PF */
34 /* HW capabilities for each engine type */
35 union otx2_cpt_eng_caps eng_caps[OTX2_CPT_MAX_ENG_TYPES];
36 bool is_eng_caps_discovered;
39 struct otx2_mbox afpf_mbox;
40 struct work_struct afpf_mbox_work;
41 struct workqueue_struct *afpf_mbox_wq;
44 struct otx2_mbox vfpf_mbox;
45 struct workqueue_struct *vfpf_mbox_wq;
47 struct workqueue_struct *flr_wq;
48 struct cptpf_flr_work *flr_work;
50 unsigned long cap_flag;
51 u8 pf_id; /* RVU PF number */
52 u8 max_vfs; /* Maximum number of VFs supported by CPT */
53 u8 enabled_vfs; /* Number of enabled VFs */
54 u8 kvf_limits; /* Kernel crypto limits */
58 irqreturn_t otx2_cptpf_afpf_mbox_intr(int irq, void *arg);
59 void otx2_cptpf_afpf_mbox_handler(struct work_struct *work);
60 irqreturn_t otx2_cptpf_vfpf_mbox_intr(int irq, void *arg);
61 void otx2_cptpf_vfpf_mbox_handler(struct work_struct *work);
63 #endif /* __OTX2_CPTPF_H */