1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2020 Marvell. */
4 #include "otx2_cpt_common.h"
5 #include "otx2_cptlf.h"
7 int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev)
11 otx2_mbox_msg_send(mbox, 0);
12 ret = otx2_mbox_wait_for_rsp(mbox, 0);
14 dev_err(&pdev->dev, "RVU MBOX timeout.\n");
17 dev_err(&pdev->dev, "RVU MBOX error: %d.\n", ret);
23 int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev)
25 struct mbox_msghdr *req;
27 req = otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
28 sizeof(struct ready_msg_rsp));
30 dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
33 req->id = MBOX_MSG_READY;
34 req->sig = OTX2_MBOX_REQ_SIG;
37 return otx2_cpt_send_mbox_msg(mbox, pdev);
40 int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox, struct pci_dev *pdev)
42 return otx2_cpt_send_mbox_msg(mbox, pdev);
45 int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
46 u64 reg, u64 *val, int blkaddr)
48 struct cpt_rd_wr_reg_msg *reg_msg;
50 reg_msg = (struct cpt_rd_wr_reg_msg *)
51 otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*reg_msg),
53 if (reg_msg == NULL) {
54 dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
58 reg_msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;
59 reg_msg->hdr.sig = OTX2_MBOX_REQ_SIG;
60 reg_msg->hdr.pcifunc = 0;
62 reg_msg->is_write = 0;
63 reg_msg->reg_offset = reg;
64 reg_msg->ret_val = val;
65 reg_msg->blkaddr = blkaddr;
70 int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
71 u64 reg, u64 val, int blkaddr)
73 struct cpt_rd_wr_reg_msg *reg_msg;
75 reg_msg = (struct cpt_rd_wr_reg_msg *)
76 otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*reg_msg),
78 if (reg_msg == NULL) {
79 dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
83 reg_msg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;
84 reg_msg->hdr.sig = OTX2_MBOX_REQ_SIG;
85 reg_msg->hdr.pcifunc = 0;
87 reg_msg->is_write = 1;
88 reg_msg->reg_offset = reg;
90 reg_msg->blkaddr = blkaddr;
95 int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
96 u64 reg, u64 *val, int blkaddr)
100 ret = otx2_cpt_add_read_af_reg(mbox, pdev, reg, val, blkaddr);
104 return otx2_cpt_send_mbox_msg(mbox, pdev);
107 int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
108 u64 reg, u64 val, int blkaddr)
112 ret = otx2_cpt_add_write_af_reg(mbox, pdev, reg, val, blkaddr);
116 return otx2_cpt_send_mbox_msg(mbox, pdev);
119 int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs)
121 struct otx2_mbox *mbox = lfs->mbox;
122 struct rsrc_attach *req;
125 req = (struct rsrc_attach *)
126 otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
127 sizeof(struct msg_rsp));
129 dev_err(&lfs->pdev->dev, "RVU MBOX failed to get message.\n");
133 req->hdr.id = MBOX_MSG_ATTACH_RESOURCES;
134 req->hdr.sig = OTX2_MBOX_REQ_SIG;
135 req->hdr.pcifunc = 0;
136 req->cptlfs = lfs->lfs_num;
137 ret = otx2_cpt_send_mbox_msg(mbox, lfs->pdev);
141 if (!lfs->are_lfs_attached)
147 int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs)
149 struct otx2_mbox *mbox = lfs->mbox;
150 struct rsrc_detach *req;
153 req = (struct rsrc_detach *)
154 otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
155 sizeof(struct msg_rsp));
157 dev_err(&lfs->pdev->dev, "RVU MBOX failed to get message.\n");
161 req->hdr.id = MBOX_MSG_DETACH_RESOURCES;
162 req->hdr.sig = OTX2_MBOX_REQ_SIG;
163 req->hdr.pcifunc = 0;
164 ret = otx2_cpt_send_mbox_msg(mbox, lfs->pdev);
168 if (lfs->are_lfs_attached)
174 int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs)
176 struct otx2_mbox *mbox = lfs->mbox;
177 struct pci_dev *pdev = lfs->pdev;
178 struct mbox_msghdr *req;
181 req = otx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*req),
182 sizeof(struct msix_offset_rsp));
184 dev_err(&pdev->dev, "RVU MBOX failed to get message.\n");
188 req->id = MBOX_MSG_MSIX_OFFSET;
189 req->sig = OTX2_MBOX_REQ_SIG;
191 ret = otx2_cpt_send_mbox_msg(mbox, pdev);
195 for (i = 0; i < lfs->lfs_num; i++) {
196 if (lfs->lf[i].msix_offset == MSIX_VECTOR_INVALID) {
198 "Invalid msix offset %d for LF %d\n",
199 lfs->lf[i].msix_offset, i);