1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Keem Bay OCS HCU Crypto Driver.
5 * Copyright (C) 2018-2020 Intel Corporation
8 #include <linux/completion.h>
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
15 #include <crypto/engine.h>
16 #include <crypto/scatterwalk.h>
17 #include <crypto/sha2.h>
18 #include <crypto/sm3.h>
19 #include <crypto/hmac.h>
20 #include <crypto/internal/hash.h>
24 #define DRV_NAME "keembay-ocs-hcu"
26 /* Flag marking a final request. */
27 #define REQ_FINAL BIT(0)
28 /* Flag marking a HMAC request. */
29 #define REQ_FLAGS_HMAC BIT(1)
30 /* Flag set when HW HMAC is being used. */
31 #define REQ_FLAGS_HMAC_HW BIT(2)
32 /* Flag set when SW HMAC is being used. */
33 #define REQ_FLAGS_HMAC_SW BIT(3)
36 * struct ocs_hcu_ctx: OCS HCU Transform context.
37 * @engine_ctx: Crypto Engine context.
38 * @hcu_dev: The OCS HCU device used by the transformation.
39 * @key: The key (used only for HMAC transformations).
40 * @key_len: The length of the key.
41 * @is_sm3_tfm: Whether or not this is an SM3 transformation.
42 * @is_hmac_tfm: Whether or not this is a HMAC transformation.
45 struct crypto_engine_ctx engine_ctx;
46 struct ocs_hcu_dev *hcu_dev;
47 u8 key[SHA512_BLOCK_SIZE];
54 * struct ocs_hcu_rctx - Context for the request.
55 * @hcu_dev: OCS HCU device to be used to service the request.
56 * @flags: Flags tracking request status.
57 * @algo: Algorithm to use for the request.
58 * @blk_sz: Block size of the transformation / request.
59 * @dig_sz: Digest size of the transformation / request.
60 * @dma_list: OCS DMA linked list.
61 * @hash_ctx: OCS HCU hashing context.
62 * @buffer: Buffer to store: partial block of data and SW HMAC
63 * artifacts (ipad, opad, etc.).
64 * @buf_cnt: Number of bytes currently stored in the buffer.
65 * @buf_dma_addr: The DMA address of @buffer (when mapped).
66 * @buf_dma_count: The number of bytes in @buffer currently DMA-mapped.
67 * @sg: Head of the scatterlist entries containing data.
68 * @sg_data_total: Total data in the SG list at any time.
69 * @sg_data_offset: Offset into the data of the current individual SG node.
70 * @sg_dma_nents: Number of sg entries mapped in dma_list.
73 struct ocs_hcu_dev *hcu_dev;
75 enum ocs_hcu_algo algo;
78 struct ocs_hcu_dma_list *dma_list;
79 struct ocs_hcu_hash_ctx hash_ctx;
81 * Buffer is double the block size because we need space for SW HMAC
83 * - ipad (1 block) + a possible partial block of data.
84 * - opad (1 block) + digest of H(k ^ ipad || m)
86 u8 buffer[2 * SHA512_BLOCK_SIZE];
88 dma_addr_t buf_dma_addr;
90 struct scatterlist *sg;
91 unsigned int sg_data_total;
92 unsigned int sg_data_offset;
93 unsigned int sg_dma_nents;
97 * struct ocs_hcu_drv - Driver data
98 * @dev_list: The list of HCU devices.
99 * @lock: The lock protecting dev_list.
102 struct list_head dev_list;
103 spinlock_t lock; /* Protects dev_list. */
106 static struct ocs_hcu_drv ocs_hcu = {
107 .dev_list = LIST_HEAD_INIT(ocs_hcu.dev_list),
108 .lock = __SPIN_LOCK_UNLOCKED(ocs_hcu.lock),
112 * Return the total amount of data in the request; that is: the data in the
113 * request buffer + the data in the sg list.
115 static inline unsigned int kmb_get_total_data(struct ocs_hcu_rctx *rctx)
117 return rctx->sg_data_total + rctx->buf_cnt;
120 /* Move remaining content of scatter-gather list to context buffer. */
121 static int flush_sg_to_ocs_buffer(struct ocs_hcu_rctx *rctx)
125 if (rctx->sg_data_total > (sizeof(rctx->buffer) - rctx->buf_cnt)) {
126 WARN(1, "%s: sg data does not fit in buffer\n", __func__);
130 while (rctx->sg_data_total) {
132 WARN(1, "%s: unexpected NULL sg\n", __func__);
136 * If current sg has been fully processed, skip to the next
139 if (rctx->sg_data_offset == rctx->sg->length) {
140 rctx->sg = sg_next(rctx->sg);
141 rctx->sg_data_offset = 0;
145 * Determine the maximum data available to copy from the node.
146 * Minimum of the length left in the sg node, or the total data
149 count = min(rctx->sg->length - rctx->sg_data_offset,
150 rctx->sg_data_total);
151 /* Copy from scatter-list entry to context buffer. */
152 scatterwalk_map_and_copy(&rctx->buffer[rctx->buf_cnt],
153 rctx->sg, rctx->sg_data_offset,
156 rctx->sg_data_offset += count;
157 rctx->sg_data_total -= count;
158 rctx->buf_cnt += count;
164 static struct ocs_hcu_dev *kmb_ocs_hcu_find_dev(struct ahash_request *req)
166 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
167 struct ocs_hcu_ctx *tctx = crypto_ahash_ctx(tfm);
169 /* If the HCU device for the request was previously set, return it. */
171 return tctx->hcu_dev;
174 * Otherwise, get the first HCU device available (there should be one
175 * and only one device).
177 spin_lock_bh(&ocs_hcu.lock);
178 tctx->hcu_dev = list_first_entry_or_null(&ocs_hcu.dev_list,
181 spin_unlock_bh(&ocs_hcu.lock);
183 return tctx->hcu_dev;
186 /* Free OCS DMA linked list and DMA-able context buffer. */
187 static void kmb_ocs_hcu_dma_cleanup(struct ahash_request *req,
188 struct ocs_hcu_rctx *rctx)
190 struct ocs_hcu_dev *hcu_dev = rctx->hcu_dev;
191 struct device *dev = hcu_dev->dev;
193 /* Unmap rctx->buffer (if mapped). */
194 if (rctx->buf_dma_count) {
195 dma_unmap_single(dev, rctx->buf_dma_addr, rctx->buf_dma_count,
197 rctx->buf_dma_count = 0;
200 /* Unmap req->src (if mapped). */
201 if (rctx->sg_dma_nents) {
202 dma_unmap_sg(dev, req->src, rctx->sg_dma_nents, DMA_TO_DEVICE);
203 rctx->sg_dma_nents = 0;
206 /* Free dma_list (if allocated). */
207 if (rctx->dma_list) {
208 ocs_hcu_dma_list_free(hcu_dev, rctx->dma_list);
209 rctx->dma_list = NULL;
214 * Prepare for DMA operation:
215 * - DMA-map request context buffer (if needed)
216 * - DMA-map SG list (only the entries to be processed, see note below)
217 * - Allocate OCS HCU DMA linked list (number of elements = SG entries to
218 * process + context buffer (if not empty)).
219 * - Add DMA-mapped request context buffer to OCS HCU DMA list.
220 * - Add SG entries to DMA list.
222 * Note: if this is a final request, we process all the data in the SG list,
223 * otherwise we can only process up to the maximum amount of block-aligned data
224 * (the remainder will be put into the context buffer and processed in the next
227 static int kmb_ocs_dma_prepare(struct ahash_request *req)
229 struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
230 struct device *dev = rctx->hcu_dev->dev;
231 unsigned int remainder = 0;
238 /* This function should be called only when there is data to process. */
239 total = kmb_get_total_data(rctx);
244 * If this is not a final DMA (terminated DMA), the data passed to the
245 * HCU must be aligned to the block size; compute the remainder data to
246 * be processed in the next request.
248 if (!(rctx->flags & REQ_FINAL))
249 remainder = total % rctx->blk_sz;
251 /* Determine the number of scatter gather list entries to process. */
252 nents = sg_nents_for_len(req->src, rctx->sg_data_total - remainder);
254 /* If there are entries to process, map them. */
256 rctx->sg_dma_nents = dma_map_sg(dev, req->src, nents,
258 if (!rctx->sg_dma_nents) {
259 dev_err(dev, "Failed to MAP SG\n");
264 * The value returned by dma_map_sg() can be < nents; so update
267 nents = rctx->sg_dma_nents;
271 * If context buffer is not empty, map it and add extra DMA entry for
275 rctx->buf_dma_addr = dma_map_single(dev, rctx->buffer,
278 if (dma_mapping_error(dev, rctx->buf_dma_addr)) {
279 dev_err(dev, "Failed to map request context buffer\n");
283 rctx->buf_dma_count = rctx->buf_cnt;
284 /* Increase number of dma entries. */
288 /* Allocate OCS HCU DMA list. */
289 rctx->dma_list = ocs_hcu_dma_list_alloc(rctx->hcu_dev, nents);
290 if (!rctx->dma_list) {
295 /* Add request context buffer (if previously DMA-mapped) */
296 if (rctx->buf_dma_count) {
297 rc = ocs_hcu_dma_list_add_tail(rctx->hcu_dev, rctx->dma_list,
299 rctx->buf_dma_count);
304 /* Add the SG nodes to be processed to the DMA linked list. */
305 for_each_sg(req->src, rctx->sg, rctx->sg_dma_nents, i) {
307 * The number of bytes to add to the list entry is the minimum
309 * - The DMA length of the SG entry.
310 * - The data left to be processed.
312 count = min(rctx->sg_data_total - remainder,
313 sg_dma_len(rctx->sg) - rctx->sg_data_offset);
315 * Do not create a zero length DMA descriptor. Check in case of
316 * zero length SG node.
320 /* Add sg to HCU DMA list. */
321 rc = ocs_hcu_dma_list_add_tail(rctx->hcu_dev,
323 rctx->sg->dma_address,
328 /* Update amount of data remaining in SG list. */
329 rctx->sg_data_total -= count;
332 * If remaining data is equal to remainder (note: 'less than'
333 * case should never happen in practice), we are done: update
334 * offset and exit the loop.
336 if (rctx->sg_data_total <= remainder) {
337 WARN_ON(rctx->sg_data_total < remainder);
338 rctx->sg_data_offset += count;
343 * If we get here is because we need to process the next sg in
344 * the list; set offset within the sg to 0.
346 rctx->sg_data_offset = 0;
351 dev_err(dev, "Failed to prepare DMA.\n");
352 kmb_ocs_hcu_dma_cleanup(req, rctx);
357 static void kmb_ocs_hcu_secure_cleanup(struct ahash_request *req)
359 struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
361 /* Clear buffer of any data. */
362 memzero_explicit(rctx->buffer, sizeof(rctx->buffer));
365 static int kmb_ocs_hcu_handle_queue(struct ahash_request *req)
367 struct ocs_hcu_dev *hcu_dev = kmb_ocs_hcu_find_dev(req);
372 return crypto_transfer_hash_request_to_engine(hcu_dev->engine, req);
375 static int prepare_ipad(struct ahash_request *req)
377 struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
378 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
379 struct ocs_hcu_ctx *ctx = crypto_ahash_ctx(tfm);
382 WARN(rctx->buf_cnt, "%s: Context buffer is not empty\n", __func__);
383 WARN(!(rctx->flags & REQ_FLAGS_HMAC_SW),
384 "%s: HMAC_SW flag is not set\n", __func__);
386 * Key length must be equal to block size. If key is shorter,
387 * we pad it with zero (note: key cannot be longer, since
388 * longer keys are hashed by kmb_ocs_hcu_setkey()).
390 if (ctx->key_len > rctx->blk_sz) {
391 WARN(1, "%s: Invalid key length in tfm context\n", __func__);
394 memzero_explicit(&ctx->key[ctx->key_len],
395 rctx->blk_sz - ctx->key_len);
396 ctx->key_len = rctx->blk_sz;
398 * Prepare IPAD for HMAC. Only done for first block.
399 * HMAC(k,m) = H(k ^ opad || H(k ^ ipad || m))
400 * k ^ ipad will be first hashed block.
401 * k ^ opad will be calculated in the final request.
402 * Only needed if not using HW HMAC.
404 for (i = 0; i < rctx->blk_sz; i++)
405 rctx->buffer[i] = ctx->key[i] ^ HMAC_IPAD_VALUE;
406 rctx->buf_cnt = rctx->blk_sz;
411 static int kmb_ocs_hcu_do_one_request(struct crypto_engine *engine, void *areq)
413 struct ahash_request *req = container_of(areq, struct ahash_request,
415 struct ocs_hcu_dev *hcu_dev = kmb_ocs_hcu_find_dev(req);
416 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
417 struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
418 struct ocs_hcu_ctx *tctx = crypto_ahash_ctx(tfm);
428 * If hardware HMAC flag is set, perform HMAC in hardware.
430 * NOTE: this flag implies REQ_FINAL && kmb_get_total_data(rctx)
432 if (rctx->flags & REQ_FLAGS_HMAC_HW) {
433 /* Map input data into the HCU DMA linked list. */
434 rc = kmb_ocs_dma_prepare(req);
438 rc = ocs_hcu_hmac(hcu_dev, rctx->algo, tctx->key, tctx->key_len,
439 rctx->dma_list, req->result, rctx->dig_sz);
441 /* Unmap data and free DMA list regardless of return code. */
442 kmb_ocs_hcu_dma_cleanup(req, rctx);
444 /* Process previous return code. */
451 /* Handle update request case. */
452 if (!(rctx->flags & REQ_FINAL)) {
453 /* Update should always have input data. */
454 if (!kmb_get_total_data(rctx))
457 /* Map input data into the HCU DMA linked list. */
458 rc = kmb_ocs_dma_prepare(req);
462 /* Do hashing step. */
463 rc = ocs_hcu_hash_update(hcu_dev, &rctx->hash_ctx,
466 /* Unmap data and free DMA list regardless of return code. */
467 kmb_ocs_hcu_dma_cleanup(req, rctx);
469 /* Process previous return code. */
474 * Reset request buffer count (data in the buffer was just
479 * Move remaining sg data into the request buffer, so that it
480 * will be processed during the next request.
482 * NOTE: we have remaining data if kmb_get_total_data() was not
483 * a multiple of block size.
485 rc = flush_sg_to_ocs_buffer(rctx);
492 /* If we get here, this is a final request. */
494 /* If there is data to process, use finup. */
495 if (kmb_get_total_data(rctx)) {
496 /* Map input data into the HCU DMA linked list. */
497 rc = kmb_ocs_dma_prepare(req);
501 /* Do hashing step. */
502 rc = ocs_hcu_hash_finup(hcu_dev, &rctx->hash_ctx,
504 req->result, rctx->dig_sz);
505 /* Free DMA list regardless of return code. */
506 kmb_ocs_hcu_dma_cleanup(req, rctx);
508 /* Process previous return code. */
512 } else { /* Otherwise (if we have no data), use final. */
513 rc = ocs_hcu_hash_final(hcu_dev, &rctx->hash_ctx, req->result,
520 * If we are finalizing a SW HMAC request, we just computed the result
521 * of: H(k ^ ipad || m).
523 * We now need to complete the HMAC calculation with the OPAD step,
524 * that is, we need to compute H(k ^ opad || digest), where digest is
525 * the digest we just obtained, i.e., H(k ^ ipad || m).
527 if (rctx->flags & REQ_FLAGS_HMAC_SW) {
529 * Compute k ^ opad and store it in the request buffer (which
530 * is not used anymore at this point).
531 * Note: key has been padded / hashed already (so keylen ==
534 WARN_ON(tctx->key_len != rctx->blk_sz);
535 for (i = 0; i < rctx->blk_sz; i++)
536 rctx->buffer[i] = tctx->key[i] ^ HMAC_OPAD_VALUE;
537 /* Now append the digest to the rest of the buffer. */
538 for (i = 0; (i < rctx->dig_sz); i++)
539 rctx->buffer[rctx->blk_sz + i] = req->result[i];
541 /* Now hash the buffer to obtain the final HMAC. */
542 rc = ocs_hcu_digest(hcu_dev, rctx->algo, rctx->buffer,
543 rctx->blk_sz + rctx->dig_sz, req->result,
549 /* Perform secure clean-up. */
550 kmb_ocs_hcu_secure_cleanup(req);
552 crypto_finalize_hash_request(hcu_dev->engine, req, 0);
557 kmb_ocs_hcu_secure_cleanup(req);
561 static int kmb_ocs_hcu_init(struct ahash_request *req)
563 struct ocs_hcu_dev *hcu_dev = kmb_ocs_hcu_find_dev(req);
564 struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
565 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
566 struct ocs_hcu_ctx *ctx = crypto_ahash_ctx(tfm);
571 /* Initialize entire request context to zero. */
572 memset(rctx, 0, sizeof(*rctx));
574 rctx->hcu_dev = hcu_dev;
575 rctx->dig_sz = crypto_ahash_digestsize(tfm);
577 switch (rctx->dig_sz) {
578 #ifdef CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224
579 case SHA224_DIGEST_SIZE:
580 rctx->blk_sz = SHA224_BLOCK_SIZE;
581 rctx->algo = OCS_HCU_ALGO_SHA224;
583 #endif /* CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224 */
584 case SHA256_DIGEST_SIZE:
585 rctx->blk_sz = SHA256_BLOCK_SIZE;
587 * SHA256 and SM3 have the same digest size: use info from tfm
588 * context to find out which one we should use.
590 rctx->algo = ctx->is_sm3_tfm ? OCS_HCU_ALGO_SM3 :
593 case SHA384_DIGEST_SIZE:
594 rctx->blk_sz = SHA384_BLOCK_SIZE;
595 rctx->algo = OCS_HCU_ALGO_SHA384;
597 case SHA512_DIGEST_SIZE:
598 rctx->blk_sz = SHA512_BLOCK_SIZE;
599 rctx->algo = OCS_HCU_ALGO_SHA512;
605 /* Initialize intermediate data. */
606 ocs_hcu_hash_init(&rctx->hash_ctx, rctx->algo);
608 /* If this a HMAC request, set HMAC flag. */
609 if (ctx->is_hmac_tfm)
610 rctx->flags |= REQ_FLAGS_HMAC;
615 static int kmb_ocs_hcu_update(struct ahash_request *req)
617 struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
623 rctx->sg_data_total = req->nbytes;
624 rctx->sg_data_offset = 0;
628 * If we are doing HMAC, then we must use SW-assisted HMAC, since HW
629 * HMAC does not support context switching (there it can only be used
630 * with finup() or digest()).
632 if (rctx->flags & REQ_FLAGS_HMAC &&
633 !(rctx->flags & REQ_FLAGS_HMAC_SW)) {
634 rctx->flags |= REQ_FLAGS_HMAC_SW;
635 rc = prepare_ipad(req);
641 * If remaining sg_data fits into ctx buffer, just copy it there; we'll
642 * process it at the next update() or final().
644 if (rctx->sg_data_total <= (sizeof(rctx->buffer) - rctx->buf_cnt))
645 return flush_sg_to_ocs_buffer(rctx);
647 return kmb_ocs_hcu_handle_queue(req);
650 /* Common logic for kmb_ocs_hcu_final() and kmb_ocs_hcu_finup(). */
651 static int kmb_ocs_hcu_fin_common(struct ahash_request *req)
653 struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
654 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
655 struct ocs_hcu_ctx *ctx = crypto_ahash_ctx(tfm);
658 rctx->flags |= REQ_FINAL;
661 * If this is a HMAC request and, so far, we didn't have to switch to
662 * SW HMAC, check if we can use HW HMAC.
664 if (rctx->flags & REQ_FLAGS_HMAC &&
665 !(rctx->flags & REQ_FLAGS_HMAC_SW)) {
667 * If we are here, it means we never processed any data so far,
668 * so we can use HW HMAC, but only if there is some data to
669 * process (since OCS HW MAC does not support zero-length
670 * messages) and the key length is supported by the hardware
671 * (OCS HCU HW only supports length <= 64); if HW HMAC cannot
672 * be used, fall back to SW-assisted HMAC.
674 if (kmb_get_total_data(rctx) &&
675 ctx->key_len <= OCS_HCU_HW_KEY_LEN) {
676 rctx->flags |= REQ_FLAGS_HMAC_HW;
678 rctx->flags |= REQ_FLAGS_HMAC_SW;
679 rc = prepare_ipad(req);
685 return kmb_ocs_hcu_handle_queue(req);
688 static int kmb_ocs_hcu_final(struct ahash_request *req)
690 struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
692 rctx->sg_data_total = 0;
693 rctx->sg_data_offset = 0;
696 return kmb_ocs_hcu_fin_common(req);
699 static int kmb_ocs_hcu_finup(struct ahash_request *req)
701 struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
703 rctx->sg_data_total = req->nbytes;
704 rctx->sg_data_offset = 0;
707 return kmb_ocs_hcu_fin_common(req);
710 static int kmb_ocs_hcu_digest(struct ahash_request *req)
713 struct ocs_hcu_dev *hcu_dev = kmb_ocs_hcu_find_dev(req);
718 rc = kmb_ocs_hcu_init(req);
722 rc = kmb_ocs_hcu_finup(req);
727 static int kmb_ocs_hcu_export(struct ahash_request *req, void *out)
729 struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
731 /* Intermediate data is always stored and applied per request. */
732 memcpy(out, rctx, sizeof(*rctx));
737 static int kmb_ocs_hcu_import(struct ahash_request *req, const void *in)
739 struct ocs_hcu_rctx *rctx = ahash_request_ctx(req);
741 /* Intermediate data is always stored and applied per request. */
742 memcpy(rctx, in, sizeof(*rctx));
747 static int kmb_ocs_hcu_setkey(struct crypto_ahash *tfm, const u8 *key,
750 unsigned int digestsize = crypto_ahash_digestsize(tfm);
751 struct ocs_hcu_ctx *ctx = crypto_ahash_ctx(tfm);
752 size_t blk_sz = crypto_ahash_blocksize(tfm);
753 struct crypto_ahash *ahash_tfm;
754 struct ahash_request *req;
755 struct crypto_wait wait;
756 struct scatterlist sg;
757 const char *alg_name;
761 * Key length must be equal to block size:
762 * - If key is shorter, we are done for now (the key will be padded
763 * later on); this is to maximize the use of HW HMAC (which works
764 * only for keys <= 64 bytes).
765 * - If key is longer, we hash it.
767 if (keylen <= blk_sz) {
768 memcpy(ctx->key, key, keylen);
769 ctx->key_len = keylen;
773 switch (digestsize) {
774 #ifdef CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224
775 case SHA224_DIGEST_SIZE:
776 alg_name = "sha224-keembay-ocs";
778 #endif /* CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224 */
779 case SHA256_DIGEST_SIZE:
780 alg_name = ctx->is_sm3_tfm ? "sm3-keembay-ocs" :
781 "sha256-keembay-ocs";
783 case SHA384_DIGEST_SIZE:
784 alg_name = "sha384-keembay-ocs";
786 case SHA512_DIGEST_SIZE:
787 alg_name = "sha512-keembay-ocs";
793 ahash_tfm = crypto_alloc_ahash(alg_name, 0, 0);
794 if (IS_ERR(ahash_tfm))
795 return PTR_ERR(ahash_tfm);
797 req = ahash_request_alloc(ahash_tfm, GFP_KERNEL);
803 crypto_init_wait(&wait);
804 ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
805 crypto_req_done, &wait);
806 crypto_ahash_clear_flags(ahash_tfm, ~0);
808 sg_init_one(&sg, key, keylen);
809 ahash_request_set_crypt(req, &sg, ctx->key, keylen);
811 rc = crypto_wait_req(crypto_ahash_digest(req), &wait);
813 ctx->key_len = digestsize;
815 ahash_request_free(req);
817 crypto_free_ahash(ahash_tfm);
822 /* Set request size and initialize tfm context. */
823 static void __cra_init(struct crypto_tfm *tfm, struct ocs_hcu_ctx *ctx)
825 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
826 sizeof(struct ocs_hcu_rctx));
828 /* Init context to 0. */
829 memzero_explicit(ctx, sizeof(*ctx));
830 /* Set engine ops. */
831 ctx->engine_ctx.op.do_one_request = kmb_ocs_hcu_do_one_request;
834 static int kmb_ocs_hcu_sha_cra_init(struct crypto_tfm *tfm)
836 struct ocs_hcu_ctx *ctx = crypto_tfm_ctx(tfm);
838 __cra_init(tfm, ctx);
843 static int kmb_ocs_hcu_sm3_cra_init(struct crypto_tfm *tfm)
845 struct ocs_hcu_ctx *ctx = crypto_tfm_ctx(tfm);
847 __cra_init(tfm, ctx);
849 ctx->is_sm3_tfm = true;
854 static int kmb_ocs_hcu_hmac_sm3_cra_init(struct crypto_tfm *tfm)
856 struct ocs_hcu_ctx *ctx = crypto_tfm_ctx(tfm);
858 __cra_init(tfm, ctx);
860 ctx->is_sm3_tfm = true;
861 ctx->is_hmac_tfm = true;
866 static int kmb_ocs_hcu_hmac_cra_init(struct crypto_tfm *tfm)
868 struct ocs_hcu_ctx *ctx = crypto_tfm_ctx(tfm);
870 __cra_init(tfm, ctx);
872 ctx->is_hmac_tfm = true;
877 /* Function called when 'tfm' is de-initialized. */
878 static void kmb_ocs_hcu_hmac_cra_exit(struct crypto_tfm *tfm)
880 struct ocs_hcu_ctx *ctx = crypto_tfm_ctx(tfm);
883 memzero_explicit(ctx->key, sizeof(ctx->key));
886 static struct ahash_alg ocs_hcu_algs[] = {
887 #ifdef CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224
889 .init = kmb_ocs_hcu_init,
890 .update = kmb_ocs_hcu_update,
891 .final = kmb_ocs_hcu_final,
892 .finup = kmb_ocs_hcu_finup,
893 .digest = kmb_ocs_hcu_digest,
894 .export = kmb_ocs_hcu_export,
895 .import = kmb_ocs_hcu_import,
897 .digestsize = SHA224_DIGEST_SIZE,
898 .statesize = sizeof(struct ocs_hcu_rctx),
900 .cra_name = "sha224",
901 .cra_driver_name = "sha224-keembay-ocs",
903 .cra_flags = CRYPTO_ALG_ASYNC,
904 .cra_blocksize = SHA224_BLOCK_SIZE,
905 .cra_ctxsize = sizeof(struct ocs_hcu_ctx),
907 .cra_module = THIS_MODULE,
908 .cra_init = kmb_ocs_hcu_sha_cra_init,
913 .init = kmb_ocs_hcu_init,
914 .update = kmb_ocs_hcu_update,
915 .final = kmb_ocs_hcu_final,
916 .finup = kmb_ocs_hcu_finup,
917 .digest = kmb_ocs_hcu_digest,
918 .export = kmb_ocs_hcu_export,
919 .import = kmb_ocs_hcu_import,
920 .setkey = kmb_ocs_hcu_setkey,
922 .digestsize = SHA224_DIGEST_SIZE,
923 .statesize = sizeof(struct ocs_hcu_rctx),
925 .cra_name = "hmac(sha224)",
926 .cra_driver_name = "hmac-sha224-keembay-ocs",
928 .cra_flags = CRYPTO_ALG_ASYNC,
929 .cra_blocksize = SHA224_BLOCK_SIZE,
930 .cra_ctxsize = sizeof(struct ocs_hcu_ctx),
932 .cra_module = THIS_MODULE,
933 .cra_init = kmb_ocs_hcu_hmac_cra_init,
934 .cra_exit = kmb_ocs_hcu_hmac_cra_exit,
938 #endif /* CONFIG_CRYPTO_DEV_KEEMBAY_OCS_HCU_HMAC_SHA224 */
940 .init = kmb_ocs_hcu_init,
941 .update = kmb_ocs_hcu_update,
942 .final = kmb_ocs_hcu_final,
943 .finup = kmb_ocs_hcu_finup,
944 .digest = kmb_ocs_hcu_digest,
945 .export = kmb_ocs_hcu_export,
946 .import = kmb_ocs_hcu_import,
948 .digestsize = SHA256_DIGEST_SIZE,
949 .statesize = sizeof(struct ocs_hcu_rctx),
951 .cra_name = "sha256",
952 .cra_driver_name = "sha256-keembay-ocs",
954 .cra_flags = CRYPTO_ALG_ASYNC,
955 .cra_blocksize = SHA256_BLOCK_SIZE,
956 .cra_ctxsize = sizeof(struct ocs_hcu_ctx),
958 .cra_module = THIS_MODULE,
959 .cra_init = kmb_ocs_hcu_sha_cra_init,
964 .init = kmb_ocs_hcu_init,
965 .update = kmb_ocs_hcu_update,
966 .final = kmb_ocs_hcu_final,
967 .finup = kmb_ocs_hcu_finup,
968 .digest = kmb_ocs_hcu_digest,
969 .export = kmb_ocs_hcu_export,
970 .import = kmb_ocs_hcu_import,
971 .setkey = kmb_ocs_hcu_setkey,
973 .digestsize = SHA256_DIGEST_SIZE,
974 .statesize = sizeof(struct ocs_hcu_rctx),
976 .cra_name = "hmac(sha256)",
977 .cra_driver_name = "hmac-sha256-keembay-ocs",
979 .cra_flags = CRYPTO_ALG_ASYNC,
980 .cra_blocksize = SHA256_BLOCK_SIZE,
981 .cra_ctxsize = sizeof(struct ocs_hcu_ctx),
983 .cra_module = THIS_MODULE,
984 .cra_init = kmb_ocs_hcu_hmac_cra_init,
985 .cra_exit = kmb_ocs_hcu_hmac_cra_exit,
990 .init = kmb_ocs_hcu_init,
991 .update = kmb_ocs_hcu_update,
992 .final = kmb_ocs_hcu_final,
993 .finup = kmb_ocs_hcu_finup,
994 .digest = kmb_ocs_hcu_digest,
995 .export = kmb_ocs_hcu_export,
996 .import = kmb_ocs_hcu_import,
998 .digestsize = SM3_DIGEST_SIZE,
999 .statesize = sizeof(struct ocs_hcu_rctx),
1002 .cra_driver_name = "sm3-keembay-ocs",
1003 .cra_priority = 255,
1004 .cra_flags = CRYPTO_ALG_ASYNC,
1005 .cra_blocksize = SM3_BLOCK_SIZE,
1006 .cra_ctxsize = sizeof(struct ocs_hcu_ctx),
1008 .cra_module = THIS_MODULE,
1009 .cra_init = kmb_ocs_hcu_sm3_cra_init,
1014 .init = kmb_ocs_hcu_init,
1015 .update = kmb_ocs_hcu_update,
1016 .final = kmb_ocs_hcu_final,
1017 .finup = kmb_ocs_hcu_finup,
1018 .digest = kmb_ocs_hcu_digest,
1019 .export = kmb_ocs_hcu_export,
1020 .import = kmb_ocs_hcu_import,
1021 .setkey = kmb_ocs_hcu_setkey,
1023 .digestsize = SM3_DIGEST_SIZE,
1024 .statesize = sizeof(struct ocs_hcu_rctx),
1026 .cra_name = "hmac(sm3)",
1027 .cra_driver_name = "hmac-sm3-keembay-ocs",
1028 .cra_priority = 255,
1029 .cra_flags = CRYPTO_ALG_ASYNC,
1030 .cra_blocksize = SM3_BLOCK_SIZE,
1031 .cra_ctxsize = sizeof(struct ocs_hcu_ctx),
1033 .cra_module = THIS_MODULE,
1034 .cra_init = kmb_ocs_hcu_hmac_sm3_cra_init,
1035 .cra_exit = kmb_ocs_hcu_hmac_cra_exit,
1040 .init = kmb_ocs_hcu_init,
1041 .update = kmb_ocs_hcu_update,
1042 .final = kmb_ocs_hcu_final,
1043 .finup = kmb_ocs_hcu_finup,
1044 .digest = kmb_ocs_hcu_digest,
1045 .export = kmb_ocs_hcu_export,
1046 .import = kmb_ocs_hcu_import,
1048 .digestsize = SHA384_DIGEST_SIZE,
1049 .statesize = sizeof(struct ocs_hcu_rctx),
1051 .cra_name = "sha384",
1052 .cra_driver_name = "sha384-keembay-ocs",
1053 .cra_priority = 255,
1054 .cra_flags = CRYPTO_ALG_ASYNC,
1055 .cra_blocksize = SHA384_BLOCK_SIZE,
1056 .cra_ctxsize = sizeof(struct ocs_hcu_ctx),
1058 .cra_module = THIS_MODULE,
1059 .cra_init = kmb_ocs_hcu_sha_cra_init,
1064 .init = kmb_ocs_hcu_init,
1065 .update = kmb_ocs_hcu_update,
1066 .final = kmb_ocs_hcu_final,
1067 .finup = kmb_ocs_hcu_finup,
1068 .digest = kmb_ocs_hcu_digest,
1069 .export = kmb_ocs_hcu_export,
1070 .import = kmb_ocs_hcu_import,
1071 .setkey = kmb_ocs_hcu_setkey,
1073 .digestsize = SHA384_DIGEST_SIZE,
1074 .statesize = sizeof(struct ocs_hcu_rctx),
1076 .cra_name = "hmac(sha384)",
1077 .cra_driver_name = "hmac-sha384-keembay-ocs",
1078 .cra_priority = 255,
1079 .cra_flags = CRYPTO_ALG_ASYNC,
1080 .cra_blocksize = SHA384_BLOCK_SIZE,
1081 .cra_ctxsize = sizeof(struct ocs_hcu_ctx),
1083 .cra_module = THIS_MODULE,
1084 .cra_init = kmb_ocs_hcu_hmac_cra_init,
1085 .cra_exit = kmb_ocs_hcu_hmac_cra_exit,
1090 .init = kmb_ocs_hcu_init,
1091 .update = kmb_ocs_hcu_update,
1092 .final = kmb_ocs_hcu_final,
1093 .finup = kmb_ocs_hcu_finup,
1094 .digest = kmb_ocs_hcu_digest,
1095 .export = kmb_ocs_hcu_export,
1096 .import = kmb_ocs_hcu_import,
1098 .digestsize = SHA512_DIGEST_SIZE,
1099 .statesize = sizeof(struct ocs_hcu_rctx),
1101 .cra_name = "sha512",
1102 .cra_driver_name = "sha512-keembay-ocs",
1103 .cra_priority = 255,
1104 .cra_flags = CRYPTO_ALG_ASYNC,
1105 .cra_blocksize = SHA512_BLOCK_SIZE,
1106 .cra_ctxsize = sizeof(struct ocs_hcu_ctx),
1108 .cra_module = THIS_MODULE,
1109 .cra_init = kmb_ocs_hcu_sha_cra_init,
1114 .init = kmb_ocs_hcu_init,
1115 .update = kmb_ocs_hcu_update,
1116 .final = kmb_ocs_hcu_final,
1117 .finup = kmb_ocs_hcu_finup,
1118 .digest = kmb_ocs_hcu_digest,
1119 .export = kmb_ocs_hcu_export,
1120 .import = kmb_ocs_hcu_import,
1121 .setkey = kmb_ocs_hcu_setkey,
1123 .digestsize = SHA512_DIGEST_SIZE,
1124 .statesize = sizeof(struct ocs_hcu_rctx),
1126 .cra_name = "hmac(sha512)",
1127 .cra_driver_name = "hmac-sha512-keembay-ocs",
1128 .cra_priority = 255,
1129 .cra_flags = CRYPTO_ALG_ASYNC,
1130 .cra_blocksize = SHA512_BLOCK_SIZE,
1131 .cra_ctxsize = sizeof(struct ocs_hcu_ctx),
1133 .cra_module = THIS_MODULE,
1134 .cra_init = kmb_ocs_hcu_hmac_cra_init,
1135 .cra_exit = kmb_ocs_hcu_hmac_cra_exit,
1141 /* Device tree driver match. */
1142 static const struct of_device_id kmb_ocs_hcu_of_match[] = {
1144 .compatible = "intel,keembay-ocs-hcu",
1149 static int kmb_ocs_hcu_remove(struct platform_device *pdev)
1151 struct ocs_hcu_dev *hcu_dev;
1154 hcu_dev = platform_get_drvdata(pdev);
1158 crypto_unregister_ahashes(ocs_hcu_algs, ARRAY_SIZE(ocs_hcu_algs));
1160 rc = crypto_engine_exit(hcu_dev->engine);
1162 spin_lock_bh(&ocs_hcu.lock);
1163 list_del(&hcu_dev->list);
1164 spin_unlock_bh(&ocs_hcu.lock);
1169 static int kmb_ocs_hcu_probe(struct platform_device *pdev)
1171 struct device *dev = &pdev->dev;
1172 struct ocs_hcu_dev *hcu_dev;
1173 struct resource *hcu_mem;
1176 hcu_dev = devm_kzalloc(dev, sizeof(*hcu_dev), GFP_KERNEL);
1182 platform_set_drvdata(pdev, hcu_dev);
1183 rc = dma_set_mask_and_coherent(&pdev->dev, OCS_HCU_DMA_BIT_MASK);
1187 /* Get the memory address and remap. */
1188 hcu_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1190 dev_err(dev, "Could not retrieve io mem resource.\n");
1194 hcu_dev->io_base = devm_ioremap_resource(dev, hcu_mem);
1195 if (IS_ERR(hcu_dev->io_base))
1196 return PTR_ERR(hcu_dev->io_base);
1198 init_completion(&hcu_dev->irq_done);
1200 /* Get and request IRQ. */
1201 hcu_dev->irq = platform_get_irq(pdev, 0);
1202 if (hcu_dev->irq < 0)
1203 return hcu_dev->irq;
1205 rc = devm_request_threaded_irq(&pdev->dev, hcu_dev->irq,
1206 ocs_hcu_irq_handler, NULL, 0,
1207 "keembay-ocs-hcu", hcu_dev);
1209 dev_err(dev, "Could not request IRQ.\n");
1213 INIT_LIST_HEAD(&hcu_dev->list);
1215 spin_lock_bh(&ocs_hcu.lock);
1216 list_add_tail(&hcu_dev->list, &ocs_hcu.dev_list);
1217 spin_unlock_bh(&ocs_hcu.lock);
1219 /* Initialize crypto engine */
1220 hcu_dev->engine = crypto_engine_alloc_init(dev, 1);
1221 if (!hcu_dev->engine) {
1226 rc = crypto_engine_start(hcu_dev->engine);
1228 dev_err(dev, "Could not start engine.\n");
1232 /* Security infrastructure guarantees OCS clock is enabled. */
1234 rc = crypto_register_ahashes(ocs_hcu_algs, ARRAY_SIZE(ocs_hcu_algs));
1236 dev_err(dev, "Could not register algorithms.\n");
1243 crypto_engine_exit(hcu_dev->engine);
1245 spin_lock_bh(&ocs_hcu.lock);
1246 list_del(&hcu_dev->list);
1247 spin_unlock_bh(&ocs_hcu.lock);
1252 /* The OCS driver is a platform device. */
1253 static struct platform_driver kmb_ocs_hcu_driver = {
1254 .probe = kmb_ocs_hcu_probe,
1255 .remove = kmb_ocs_hcu_remove,
1258 .of_match_table = kmb_ocs_hcu_of_match,
1262 module_platform_driver(kmb_ocs_hcu_driver);
1264 MODULE_LICENSE("GPL");