1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2019 HiSilicon Limited. */
4 #ifndef __HISI_SEC_V2_CRYPTO_H
5 #define __HISI_SEC_V2_CRYPTO_H
8 #define SEC_MAX_KEY_SIZE 64
9 #define SEC_MAX_AKEY_SIZE 128
10 #define SEC_COMM_SCENE 0
19 SEC_A_HMAC_SHA1 = 0x10,
20 SEC_A_HMAC_SHA256 = 0x11,
21 SEC_A_HMAC_SHA512 = 0x15,
25 SEC_HMAC_SHA1_MAC = 20,
26 SEC_HMAC_SHA256_MAC = 32,
27 SEC_HMAC_SHA512_MAC = 64,
38 SEC_CKEY_128BIT = 0x0,
39 SEC_CKEY_192BIT = 0x1,
40 SEC_CKEY_256BIT = 0x2,
41 SEC_CKEY_3DES_3KEY = 0x1,
42 SEC_CKEY_3DES_2KEY = 0x3,
67 struct sec_sqe_type2 {
70 * a_key_len: 5~10 bits
78 * c_key_len: 9~11 bits
89 * iv_offset_l: 24~31 bits
95 * iv_offset_h: 24~31 bits
99 __le16 auth_src_offset;
100 __le16 cipher_src_offset;
101 __le16 cs_ip_header_offset;
102 __le16 cs_udp_header_offset;
103 __le16 pass_word_len;
114 * c_pad_type: 0~3 bits
115 * c_pad_len: 4~11 bits
116 * c_pad_data_type: 12~15 bits
120 /* c_pad_len_field: 0~1 bits */
121 __le16 c_pad_len_field;
123 __le64 long_a_data_len;
130 __le64 data_src_addr;
131 __le64 data_dst_addr;
138 * dif_check: 11~13 bits
160 __u8 type_cipher_auth;
166 * src_addr_type: ~7 bit, with sdm_addr_type 0-1 bits
171 * src_addr_type: 0~1 bits, not used now,
172 * if support PRP, set this field, or set zero.
173 * dst_addr_type: 2~4 bits
174 * mac_addr_type: 5~7 bits
180 * nonce_len(type2): 0~3 bits
182 * key_s(type2): 5 bit
189 * a_pad(type2): 2~3 bits
190 * c_s(type2): 4~5 bits
196 * c_key_type: 1~2 bits
197 * a_key_type: 3~4 bits
198 * write_frame_len(type2): 5~7 bits
203 * cal_iv_addr_en(type2): 0 bit
204 * tls_up(type2): 1 bit
209 /* Just using type2 BD now */
210 struct sec_sqe_type2 type2;
213 int sec_register_to_crypto(void);
214 void sec_unregister_from_crypto(void);