1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2019 HiSilicon Limited. */
6 #include <linux/bitfield.h>
7 #include <linux/iopoll.h>
8 #include <linux/module.h>
11 #define QM_QNUM_V1 4096
12 #define QM_QNUM_V2 1024
13 #define QM_MAX_VFS_NUM_V2 63
16 #define QM_ARUSER_M_CFG_1 0x100088
17 #define AXUSER_SNOOP_ENABLE BIT(30)
18 #define AXUSER_CMD_TYPE GENMASK(14, 12)
19 #define AXUSER_CMD_SMMU_NORMAL 1
20 #define AXUSER_NS BIT(6)
21 #define AXUSER_NO BIT(5)
22 #define AXUSER_FP BIT(4)
23 #define AXUSER_SSV BIT(0)
24 #define AXUSER_BASE (AXUSER_SNOOP_ENABLE | \
25 FIELD_PREP(AXUSER_CMD_TYPE, \
26 AXUSER_CMD_SMMU_NORMAL) | \
27 AXUSER_NS | AXUSER_NO | AXUSER_FP)
28 #define QM_ARUSER_M_CFG_ENABLE 0x100090
29 #define ARUSER_M_CFG_ENABLE 0xfffffffe
30 #define QM_AWUSER_M_CFG_1 0x100098
31 #define QM_AWUSER_M_CFG_ENABLE 0x1000a0
32 #define AWUSER_M_CFG_ENABLE 0xfffffffe
33 #define QM_WUSER_M_CFG_ENABLE 0x1000a8
34 #define WUSER_M_CFG_ENABLE 0xffffffff
37 #define QM_CACHE_CTL 0x100050
38 #define SQC_CACHE_ENABLE BIT(0)
39 #define CQC_CACHE_ENABLE BIT(1)
40 #define SQC_CACHE_WB_ENABLE BIT(4)
41 #define SQC_CACHE_WB_THRD GENMASK(10, 5)
42 #define CQC_CACHE_WB_ENABLE BIT(11)
43 #define CQC_CACHE_WB_THRD GENMASK(17, 12)
44 #define QM_AXI_M_CFG 0x1000ac
45 #define AXI_M_CFG 0xffff
46 #define QM_AXI_M_CFG_ENABLE 0x1000b0
47 #define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014
48 #define AXI_M_CFG_ENABLE 0xffffffff
49 #define QM_PEH_AXUSER_CFG 0x1000cc
50 #define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
51 #define PEH_AXUSER_CFG 0x401001
52 #define PEH_AXUSER_CFG_ENABLE 0xffffffff
54 #define QM_DFX_MB_CNT_VF 0x104010
55 #define QM_DFX_DB_CNT_VF 0x104020
56 #define QM_DFX_SQE_CNT_VF_SQN 0x104030
57 #define QM_DFX_CQE_CNT_VF_CQN 0x104040
58 #define QM_DFX_QN_SHIFT 16
59 #define CURRENT_FUN_MASK GENMASK(5, 0)
60 #define CURRENT_Q_MASK GENMASK(31, 16)
62 #define QM_AXI_RRESP BIT(0)
63 #define QM_AXI_BRESP BIT(1)
64 #define QM_ECC_MBIT BIT(2)
65 #define QM_ECC_1BIT BIT(3)
66 #define QM_ACC_GET_TASK_TIMEOUT BIT(4)
67 #define QM_ACC_DO_TASK_TIMEOUT BIT(5)
68 #define QM_ACC_WB_NOT_READY_TIMEOUT BIT(6)
69 #define QM_SQ_CQ_VF_INVALID BIT(7)
70 #define QM_CQ_VF_INVALID BIT(8)
71 #define QM_SQ_VF_INVALID BIT(9)
72 #define QM_DB_TIMEOUT BIT(10)
73 #define QM_OF_FIFO_OF BIT(11)
74 #define QM_DB_RANDOM_INVALID BIT(12)
76 #define QM_BASE_NFE (QM_AXI_RRESP | QM_AXI_BRESP | QM_ECC_MBIT | \
77 QM_ACC_GET_TASK_TIMEOUT | QM_DB_TIMEOUT | \
78 QM_OF_FIFO_OF | QM_DB_RANDOM_INVALID)
79 #define QM_BASE_CE QM_ECC_1BIT
81 #define QM_Q_DEPTH 1024
83 #define HISI_ACC_SGL_SGE_NR_MAX 255
85 /* page number for queue file region */
86 #define QM_DOORBELL_PAGE_NR 1
127 atomic64_t err_irq_cnt;
128 atomic64_t aeq_irq_cnt;
129 atomic64_t abnormal_irq_cnt;
130 atomic64_t create_qp_err_cnt;
131 atomic64_t mb_err_cnt;
134 struct debugfs_file {
135 enum qm_debug_file index;
137 struct qm_debug *debug;
145 struct dentry *debug_root;
147 struct debugfs_file files[DEBUG_FILE_NUM];
156 struct hisi_qm_status {
167 struct hisi_qm_err_info {
176 struct hisi_qm_err_status {
181 struct hisi_qm_err_ini {
182 int (*hw_init)(struct hisi_qm *qm);
183 void (*hw_err_enable)(struct hisi_qm *qm);
184 void (*hw_err_disable)(struct hisi_qm *qm);
185 u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
186 void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
187 void (*open_axi_master_ooo)(struct hisi_qm *qm);
188 void (*close_axi_master_ooo)(struct hisi_qm *qm);
189 void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
190 struct hisi_qm_err_info err_info;
193 struct hisi_qm_list {
195 struct list_head list;
196 int (*register_to_crypto)(void);
197 void (*unregister_from_crypto)(void);
202 enum qm_fun_type fun_type;
203 const char *dev_name;
204 struct pci_dev *pdev;
205 void __iomem *io_base;
212 struct list_head list;
213 struct hisi_qm_list *qm_list;
219 struct qm_aeqe *aeqe;
225 struct hisi_qm_status status;
226 const struct hisi_qm_err_ini *err_ini;
227 struct hisi_qm_err_status err_status;
228 unsigned long reset_flag;
230 struct rw_semaphore qps_lock;
232 struct hisi_qp *qp_array;
234 struct mutex mailbox_lock;
236 const struct hisi_qm_hw_ops *ops;
238 struct qm_debug debug;
242 struct workqueue_struct *wq;
243 struct work_struct work;
244 struct work_struct rst_work;
249 resource_size_t phys_base;
250 resource_size_t phys_size;
251 struct uacce_device *uacce;
254 struct hisi_qp_status {
263 int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
277 struct hisi_qp_status qp_status;
278 struct hisi_qp_ops *hw_ops;
280 void (*req_cb)(struct hisi_qp *qp, void *data);
281 void (*event_cb)(struct hisi_qp *qp);
286 struct uacce_queue *uacce_q;
289 static inline int q_num_set(const char *val, const struct kernel_param *kp,
292 struct pci_dev *pdev;
299 pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI, device, NULL);
301 q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
302 pr_info("No device found currently, suppose queue number is %d\n",
305 if (pdev->revision == QM_HW_V1)
313 ret = kstrtou32(val, 10, &n);
314 if (ret || n < QM_MIN_QNUM || n > q_num)
317 return param_set_int(val, kp);
320 static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
328 ret = kstrtou32(val, 10, &n);
332 if (n > QM_MAX_VFS_NUM_V2)
335 return param_set_int(val, kp);
338 static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
340 INIT_LIST_HEAD(&qm_list->list);
341 mutex_init(&qm_list->lock);
344 int hisi_qm_init(struct hisi_qm *qm);
345 void hisi_qm_uninit(struct hisi_qm *qm);
346 int hisi_qm_start(struct hisi_qm *qm);
347 int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
348 struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type);
349 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
350 int hisi_qm_stop_qp(struct hisi_qp *qp);
351 void hisi_qm_release_qp(struct hisi_qp *qp);
352 int hisi_qp_send(struct hisi_qp *qp, const void *msg);
353 int hisi_qm_get_free_qp_num(struct hisi_qm *qm);
354 int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number);
355 int hisi_qm_debug_init(struct hisi_qm *qm);
356 enum qm_hw_ver hisi_qm_get_hw_version(struct pci_dev *pdev);
357 void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
358 int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
359 int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
360 int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
361 void hisi_qm_dev_err_init(struct hisi_qm *qm);
362 void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
363 pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
364 pci_channel_state_t state);
365 pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
366 void hisi_qm_reset_prepare(struct pci_dev *pdev);
367 void hisi_qm_reset_done(struct pci_dev *pdev);
369 struct hisi_acc_sgl_pool;
370 struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
371 struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
372 u32 index, dma_addr_t *hw_sgl_dma);
373 void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
374 struct hisi_acc_hw_sgl *hw_sgl);
375 struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
376 u32 count, u32 sge_nr);
377 void hisi_acc_free_sgl_pool(struct device *dev,
378 struct hisi_acc_sgl_pool *pool);
379 int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
380 u8 alg_type, int node, struct hisi_qp **qps);
381 void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
382 void hisi_qm_dev_shutdown(struct pci_dev *pdev);
383 void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
384 int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
385 void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list);