1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <crypto/algapi.h>
7 #include <crypto/internal/skcipher.h>
8 #include <crypto/des.h>
9 #include <crypto/xts.h>
10 #include <crypto/scatterwalk.h>
12 #include "cc_driver.h"
13 #include "cc_lli_defs.h"
14 #include "cc_buffer_mgr.h"
15 #include "cc_cipher.h"
16 #include "cc_request_mgr.h"
18 #define MAX_ABLKCIPHER_SEQ_LEN 6
20 #define template_skcipher template_u.skcipher
22 struct cc_cipher_handle {
23 struct list_head alg_list;
26 struct cc_user_key_info {
28 dma_addr_t key_dma_addr;
31 struct cc_hw_key_info {
32 enum cc_hw_crypto_key key1_slot;
33 enum cc_hw_crypto_key key2_slot;
36 struct cc_cipher_ctx {
37 struct cc_drvdata *drvdata;
44 struct cc_user_key_info user;
45 struct cc_hw_key_info hw;
46 struct crypto_shash *shash_tfm;
49 static void cc_cipher_complete(struct device *dev, void *cc_req, int err);
51 static inline bool cc_is_hw_key(struct crypto_tfm *tfm)
53 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
58 static int validate_keys_sizes(struct cc_cipher_ctx *ctx_p, u32 size)
60 switch (ctx_p->flow_mode) {
63 case CC_AES_128_BIT_KEY_SIZE:
64 case CC_AES_192_BIT_KEY_SIZE:
65 if (ctx_p->cipher_mode != DRV_CIPHER_XTS &&
66 ctx_p->cipher_mode != DRV_CIPHER_ESSIV &&
67 ctx_p->cipher_mode != DRV_CIPHER_BITLOCKER)
70 case CC_AES_256_BIT_KEY_SIZE:
72 case (CC_AES_192_BIT_KEY_SIZE * 2):
73 case (CC_AES_256_BIT_KEY_SIZE * 2):
74 if (ctx_p->cipher_mode == DRV_CIPHER_XTS ||
75 ctx_p->cipher_mode == DRV_CIPHER_ESSIV ||
76 ctx_p->cipher_mode == DRV_CIPHER_BITLOCKER)
84 if (size == DES3_EDE_KEY_SIZE || size == DES_KEY_SIZE)
93 static int validate_data_size(struct cc_cipher_ctx *ctx_p,
96 switch (ctx_p->flow_mode) {
98 switch (ctx_p->cipher_mode) {
100 if (size >= AES_BLOCK_SIZE &&
101 IS_ALIGNED(size, AES_BLOCK_SIZE))
104 case DRV_CIPHER_CBC_CTS:
105 if (size >= AES_BLOCK_SIZE)
113 case DRV_CIPHER_ESSIV:
114 case DRV_CIPHER_BITLOCKER:
115 if (IS_ALIGNED(size, AES_BLOCK_SIZE))
123 if (IS_ALIGNED(size, DES_BLOCK_SIZE))
132 static int cc_cipher_init(struct crypto_tfm *tfm)
134 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
135 struct cc_crypto_alg *cc_alg =
136 container_of(tfm->__crt_alg, struct cc_crypto_alg,
138 struct device *dev = drvdata_to_dev(cc_alg->drvdata);
139 unsigned int max_key_buf_size = cc_alg->skcipher_alg.max_keysize;
141 dev_dbg(dev, "Initializing context @%p for %s\n", ctx_p,
142 crypto_tfm_alg_name(tfm));
144 crypto_skcipher_set_reqsize(__crypto_skcipher_cast(tfm),
145 sizeof(struct cipher_req_ctx));
147 ctx_p->cipher_mode = cc_alg->cipher_mode;
148 ctx_p->flow_mode = cc_alg->flow_mode;
149 ctx_p->drvdata = cc_alg->drvdata;
151 if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) {
152 /* Alloc hash tfm for essiv */
153 ctx_p->shash_tfm = crypto_alloc_shash("sha256-generic", 0, 0);
154 if (IS_ERR(ctx_p->shash_tfm)) {
155 dev_err(dev, "Error allocating hash tfm for ESSIV.\n");
156 return PTR_ERR(ctx_p->shash_tfm);
160 /* Allocate key buffer, cache line aligned */
161 ctx_p->user.key = kmalloc(max_key_buf_size, GFP_KERNEL);
162 if (!ctx_p->user.key)
165 dev_dbg(dev, "Allocated key buffer in context. key=@%p\n",
169 ctx_p->user.key_dma_addr = dma_map_single(dev, (void *)ctx_p->user.key,
172 if (dma_mapping_error(dev, ctx_p->user.key_dma_addr)) {
173 dev_err(dev, "Mapping Key %u B at va=%pK for DMA failed\n",
174 max_key_buf_size, ctx_p->user.key);
177 dev_dbg(dev, "Mapped key %u B at va=%pK to dma=%pad\n",
178 max_key_buf_size, ctx_p->user.key, &ctx_p->user.key_dma_addr);
183 kfree(ctx_p->user.key);
185 crypto_free_shash(ctx_p->shash_tfm);
190 static void cc_cipher_exit(struct crypto_tfm *tfm)
192 struct crypto_alg *alg = tfm->__crt_alg;
193 struct cc_crypto_alg *cc_alg =
194 container_of(alg, struct cc_crypto_alg,
196 unsigned int max_key_buf_size = cc_alg->skcipher_alg.max_keysize;
197 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
198 struct device *dev = drvdata_to_dev(ctx_p->drvdata);
200 dev_dbg(dev, "Clearing context @%p for %s\n",
201 crypto_tfm_ctx(tfm), crypto_tfm_alg_name(tfm));
203 if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) {
204 /* Free hash tfm for essiv */
205 crypto_free_shash(ctx_p->shash_tfm);
206 ctx_p->shash_tfm = NULL;
209 /* Unmap key buffer */
210 dma_unmap_single(dev, ctx_p->user.key_dma_addr, max_key_buf_size,
212 dev_dbg(dev, "Unmapped key buffer key_dma_addr=%pad\n",
213 &ctx_p->user.key_dma_addr);
215 /* Free key buffer in context */
216 kzfree(ctx_p->user.key);
217 dev_dbg(dev, "Free key buffer in context. key=@%p\n", ctx_p->user.key);
221 u8 key1[DES_KEY_SIZE];
222 u8 key2[DES_KEY_SIZE];
223 u8 key3[DES_KEY_SIZE];
226 static enum cc_hw_crypto_key cc_slot_to_hw_key(int slot_num)
241 static int cc_cipher_sethkey(struct crypto_skcipher *sktfm, const u8 *key,
244 struct crypto_tfm *tfm = crypto_skcipher_tfm(sktfm);
245 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
246 struct device *dev = drvdata_to_dev(ctx_p->drvdata);
247 struct cc_hkey_info hki;
249 dev_dbg(dev, "Setting HW key in context @%p for %s. keylen=%u\n",
250 ctx_p, crypto_tfm_alg_name(tfm), keylen);
251 dump_byte_array("key", (u8 *)key, keylen);
253 /* STAT_PHASE_0: Init and sanity checks */
255 /* This check the size of the hardware key token */
256 if (keylen != sizeof(hki)) {
257 dev_err(dev, "Unsupported HW key size %d.\n", keylen);
258 crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
262 if (ctx_p->flow_mode != S_DIN_to_AES) {
263 dev_err(dev, "HW key not supported for non-AES flows\n");
267 memcpy(&hki, key, keylen);
269 /* The real key len for crypto op is the size of the HW key
270 * referenced by the HW key slot, not the hardware key token
274 if (validate_keys_sizes(ctx_p, keylen)) {
275 dev_err(dev, "Unsupported key size %d.\n", keylen);
276 crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
280 ctx_p->hw.key1_slot = cc_slot_to_hw_key(hki.hw_key1);
281 if (ctx_p->hw.key1_slot == END_OF_KEYS) {
282 dev_err(dev, "Unsupported hw key1 number (%d)\n", hki.hw_key1);
286 if (ctx_p->cipher_mode == DRV_CIPHER_XTS ||
287 ctx_p->cipher_mode == DRV_CIPHER_ESSIV ||
288 ctx_p->cipher_mode == DRV_CIPHER_BITLOCKER) {
289 if (hki.hw_key1 == hki.hw_key2) {
290 dev_err(dev, "Illegal hw key numbers (%d,%d)\n",
291 hki.hw_key1, hki.hw_key2);
294 ctx_p->hw.key2_slot = cc_slot_to_hw_key(hki.hw_key2);
295 if (ctx_p->hw.key2_slot == END_OF_KEYS) {
296 dev_err(dev, "Unsupported hw key2 number (%d)\n",
302 ctx_p->keylen = keylen;
303 ctx_p->hw_key = true;
304 dev_dbg(dev, "cc_is_hw_key ret 0");
309 static int cc_cipher_setkey(struct crypto_skcipher *sktfm, const u8 *key,
312 struct crypto_tfm *tfm = crypto_skcipher_tfm(sktfm);
313 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
314 struct device *dev = drvdata_to_dev(ctx_p->drvdata);
315 struct cc_crypto_alg *cc_alg =
316 container_of(tfm->__crt_alg, struct cc_crypto_alg,
318 unsigned int max_key_buf_size = cc_alg->skcipher_alg.max_keysize;
320 dev_dbg(dev, "Setting key in context @%p for %s. keylen=%u\n",
321 ctx_p, crypto_tfm_alg_name(tfm), keylen);
322 dump_byte_array("key", (u8 *)key, keylen);
324 /* STAT_PHASE_0: Init and sanity checks */
326 if (validate_keys_sizes(ctx_p, keylen)) {
327 dev_err(dev, "Unsupported key size %d.\n", keylen);
328 crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
332 ctx_p->hw_key = false;
335 * Verify DES weak keys
336 * Note that we're dropping the expanded key since the
337 * HW does the expansion on its own.
339 if (ctx_p->flow_mode == S_DIN_to_DES) {
340 u32 tmp[DES3_EDE_EXPKEY_WORDS];
341 if (keylen == DES3_EDE_KEY_SIZE &&
342 __des3_ede_setkey(tmp, &tfm->crt_flags, key,
343 DES3_EDE_KEY_SIZE)) {
344 dev_dbg(dev, "weak 3DES key");
346 } else if (!des_ekey(tmp, key) &&
347 (crypto_tfm_get_flags(tfm) & CRYPTO_TFM_REQ_WEAK_KEY)) {
348 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
349 dev_dbg(dev, "weak DES key");
354 if (ctx_p->cipher_mode == DRV_CIPHER_XTS &&
355 xts_check_key(tfm, key, keylen)) {
356 dev_dbg(dev, "weak XTS key");
360 /* STAT_PHASE_1: Copy key to ctx */
361 dma_sync_single_for_cpu(dev, ctx_p->user.key_dma_addr,
362 max_key_buf_size, DMA_TO_DEVICE);
364 memcpy(ctx_p->user.key, key, keylen);
366 memset(ctx_p->user.key + 24, 0, CC_AES_KEY_SIZE_MAX - 24);
368 if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) {
369 /* sha256 for key2 - use sw implementation */
370 int key_len = keylen >> 1;
373 SHASH_DESC_ON_STACK(desc, ctx_p->shash_tfm);
375 desc->tfm = ctx_p->shash_tfm;
377 err = crypto_shash_digest(desc, ctx_p->user.key, key_len,
378 ctx_p->user.key + key_len);
380 dev_err(dev, "Failed to hash ESSIV key.\n");
384 dma_sync_single_for_device(dev, ctx_p->user.key_dma_addr,
385 max_key_buf_size, DMA_TO_DEVICE);
386 ctx_p->keylen = keylen;
388 dev_dbg(dev, "return safely");
392 static void cc_setup_cipher_desc(struct crypto_tfm *tfm,
393 struct cipher_req_ctx *req_ctx,
394 unsigned int ivsize, unsigned int nbytes,
395 struct cc_hw_desc desc[],
396 unsigned int *seq_size)
398 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
399 struct device *dev = drvdata_to_dev(ctx_p->drvdata);
400 int cipher_mode = ctx_p->cipher_mode;
401 int flow_mode = ctx_p->flow_mode;
402 int direction = req_ctx->gen_ctx.op_type;
403 dma_addr_t key_dma_addr = ctx_p->user.key_dma_addr;
404 unsigned int key_len = ctx_p->keylen;
405 dma_addr_t iv_dma_addr = req_ctx->gen_ctx.iv_dma_addr;
406 unsigned int du_size = nbytes;
408 struct cc_crypto_alg *cc_alg =
409 container_of(tfm->__crt_alg, struct cc_crypto_alg,
412 if (cc_alg->data_unit)
413 du_size = cc_alg->data_unit;
415 switch (cipher_mode) {
417 case DRV_CIPHER_CBC_CTS:
420 /* Load cipher state */
421 hw_desc_init(&desc[*seq_size]);
422 set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr, ivsize,
424 set_cipher_config0(&desc[*seq_size], direction);
425 set_flow_mode(&desc[*seq_size], flow_mode);
426 set_cipher_mode(&desc[*seq_size], cipher_mode);
427 if (cipher_mode == DRV_CIPHER_CTR ||
428 cipher_mode == DRV_CIPHER_OFB) {
429 set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);
431 set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE0);
437 hw_desc_init(&desc[*seq_size]);
438 set_cipher_mode(&desc[*seq_size], cipher_mode);
439 set_cipher_config0(&desc[*seq_size], direction);
440 if (flow_mode == S_DIN_to_AES) {
441 if (cc_is_hw_key(tfm)) {
442 set_hw_crypto_key(&desc[*seq_size],
443 ctx_p->hw.key1_slot);
445 set_din_type(&desc[*seq_size], DMA_DLLI,
446 key_dma_addr, ((key_len == 24) ?
450 set_key_size_aes(&desc[*seq_size], key_len);
453 set_din_type(&desc[*seq_size], DMA_DLLI, key_dma_addr,
455 set_key_size_des(&desc[*seq_size], key_len);
457 set_flow_mode(&desc[*seq_size], flow_mode);
458 set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);
462 case DRV_CIPHER_ESSIV:
463 case DRV_CIPHER_BITLOCKER:
465 hw_desc_init(&desc[*seq_size]);
466 set_cipher_mode(&desc[*seq_size], cipher_mode);
467 set_cipher_config0(&desc[*seq_size], direction);
468 if (cc_is_hw_key(tfm)) {
469 set_hw_crypto_key(&desc[*seq_size],
470 ctx_p->hw.key1_slot);
472 set_din_type(&desc[*seq_size], DMA_DLLI, key_dma_addr,
473 (key_len / 2), NS_BIT);
475 set_key_size_aes(&desc[*seq_size], (key_len / 2));
476 set_flow_mode(&desc[*seq_size], flow_mode);
477 set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);
481 hw_desc_init(&desc[*seq_size]);
482 set_cipher_mode(&desc[*seq_size], cipher_mode);
483 set_cipher_config0(&desc[*seq_size], direction);
484 if (cc_is_hw_key(tfm)) {
485 set_hw_crypto_key(&desc[*seq_size],
486 ctx_p->hw.key2_slot);
488 set_din_type(&desc[*seq_size], DMA_DLLI,
489 (key_dma_addr + (key_len / 2)),
490 (key_len / 2), NS_BIT);
492 set_xex_data_unit_size(&desc[*seq_size], du_size);
493 set_flow_mode(&desc[*seq_size], S_DIN_to_AES2);
494 set_key_size_aes(&desc[*seq_size], (key_len / 2));
495 set_setup_mode(&desc[*seq_size], SETUP_LOAD_XEX_KEY);
499 hw_desc_init(&desc[*seq_size]);
500 set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);
501 set_cipher_mode(&desc[*seq_size], cipher_mode);
502 set_cipher_config0(&desc[*seq_size], direction);
503 set_key_size_aes(&desc[*seq_size], (key_len / 2));
504 set_flow_mode(&desc[*seq_size], flow_mode);
505 set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr,
506 CC_AES_BLOCK_SIZE, NS_BIT);
510 dev_err(dev, "Unsupported cipher mode (%d)\n", cipher_mode);
514 static void cc_setup_cipher_data(struct crypto_tfm *tfm,
515 struct cipher_req_ctx *req_ctx,
516 struct scatterlist *dst,
517 struct scatterlist *src, unsigned int nbytes,
518 void *areq, struct cc_hw_desc desc[],
519 unsigned int *seq_size)
521 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
522 struct device *dev = drvdata_to_dev(ctx_p->drvdata);
523 unsigned int flow_mode = ctx_p->flow_mode;
525 switch (ctx_p->flow_mode) {
527 flow_mode = DIN_AES_DOUT;
530 flow_mode = DIN_DES_DOUT;
533 dev_err(dev, "invalid flow mode, flow_mode = %d\n", flow_mode);
537 if (req_ctx->dma_buf_type == CC_DMA_BUF_DLLI) {
538 dev_dbg(dev, " data params addr %pad length 0x%X\n",
539 &sg_dma_address(src), nbytes);
540 dev_dbg(dev, " data params addr %pad length 0x%X\n",
541 &sg_dma_address(dst), nbytes);
542 hw_desc_init(&desc[*seq_size]);
543 set_din_type(&desc[*seq_size], DMA_DLLI, sg_dma_address(src),
545 set_dout_dlli(&desc[*seq_size], sg_dma_address(dst),
546 nbytes, NS_BIT, (!areq ? 0 : 1));
548 set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);
550 set_flow_mode(&desc[*seq_size], flow_mode);
554 dev_dbg(dev, " bypass params addr %pad length 0x%X addr 0x%08X\n",
555 &req_ctx->mlli_params.mlli_dma_addr,
556 req_ctx->mlli_params.mlli_len,
557 (unsigned int)ctx_p->drvdata->mlli_sram_addr);
558 hw_desc_init(&desc[*seq_size]);
559 set_din_type(&desc[*seq_size], DMA_DLLI,
560 req_ctx->mlli_params.mlli_dma_addr,
561 req_ctx->mlli_params.mlli_len, NS_BIT);
562 set_dout_sram(&desc[*seq_size],
563 ctx_p->drvdata->mlli_sram_addr,
564 req_ctx->mlli_params.mlli_len);
565 set_flow_mode(&desc[*seq_size], BYPASS);
568 hw_desc_init(&desc[*seq_size]);
569 set_din_type(&desc[*seq_size], DMA_MLLI,
570 ctx_p->drvdata->mlli_sram_addr,
571 req_ctx->in_mlli_nents, NS_BIT);
572 if (req_ctx->out_nents == 0) {
573 dev_dbg(dev, " din/dout params addr 0x%08X addr 0x%08X\n",
574 (unsigned int)ctx_p->drvdata->mlli_sram_addr,
575 (unsigned int)ctx_p->drvdata->mlli_sram_addr);
576 set_dout_mlli(&desc[*seq_size],
577 ctx_p->drvdata->mlli_sram_addr,
578 req_ctx->in_mlli_nents, NS_BIT,
581 dev_dbg(dev, " din/dout params addr 0x%08X addr 0x%08X\n",
582 (unsigned int)ctx_p->drvdata->mlli_sram_addr,
583 (unsigned int)ctx_p->drvdata->mlli_sram_addr +
584 (u32)LLI_ENTRY_BYTE_SIZE * req_ctx->in_nents);
585 set_dout_mlli(&desc[*seq_size],
586 (ctx_p->drvdata->mlli_sram_addr +
587 (LLI_ENTRY_BYTE_SIZE *
588 req_ctx->in_mlli_nents)),
589 req_ctx->out_mlli_nents, NS_BIT,
593 set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);
595 set_flow_mode(&desc[*seq_size], flow_mode);
601 * Update a CTR-AES 128 bit counter
603 static void cc_update_ctr(u8 *ctr, unsigned int increment)
605 if (IS_ENABLED(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) ||
606 IS_ALIGNED((unsigned long)ctr, 8)) {
608 __be64 *high_be = (__be64 *)ctr;
609 __be64 *low_be = high_be + 1;
610 u64 orig_low = __be64_to_cpu(*low_be);
611 u64 new_low = orig_low + (u64)increment;
613 *low_be = __cpu_to_be64(new_low);
615 if (new_low < orig_low)
616 *high_be = __cpu_to_be64(__be64_to_cpu(*high_be) + 1);
618 u8 *pos = (ctr + AES_BLOCK_SIZE);
622 for (; increment; increment--)
623 for (size = AES_BLOCK_SIZE; size; size--) {
632 static void cc_cipher_complete(struct device *dev, void *cc_req, int err)
634 struct skcipher_request *req = (struct skcipher_request *)cc_req;
635 struct scatterlist *dst = req->dst;
636 struct scatterlist *src = req->src;
637 struct cipher_req_ctx *req_ctx = skcipher_request_ctx(req);
638 struct crypto_skcipher *sk_tfm = crypto_skcipher_reqtfm(req);
639 struct crypto_tfm *tfm = crypto_skcipher_tfm(sk_tfm);
640 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
641 unsigned int ivsize = crypto_skcipher_ivsize(sk_tfm);
644 cc_unmap_cipher_request(dev, req_ctx, ivsize, src, dst);
646 switch (ctx_p->cipher_mode) {
649 * The crypto API expects us to set the req->iv to the last
650 * ciphertext block. For encrypt, simply copy from the result.
651 * For decrypt, we must copy from a saved buffer since this
652 * could be an in-place decryption operation and the src is
653 * lost by this point.
655 if (req_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) {
656 memcpy(req->iv, req_ctx->backup_info, ivsize);
657 kzfree(req_ctx->backup_info);
659 len = req->cryptlen - ivsize;
660 scatterwalk_map_and_copy(req->iv, req->dst, len,
666 /* Compute the counter of the last block */
667 len = ALIGN(req->cryptlen, AES_BLOCK_SIZE) / AES_BLOCK_SIZE;
668 cc_update_ctr((u8 *)req->iv, len);
677 skcipher_request_complete(req, err);
680 static int cc_cipher_process(struct skcipher_request *req,
681 enum drv_crypto_direction direction)
683 struct crypto_skcipher *sk_tfm = crypto_skcipher_reqtfm(req);
684 struct crypto_tfm *tfm = crypto_skcipher_tfm(sk_tfm);
685 struct cipher_req_ctx *req_ctx = skcipher_request_ctx(req);
686 unsigned int ivsize = crypto_skcipher_ivsize(sk_tfm);
687 struct scatterlist *dst = req->dst;
688 struct scatterlist *src = req->src;
689 unsigned int nbytes = req->cryptlen;
691 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
692 struct device *dev = drvdata_to_dev(ctx_p->drvdata);
693 struct cc_hw_desc desc[MAX_ABLKCIPHER_SEQ_LEN];
694 struct cc_crypto_req cc_req = {};
696 unsigned int seq_len = 0;
697 gfp_t flags = cc_gfp_flags(&req->base);
699 dev_dbg(dev, "%s req=%p iv=%p nbytes=%d\n",
700 ((direction == DRV_CRYPTO_DIRECTION_ENCRYPT) ?
701 "Encrypt" : "Decrypt"), req, iv, nbytes);
703 /* STAT_PHASE_0: Init and sanity checks */
705 /* TODO: check data length according to mode */
706 if (validate_data_size(ctx_p, nbytes)) {
707 dev_err(dev, "Unsupported data size %d.\n", nbytes);
708 crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_BLOCK_LEN);
713 /* No data to process is valid */
718 /* The IV we are handed may be allocted from the stack so
719 * we must copy it to a DMAable buffer before use.
721 req_ctx->iv = kmemdup(iv, ivsize, flags);
727 /* Setup request structure */
728 cc_req.user_cb = (void *)cc_cipher_complete;
729 cc_req.user_arg = (void *)req;
731 /* Setup request context */
732 req_ctx->gen_ctx.op_type = direction;
734 /* STAT_PHASE_1: Map buffers */
736 rc = cc_map_cipher_request(ctx_p->drvdata, req_ctx, ivsize, nbytes,
737 req_ctx->iv, src, dst, flags);
739 dev_err(dev, "map_request() failed\n");
743 /* STAT_PHASE_2: Create sequence */
745 /* Setup processing */
746 cc_setup_cipher_desc(tfm, req_ctx, ivsize, nbytes, desc, &seq_len);
747 /* Data processing */
748 cc_setup_cipher_data(tfm, req_ctx, dst, src, nbytes, req, desc,
751 /* STAT_PHASE_3: Lock HW and push sequence */
753 rc = cc_send_request(ctx_p->drvdata, &cc_req, desc, seq_len,
755 if (rc != -EINPROGRESS && rc != -EBUSY) {
756 /* Failed to send the request or request completed
759 cc_unmap_cipher_request(dev, req_ctx, ivsize, src, dst);
763 if (rc != -EINPROGRESS && rc != -EBUSY) {
764 kzfree(req_ctx->backup_info);
771 static int cc_cipher_encrypt(struct skcipher_request *req)
773 struct cipher_req_ctx *req_ctx = skcipher_request_ctx(req);
775 memset(req_ctx, 0, sizeof(*req_ctx));
777 return cc_cipher_process(req, DRV_CRYPTO_DIRECTION_ENCRYPT);
780 static int cc_cipher_decrypt(struct skcipher_request *req)
782 struct crypto_skcipher *sk_tfm = crypto_skcipher_reqtfm(req);
783 struct crypto_tfm *tfm = crypto_skcipher_tfm(sk_tfm);
784 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
785 struct cipher_req_ctx *req_ctx = skcipher_request_ctx(req);
786 unsigned int ivsize = crypto_skcipher_ivsize(sk_tfm);
787 gfp_t flags = cc_gfp_flags(&req->base);
790 memset(req_ctx, 0, sizeof(*req_ctx));
792 if ((ctx_p->cipher_mode == DRV_CIPHER_CBC) &&
793 (req->cryptlen >= ivsize)) {
795 /* Allocate and save the last IV sized bytes of the source,
796 * which will be lost in case of in-place decryption.
798 req_ctx->backup_info = kzalloc(ivsize, flags);
799 if (!req_ctx->backup_info)
802 len = req->cryptlen - ivsize;
803 scatterwalk_map_and_copy(req_ctx->backup_info, req->src, len,
807 return cc_cipher_process(req, DRV_CRYPTO_DIRECTION_DECRYPT);
810 /* Block cipher alg */
811 static const struct cc_alg_template skcipher_algs[] = {
814 .driver_name = "xts-paes-ccree",
815 .blocksize = AES_BLOCK_SIZE,
816 .template_skcipher = {
817 .setkey = cc_cipher_sethkey,
818 .encrypt = cc_cipher_encrypt,
819 .decrypt = cc_cipher_decrypt,
820 .min_keysize = CC_HW_KEY_SIZE,
821 .max_keysize = CC_HW_KEY_SIZE,
822 .ivsize = AES_BLOCK_SIZE,
824 .cipher_mode = DRV_CIPHER_XTS,
825 .flow_mode = S_DIN_to_AES,
826 .min_hw_rev = CC_HW_REV_630,
829 .name = "xts512(paes)",
830 .driver_name = "xts-paes-du512-ccree",
831 .blocksize = AES_BLOCK_SIZE,
832 .template_skcipher = {
833 .setkey = cc_cipher_sethkey,
834 .encrypt = cc_cipher_encrypt,
835 .decrypt = cc_cipher_decrypt,
836 .min_keysize = CC_HW_KEY_SIZE,
837 .max_keysize = CC_HW_KEY_SIZE,
838 .ivsize = AES_BLOCK_SIZE,
840 .cipher_mode = DRV_CIPHER_XTS,
841 .flow_mode = S_DIN_to_AES,
843 .min_hw_rev = CC_HW_REV_712,
846 .name = "xts4096(paes)",
847 .driver_name = "xts-paes-du4096-ccree",
848 .blocksize = AES_BLOCK_SIZE,
849 .template_skcipher = {
850 .setkey = cc_cipher_sethkey,
851 .encrypt = cc_cipher_encrypt,
852 .decrypt = cc_cipher_decrypt,
853 .min_keysize = CC_HW_KEY_SIZE,
854 .max_keysize = CC_HW_KEY_SIZE,
855 .ivsize = AES_BLOCK_SIZE,
857 .cipher_mode = DRV_CIPHER_XTS,
858 .flow_mode = S_DIN_to_AES,
860 .min_hw_rev = CC_HW_REV_712,
863 .name = "essiv(paes)",
864 .driver_name = "essiv-paes-ccree",
865 .blocksize = AES_BLOCK_SIZE,
866 .template_skcipher = {
867 .setkey = cc_cipher_sethkey,
868 .encrypt = cc_cipher_encrypt,
869 .decrypt = cc_cipher_decrypt,
870 .min_keysize = CC_HW_KEY_SIZE,
871 .max_keysize = CC_HW_KEY_SIZE,
872 .ivsize = AES_BLOCK_SIZE,
874 .cipher_mode = DRV_CIPHER_ESSIV,
875 .flow_mode = S_DIN_to_AES,
876 .min_hw_rev = CC_HW_REV_712,
879 .name = "essiv512(paes)",
880 .driver_name = "essiv-paes-du512-ccree",
881 .blocksize = AES_BLOCK_SIZE,
882 .template_skcipher = {
883 .setkey = cc_cipher_sethkey,
884 .encrypt = cc_cipher_encrypt,
885 .decrypt = cc_cipher_decrypt,
886 .min_keysize = CC_HW_KEY_SIZE,
887 .max_keysize = CC_HW_KEY_SIZE,
888 .ivsize = AES_BLOCK_SIZE,
890 .cipher_mode = DRV_CIPHER_ESSIV,
891 .flow_mode = S_DIN_to_AES,
893 .min_hw_rev = CC_HW_REV_712,
896 .name = "essiv4096(paes)",
897 .driver_name = "essiv-paes-du4096-ccree",
898 .blocksize = AES_BLOCK_SIZE,
899 .template_skcipher = {
900 .setkey = cc_cipher_sethkey,
901 .encrypt = cc_cipher_encrypt,
902 .decrypt = cc_cipher_decrypt,
903 .min_keysize = CC_HW_KEY_SIZE,
904 .max_keysize = CC_HW_KEY_SIZE,
905 .ivsize = AES_BLOCK_SIZE,
907 .cipher_mode = DRV_CIPHER_ESSIV,
908 .flow_mode = S_DIN_to_AES,
910 .min_hw_rev = CC_HW_REV_712,
913 .name = "bitlocker(paes)",
914 .driver_name = "bitlocker-paes-ccree",
915 .blocksize = AES_BLOCK_SIZE,
916 .template_skcipher = {
917 .setkey = cc_cipher_sethkey,
918 .encrypt = cc_cipher_encrypt,
919 .decrypt = cc_cipher_decrypt,
920 .min_keysize = CC_HW_KEY_SIZE,
921 .max_keysize = CC_HW_KEY_SIZE,
922 .ivsize = AES_BLOCK_SIZE,
924 .cipher_mode = DRV_CIPHER_BITLOCKER,
925 .flow_mode = S_DIN_to_AES,
926 .min_hw_rev = CC_HW_REV_712,
929 .name = "bitlocker512(paes)",
930 .driver_name = "bitlocker-paes-du512-ccree",
931 .blocksize = AES_BLOCK_SIZE,
932 .template_skcipher = {
933 .setkey = cc_cipher_sethkey,
934 .encrypt = cc_cipher_encrypt,
935 .decrypt = cc_cipher_decrypt,
936 .min_keysize = CC_HW_KEY_SIZE,
937 .max_keysize = CC_HW_KEY_SIZE,
938 .ivsize = AES_BLOCK_SIZE,
940 .cipher_mode = DRV_CIPHER_BITLOCKER,
941 .flow_mode = S_DIN_to_AES,
943 .min_hw_rev = CC_HW_REV_712,
946 .name = "bitlocker4096(paes)",
947 .driver_name = "bitlocker-paes-du4096-ccree",
948 .blocksize = AES_BLOCK_SIZE,
949 .template_skcipher = {
950 .setkey = cc_cipher_sethkey,
951 .encrypt = cc_cipher_encrypt,
952 .decrypt = cc_cipher_decrypt,
953 .min_keysize = CC_HW_KEY_SIZE,
954 .max_keysize = CC_HW_KEY_SIZE,
955 .ivsize = AES_BLOCK_SIZE,
957 .cipher_mode = DRV_CIPHER_BITLOCKER,
958 .flow_mode = S_DIN_to_AES,
960 .min_hw_rev = CC_HW_REV_712,
964 .driver_name = "ecb-paes-ccree",
965 .blocksize = AES_BLOCK_SIZE,
966 .template_skcipher = {
967 .setkey = cc_cipher_sethkey,
968 .encrypt = cc_cipher_encrypt,
969 .decrypt = cc_cipher_decrypt,
970 .min_keysize = CC_HW_KEY_SIZE,
971 .max_keysize = CC_HW_KEY_SIZE,
974 .cipher_mode = DRV_CIPHER_ECB,
975 .flow_mode = S_DIN_to_AES,
976 .min_hw_rev = CC_HW_REV_712,
980 .driver_name = "cbc-paes-ccree",
981 .blocksize = AES_BLOCK_SIZE,
982 .template_skcipher = {
983 .setkey = cc_cipher_sethkey,
984 .encrypt = cc_cipher_encrypt,
985 .decrypt = cc_cipher_decrypt,
986 .min_keysize = CC_HW_KEY_SIZE,
987 .max_keysize = CC_HW_KEY_SIZE,
988 .ivsize = AES_BLOCK_SIZE,
990 .cipher_mode = DRV_CIPHER_CBC,
991 .flow_mode = S_DIN_to_AES,
992 .min_hw_rev = CC_HW_REV_712,
996 .driver_name = "ofb-paes-ccree",
997 .blocksize = AES_BLOCK_SIZE,
998 .template_skcipher = {
999 .setkey = cc_cipher_sethkey,
1000 .encrypt = cc_cipher_encrypt,
1001 .decrypt = cc_cipher_decrypt,
1002 .min_keysize = CC_HW_KEY_SIZE,
1003 .max_keysize = CC_HW_KEY_SIZE,
1004 .ivsize = AES_BLOCK_SIZE,
1006 .cipher_mode = DRV_CIPHER_OFB,
1007 .flow_mode = S_DIN_to_AES,
1008 .min_hw_rev = CC_HW_REV_712,
1011 .name = "cts(cbc(paes))",
1012 .driver_name = "cts-cbc-paes-ccree",
1013 .blocksize = AES_BLOCK_SIZE,
1014 .template_skcipher = {
1015 .setkey = cc_cipher_sethkey,
1016 .encrypt = cc_cipher_encrypt,
1017 .decrypt = cc_cipher_decrypt,
1018 .min_keysize = CC_HW_KEY_SIZE,
1019 .max_keysize = CC_HW_KEY_SIZE,
1020 .ivsize = AES_BLOCK_SIZE,
1022 .cipher_mode = DRV_CIPHER_CBC_CTS,
1023 .flow_mode = S_DIN_to_AES,
1024 .min_hw_rev = CC_HW_REV_712,
1027 .name = "ctr(paes)",
1028 .driver_name = "ctr-paes-ccree",
1030 .template_skcipher = {
1031 .setkey = cc_cipher_sethkey,
1032 .encrypt = cc_cipher_encrypt,
1033 .decrypt = cc_cipher_decrypt,
1034 .min_keysize = CC_HW_KEY_SIZE,
1035 .max_keysize = CC_HW_KEY_SIZE,
1036 .ivsize = AES_BLOCK_SIZE,
1038 .cipher_mode = DRV_CIPHER_CTR,
1039 .flow_mode = S_DIN_to_AES,
1040 .min_hw_rev = CC_HW_REV_712,
1044 .driver_name = "xts-aes-ccree",
1045 .blocksize = AES_BLOCK_SIZE,
1046 .template_skcipher = {
1047 .setkey = cc_cipher_setkey,
1048 .encrypt = cc_cipher_encrypt,
1049 .decrypt = cc_cipher_decrypt,
1050 .min_keysize = AES_MIN_KEY_SIZE * 2,
1051 .max_keysize = AES_MAX_KEY_SIZE * 2,
1052 .ivsize = AES_BLOCK_SIZE,
1054 .cipher_mode = DRV_CIPHER_XTS,
1055 .flow_mode = S_DIN_to_AES,
1056 .min_hw_rev = CC_HW_REV_630,
1059 .name = "xts512(aes)",
1060 .driver_name = "xts-aes-du512-ccree",
1061 .blocksize = AES_BLOCK_SIZE,
1062 .template_skcipher = {
1063 .setkey = cc_cipher_setkey,
1064 .encrypt = cc_cipher_encrypt,
1065 .decrypt = cc_cipher_decrypt,
1066 .min_keysize = AES_MIN_KEY_SIZE * 2,
1067 .max_keysize = AES_MAX_KEY_SIZE * 2,
1068 .ivsize = AES_BLOCK_SIZE,
1070 .cipher_mode = DRV_CIPHER_XTS,
1071 .flow_mode = S_DIN_to_AES,
1073 .min_hw_rev = CC_HW_REV_712,
1076 .name = "xts4096(aes)",
1077 .driver_name = "xts-aes-du4096-ccree",
1078 .blocksize = AES_BLOCK_SIZE,
1079 .template_skcipher = {
1080 .setkey = cc_cipher_setkey,
1081 .encrypt = cc_cipher_encrypt,
1082 .decrypt = cc_cipher_decrypt,
1083 .min_keysize = AES_MIN_KEY_SIZE * 2,
1084 .max_keysize = AES_MAX_KEY_SIZE * 2,
1085 .ivsize = AES_BLOCK_SIZE,
1087 .cipher_mode = DRV_CIPHER_XTS,
1088 .flow_mode = S_DIN_to_AES,
1090 .min_hw_rev = CC_HW_REV_712,
1093 .name = "essiv(aes)",
1094 .driver_name = "essiv-aes-ccree",
1095 .blocksize = AES_BLOCK_SIZE,
1096 .template_skcipher = {
1097 .setkey = cc_cipher_setkey,
1098 .encrypt = cc_cipher_encrypt,
1099 .decrypt = cc_cipher_decrypt,
1100 .min_keysize = AES_MIN_KEY_SIZE * 2,
1101 .max_keysize = AES_MAX_KEY_SIZE * 2,
1102 .ivsize = AES_BLOCK_SIZE,
1104 .cipher_mode = DRV_CIPHER_ESSIV,
1105 .flow_mode = S_DIN_to_AES,
1106 .min_hw_rev = CC_HW_REV_712,
1109 .name = "essiv512(aes)",
1110 .driver_name = "essiv-aes-du512-ccree",
1111 .blocksize = AES_BLOCK_SIZE,
1112 .template_skcipher = {
1113 .setkey = cc_cipher_setkey,
1114 .encrypt = cc_cipher_encrypt,
1115 .decrypt = cc_cipher_decrypt,
1116 .min_keysize = AES_MIN_KEY_SIZE * 2,
1117 .max_keysize = AES_MAX_KEY_SIZE * 2,
1118 .ivsize = AES_BLOCK_SIZE,
1120 .cipher_mode = DRV_CIPHER_ESSIV,
1121 .flow_mode = S_DIN_to_AES,
1123 .min_hw_rev = CC_HW_REV_712,
1126 .name = "essiv4096(aes)",
1127 .driver_name = "essiv-aes-du4096-ccree",
1128 .blocksize = AES_BLOCK_SIZE,
1129 .template_skcipher = {
1130 .setkey = cc_cipher_setkey,
1131 .encrypt = cc_cipher_encrypt,
1132 .decrypt = cc_cipher_decrypt,
1133 .min_keysize = AES_MIN_KEY_SIZE * 2,
1134 .max_keysize = AES_MAX_KEY_SIZE * 2,
1135 .ivsize = AES_BLOCK_SIZE,
1137 .cipher_mode = DRV_CIPHER_ESSIV,
1138 .flow_mode = S_DIN_to_AES,
1140 .min_hw_rev = CC_HW_REV_712,
1143 .name = "bitlocker(aes)",
1144 .driver_name = "bitlocker-aes-ccree",
1145 .blocksize = AES_BLOCK_SIZE,
1146 .template_skcipher = {
1147 .setkey = cc_cipher_setkey,
1148 .encrypt = cc_cipher_encrypt,
1149 .decrypt = cc_cipher_decrypt,
1150 .min_keysize = AES_MIN_KEY_SIZE * 2,
1151 .max_keysize = AES_MAX_KEY_SIZE * 2,
1152 .ivsize = AES_BLOCK_SIZE,
1154 .cipher_mode = DRV_CIPHER_BITLOCKER,
1155 .flow_mode = S_DIN_to_AES,
1156 .min_hw_rev = CC_HW_REV_712,
1159 .name = "bitlocker512(aes)",
1160 .driver_name = "bitlocker-aes-du512-ccree",
1161 .blocksize = AES_BLOCK_SIZE,
1162 .template_skcipher = {
1163 .setkey = cc_cipher_setkey,
1164 .encrypt = cc_cipher_encrypt,
1165 .decrypt = cc_cipher_decrypt,
1166 .min_keysize = AES_MIN_KEY_SIZE * 2,
1167 .max_keysize = AES_MAX_KEY_SIZE * 2,
1168 .ivsize = AES_BLOCK_SIZE,
1170 .cipher_mode = DRV_CIPHER_BITLOCKER,
1171 .flow_mode = S_DIN_to_AES,
1173 .min_hw_rev = CC_HW_REV_712,
1176 .name = "bitlocker4096(aes)",
1177 .driver_name = "bitlocker-aes-du4096-ccree",
1178 .blocksize = AES_BLOCK_SIZE,
1179 .template_skcipher = {
1180 .setkey = cc_cipher_setkey,
1181 .encrypt = cc_cipher_encrypt,
1182 .decrypt = cc_cipher_decrypt,
1183 .min_keysize = AES_MIN_KEY_SIZE * 2,
1184 .max_keysize = AES_MAX_KEY_SIZE * 2,
1185 .ivsize = AES_BLOCK_SIZE,
1187 .cipher_mode = DRV_CIPHER_BITLOCKER,
1188 .flow_mode = S_DIN_to_AES,
1190 .min_hw_rev = CC_HW_REV_712,
1194 .driver_name = "ecb-aes-ccree",
1195 .blocksize = AES_BLOCK_SIZE,
1196 .template_skcipher = {
1197 .setkey = cc_cipher_setkey,
1198 .encrypt = cc_cipher_encrypt,
1199 .decrypt = cc_cipher_decrypt,
1200 .min_keysize = AES_MIN_KEY_SIZE,
1201 .max_keysize = AES_MAX_KEY_SIZE,
1204 .cipher_mode = DRV_CIPHER_ECB,
1205 .flow_mode = S_DIN_to_AES,
1206 .min_hw_rev = CC_HW_REV_630,
1210 .driver_name = "cbc-aes-ccree",
1211 .blocksize = AES_BLOCK_SIZE,
1212 .template_skcipher = {
1213 .setkey = cc_cipher_setkey,
1214 .encrypt = cc_cipher_encrypt,
1215 .decrypt = cc_cipher_decrypt,
1216 .min_keysize = AES_MIN_KEY_SIZE,
1217 .max_keysize = AES_MAX_KEY_SIZE,
1218 .ivsize = AES_BLOCK_SIZE,
1220 .cipher_mode = DRV_CIPHER_CBC,
1221 .flow_mode = S_DIN_to_AES,
1222 .min_hw_rev = CC_HW_REV_630,
1226 .driver_name = "ofb-aes-ccree",
1227 .blocksize = AES_BLOCK_SIZE,
1228 .template_skcipher = {
1229 .setkey = cc_cipher_setkey,
1230 .encrypt = cc_cipher_encrypt,
1231 .decrypt = cc_cipher_decrypt,
1232 .min_keysize = AES_MIN_KEY_SIZE,
1233 .max_keysize = AES_MAX_KEY_SIZE,
1234 .ivsize = AES_BLOCK_SIZE,
1236 .cipher_mode = DRV_CIPHER_OFB,
1237 .flow_mode = S_DIN_to_AES,
1238 .min_hw_rev = CC_HW_REV_630,
1241 .name = "cts(cbc(aes))",
1242 .driver_name = "cts-cbc-aes-ccree",
1243 .blocksize = AES_BLOCK_SIZE,
1244 .template_skcipher = {
1245 .setkey = cc_cipher_setkey,
1246 .encrypt = cc_cipher_encrypt,
1247 .decrypt = cc_cipher_decrypt,
1248 .min_keysize = AES_MIN_KEY_SIZE,
1249 .max_keysize = AES_MAX_KEY_SIZE,
1250 .ivsize = AES_BLOCK_SIZE,
1252 .cipher_mode = DRV_CIPHER_CBC_CTS,
1253 .flow_mode = S_DIN_to_AES,
1254 .min_hw_rev = CC_HW_REV_630,
1258 .driver_name = "ctr-aes-ccree",
1260 .template_skcipher = {
1261 .setkey = cc_cipher_setkey,
1262 .encrypt = cc_cipher_encrypt,
1263 .decrypt = cc_cipher_decrypt,
1264 .min_keysize = AES_MIN_KEY_SIZE,
1265 .max_keysize = AES_MAX_KEY_SIZE,
1266 .ivsize = AES_BLOCK_SIZE,
1268 .cipher_mode = DRV_CIPHER_CTR,
1269 .flow_mode = S_DIN_to_AES,
1270 .min_hw_rev = CC_HW_REV_630,
1273 .name = "cbc(des3_ede)",
1274 .driver_name = "cbc-3des-ccree",
1275 .blocksize = DES3_EDE_BLOCK_SIZE,
1276 .template_skcipher = {
1277 .setkey = cc_cipher_setkey,
1278 .encrypt = cc_cipher_encrypt,
1279 .decrypt = cc_cipher_decrypt,
1280 .min_keysize = DES3_EDE_KEY_SIZE,
1281 .max_keysize = DES3_EDE_KEY_SIZE,
1282 .ivsize = DES3_EDE_BLOCK_SIZE,
1284 .cipher_mode = DRV_CIPHER_CBC,
1285 .flow_mode = S_DIN_to_DES,
1286 .min_hw_rev = CC_HW_REV_630,
1289 .name = "ecb(des3_ede)",
1290 .driver_name = "ecb-3des-ccree",
1291 .blocksize = DES3_EDE_BLOCK_SIZE,
1292 .template_skcipher = {
1293 .setkey = cc_cipher_setkey,
1294 .encrypt = cc_cipher_encrypt,
1295 .decrypt = cc_cipher_decrypt,
1296 .min_keysize = DES3_EDE_KEY_SIZE,
1297 .max_keysize = DES3_EDE_KEY_SIZE,
1300 .cipher_mode = DRV_CIPHER_ECB,
1301 .flow_mode = S_DIN_to_DES,
1302 .min_hw_rev = CC_HW_REV_630,
1306 .driver_name = "cbc-des-ccree",
1307 .blocksize = DES_BLOCK_SIZE,
1308 .template_skcipher = {
1309 .setkey = cc_cipher_setkey,
1310 .encrypt = cc_cipher_encrypt,
1311 .decrypt = cc_cipher_decrypt,
1312 .min_keysize = DES_KEY_SIZE,
1313 .max_keysize = DES_KEY_SIZE,
1314 .ivsize = DES_BLOCK_SIZE,
1316 .cipher_mode = DRV_CIPHER_CBC,
1317 .flow_mode = S_DIN_to_DES,
1318 .min_hw_rev = CC_HW_REV_630,
1322 .driver_name = "ecb-des-ccree",
1323 .blocksize = DES_BLOCK_SIZE,
1324 .template_skcipher = {
1325 .setkey = cc_cipher_setkey,
1326 .encrypt = cc_cipher_encrypt,
1327 .decrypt = cc_cipher_decrypt,
1328 .min_keysize = DES_KEY_SIZE,
1329 .max_keysize = DES_KEY_SIZE,
1332 .cipher_mode = DRV_CIPHER_ECB,
1333 .flow_mode = S_DIN_to_DES,
1334 .min_hw_rev = CC_HW_REV_630,
1338 static struct cc_crypto_alg *cc_create_alg(const struct cc_alg_template *tmpl,
1341 struct cc_crypto_alg *t_alg;
1342 struct skcipher_alg *alg;
1344 t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL);
1346 return ERR_PTR(-ENOMEM);
1348 alg = &t_alg->skcipher_alg;
1350 memcpy(alg, &tmpl->template_skcipher, sizeof(*alg));
1352 snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);
1353 snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
1355 alg->base.cra_module = THIS_MODULE;
1356 alg->base.cra_priority = CC_CRA_PRIO;
1357 alg->base.cra_blocksize = tmpl->blocksize;
1358 alg->base.cra_alignmask = 0;
1359 alg->base.cra_ctxsize = sizeof(struct cc_cipher_ctx);
1361 alg->base.cra_init = cc_cipher_init;
1362 alg->base.cra_exit = cc_cipher_exit;
1363 alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
1365 t_alg->cipher_mode = tmpl->cipher_mode;
1366 t_alg->flow_mode = tmpl->flow_mode;
1367 t_alg->data_unit = tmpl->data_unit;
1372 int cc_cipher_free(struct cc_drvdata *drvdata)
1374 struct cc_crypto_alg *t_alg, *n;
1375 struct cc_cipher_handle *cipher_handle = drvdata->cipher_handle;
1377 if (cipher_handle) {
1378 /* Remove registered algs */
1379 list_for_each_entry_safe(t_alg, n, &cipher_handle->alg_list,
1381 crypto_unregister_skcipher(&t_alg->skcipher_alg);
1382 list_del(&t_alg->entry);
1385 kfree(cipher_handle);
1386 drvdata->cipher_handle = NULL;
1391 int cc_cipher_alloc(struct cc_drvdata *drvdata)
1393 struct cc_cipher_handle *cipher_handle;
1394 struct cc_crypto_alg *t_alg;
1395 struct device *dev = drvdata_to_dev(drvdata);
1399 cipher_handle = kmalloc(sizeof(*cipher_handle), GFP_KERNEL);
1403 INIT_LIST_HEAD(&cipher_handle->alg_list);
1404 drvdata->cipher_handle = cipher_handle;
1407 dev_dbg(dev, "Number of algorithms = %zu\n",
1408 ARRAY_SIZE(skcipher_algs));
1409 for (alg = 0; alg < ARRAY_SIZE(skcipher_algs); alg++) {
1410 if (skcipher_algs[alg].min_hw_rev > drvdata->hw_rev)
1413 dev_dbg(dev, "creating %s\n", skcipher_algs[alg].driver_name);
1414 t_alg = cc_create_alg(&skcipher_algs[alg], dev);
1415 if (IS_ERR(t_alg)) {
1416 rc = PTR_ERR(t_alg);
1417 dev_err(dev, "%s alg allocation failed\n",
1418 skcipher_algs[alg].driver_name);
1421 t_alg->drvdata = drvdata;
1423 dev_dbg(dev, "registering %s\n",
1424 skcipher_algs[alg].driver_name);
1425 rc = crypto_register_skcipher(&t_alg->skcipher_alg);
1426 dev_dbg(dev, "%s alg registration rc = %x\n",
1427 t_alg->skcipher_alg.base.cra_driver_name, rc);
1429 dev_err(dev, "%s alg registration failed\n",
1430 t_alg->skcipher_alg.base.cra_driver_name);
1434 list_add_tail(&t_alg->entry,
1435 &cipher_handle->alg_list);
1436 dev_dbg(dev, "Registered %s\n",
1437 t_alg->skcipher_alg.base.cra_driver_name);
1443 cc_cipher_free(drvdata);