1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/delay.h>
4 #include "nitrox_dev.h"
5 #include "nitrox_csr.h"
6 #include "nitrox_hal.h"
9 #define MAX_CSR_RETRIES 10
12 * emu_enable_cores - Enable EMU cluster cores.
13 * @ndev: NITROX device
15 static void emu_enable_cores(struct nitrox_device *ndev)
17 union emu_se_enable emu_se;
18 union emu_ae_enable emu_ae;
21 /* AE cores 20 per cluster */
23 emu_ae.s.enable = 0xfffff;
25 /* SE cores 16 per cluster */
27 emu_se.s.enable = 0xffff;
29 /* enable per cluster cores */
30 for (i = 0; i < NR_CLUSTERS; i++) {
31 nitrox_write_csr(ndev, EMU_AE_ENABLEX(i), emu_ae.value);
32 nitrox_write_csr(ndev, EMU_SE_ENABLEX(i), emu_se.value);
37 * nitrox_config_emu_unit - configure EMU unit.
38 * @ndev: NITROX device
40 void nitrox_config_emu_unit(struct nitrox_device *ndev)
42 union emu_wd_int_ena_w1s emu_wd_int;
43 union emu_ge_int_ena_w1s emu_ge_int;
48 emu_enable_cores(ndev);
50 /* enable general error and watch dog interrupts */
52 emu_ge_int.s.se_ge = 0xffff;
53 emu_ge_int.s.ae_ge = 0xfffff;
55 emu_wd_int.s.se_wd = 1;
57 for (i = 0; i < NR_CLUSTERS; i++) {
58 offset = EMU_WD_INT_ENA_W1SX(i);
59 nitrox_write_csr(ndev, offset, emu_wd_int.value);
60 offset = EMU_GE_INT_ENA_W1SX(i);
61 nitrox_write_csr(ndev, offset, emu_ge_int.value);
65 static void reset_pkt_input_ring(struct nitrox_device *ndev, int ring)
67 union nps_pkt_in_instr_ctl pkt_in_ctl;
68 union nps_pkt_in_done_cnts pkt_in_cnts;
69 int max_retries = MAX_CSR_RETRIES;
72 /* step 1: disable the ring, clear enable bit */
73 offset = NPS_PKT_IN_INSTR_CTLX(ring);
74 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
76 nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
78 /* step 2: wait to clear [ENB] */
79 usleep_range(100, 150);
81 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
82 if (!pkt_in_ctl.s.enb)
85 } while (max_retries--);
87 /* step 3: clear done counts */
88 offset = NPS_PKT_IN_DONE_CNTSX(ring);
89 pkt_in_cnts.value = nitrox_read_csr(ndev, offset);
90 nitrox_write_csr(ndev, offset, pkt_in_cnts.value);
91 usleep_range(50, 100);
94 void enable_pkt_input_ring(struct nitrox_device *ndev, int ring)
96 union nps_pkt_in_instr_ctl pkt_in_ctl;
97 int max_retries = MAX_CSR_RETRIES;
100 /* 64-byte instruction size */
101 offset = NPS_PKT_IN_INSTR_CTLX(ring);
102 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
103 pkt_in_ctl.s.is64b = 1;
104 pkt_in_ctl.s.enb = 1;
105 nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
107 /* wait for set [ENB] */
109 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
110 if (pkt_in_ctl.s.enb)
113 } while (max_retries--);
117 * nitrox_config_pkt_input_rings - configure Packet Input Rings
118 * @ndev: NITROX device
120 void nitrox_config_pkt_input_rings(struct nitrox_device *ndev)
124 for (i = 0; i < ndev->nr_queues; i++) {
125 struct nitrox_cmdq *cmdq = &ndev->pkt_inq[i];
126 union nps_pkt_in_instr_rsize pkt_in_rsize;
127 union nps_pkt_in_instr_baoff_dbell pkt_in_dbell;
130 reset_pkt_input_ring(ndev, i);
134 * configure ring base address 16-byte aligned,
135 * size and interrupt threshold.
137 offset = NPS_PKT_IN_INSTR_BADDRX(i);
138 nitrox_write_csr(ndev, offset, cmdq->dma);
140 /* configure ring size */
141 offset = NPS_PKT_IN_INSTR_RSIZEX(i);
142 pkt_in_rsize.value = 0;
143 pkt_in_rsize.s.rsize = ndev->qlen;
144 nitrox_write_csr(ndev, offset, pkt_in_rsize.value);
146 /* set high threshold for pkt input ring interrupts */
147 offset = NPS_PKT_IN_INT_LEVELSX(i);
148 nitrox_write_csr(ndev, offset, 0xffffffff);
150 /* step 5: clear off door bell counts */
151 offset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(i);
152 pkt_in_dbell.value = 0;
153 pkt_in_dbell.s.dbell = 0xffffffff;
154 nitrox_write_csr(ndev, offset, pkt_in_dbell.value);
156 /* enable the ring */
157 enable_pkt_input_ring(ndev, i);
161 static void reset_pkt_solicit_port(struct nitrox_device *ndev, int port)
163 union nps_pkt_slc_ctl pkt_slc_ctl;
164 union nps_pkt_slc_cnts pkt_slc_cnts;
165 int max_retries = MAX_CSR_RETRIES;
168 /* step 1: disable slc port */
169 offset = NPS_PKT_SLC_CTLX(port);
170 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
171 pkt_slc_ctl.s.enb = 0;
172 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
175 usleep_range(100, 150);
176 /* wait to clear [ENB] */
178 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
179 if (!pkt_slc_ctl.s.enb)
182 } while (max_retries--);
184 /* step 3: clear slc counters */
185 offset = NPS_PKT_SLC_CNTSX(port);
186 pkt_slc_cnts.value = nitrox_read_csr(ndev, offset);
187 nitrox_write_csr(ndev, offset, pkt_slc_cnts.value);
188 usleep_range(50, 100);
191 void enable_pkt_solicit_port(struct nitrox_device *ndev, int port)
193 union nps_pkt_slc_ctl pkt_slc_ctl;
194 int max_retries = MAX_CSR_RETRIES;
197 offset = NPS_PKT_SLC_CTLX(port);
198 pkt_slc_ctl.value = 0;
199 pkt_slc_ctl.s.enb = 1;
201 * 8 trailing 0x00 bytes will be added
202 * to the end of the outgoing packet.
205 /* enable response header */
206 pkt_slc_ctl.s.rh = 1;
207 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
209 /* wait to set [ENB] */
211 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
212 if (pkt_slc_ctl.s.enb)
215 } while (max_retries--);
218 static void config_pkt_solicit_port(struct nitrox_device *ndev, int port)
220 union nps_pkt_slc_int_levels pkt_slc_int;
223 reset_pkt_solicit_port(ndev, port);
225 /* step 4: configure interrupt levels */
226 offset = NPS_PKT_SLC_INT_LEVELSX(port);
227 pkt_slc_int.value = 0;
228 /* time interrupt threshold */
229 pkt_slc_int.s.timet = 0x3fffff;
230 nitrox_write_csr(ndev, offset, pkt_slc_int.value);
232 /* enable the solicit port */
233 enable_pkt_solicit_port(ndev, port);
236 void nitrox_config_pkt_solicit_ports(struct nitrox_device *ndev)
240 for (i = 0; i < ndev->nr_queues; i++)
241 config_pkt_solicit_port(ndev, i);
245 * enable_nps_core_interrupts - enable NPS core interrutps
246 * @ndev: NITROX device.
248 * This includes NPS core interrupts.
250 static void enable_nps_core_interrupts(struct nitrox_device *ndev)
252 union nps_core_int_ena_w1s core_int;
254 /* NPS core interrutps */
256 core_int.s.host_wr_err = 1;
257 core_int.s.host_wr_timeout = 1;
258 core_int.s.exec_wr_timeout = 1;
259 core_int.s.npco_dma_malform = 1;
260 core_int.s.host_nps_wr_err = 1;
261 nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value);
264 void nitrox_config_nps_core_unit(struct nitrox_device *ndev)
266 union nps_core_gbl_vfcfg core_gbl_vfcfg;
268 /* endian control information */
269 nitrox_write_csr(ndev, NPS_CORE_CONTROL, 1ULL);
271 /* disable ILK interface */
272 core_gbl_vfcfg.value = 0;
273 core_gbl_vfcfg.s.ilk_disable = 1;
274 core_gbl_vfcfg.s.cfg = __NDEV_MODE_PF;
275 nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value);
277 /* enable nps core interrupts */
278 enable_nps_core_interrupts(ndev);
282 * enable_nps_pkt_interrupts - enable NPS packet interrutps
283 * @ndev: NITROX device.
285 * This includes NPS packet in and slc interrupts.
287 static void enable_nps_pkt_interrupts(struct nitrox_device *ndev)
289 /* NPS packet in ring interrupts */
290 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL));
291 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL));
292 nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL));
293 /* NPS packet slc port interrupts */
294 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL));
295 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL));
296 nitrox_write_csr(ndev, NPS_PKT_SLC_ERR_TYPE_ENA_W1S, (~0uLL));
299 void nitrox_config_nps_pkt_unit(struct nitrox_device *ndev)
301 /* config input and solicit ports */
302 nitrox_config_pkt_input_rings(ndev);
303 nitrox_config_pkt_solicit_ports(ndev);
305 /* enable nps packet interrupts */
306 enable_nps_pkt_interrupts(ndev);
309 static void reset_aqm_ring(struct nitrox_device *ndev, int ring)
311 union aqmq_en aqmq_en_reg;
312 union aqmq_activity_stat activity_stat;
313 union aqmq_cmp_cnt cmp_cnt;
314 int max_retries = MAX_CSR_RETRIES;
317 /* step 1: disable the queue */
318 offset = AQMQ_ENX(ring);
319 aqmq_en_reg.value = 0;
320 aqmq_en_reg.queue_enable = 0;
321 nitrox_write_csr(ndev, offset, aqmq_en_reg.value);
323 /* step 2: wait for AQMQ_ACTIVITY_STATX[QUEUE_ACTIVE] to clear */
324 usleep_range(100, 150);
325 offset = AQMQ_ACTIVITY_STATX(ring);
327 activity_stat.value = nitrox_read_csr(ndev, offset);
328 if (!activity_stat.queue_active)
331 } while (max_retries--);
333 /* step 3: clear commands completed count */
334 offset = AQMQ_CMP_CNTX(ring);
335 cmp_cnt.value = nitrox_read_csr(ndev, offset);
336 nitrox_write_csr(ndev, offset, cmp_cnt.value);
337 usleep_range(50, 100);
340 void enable_aqm_ring(struct nitrox_device *ndev, int ring)
342 union aqmq_en aqmq_en_reg;
345 offset = AQMQ_ENX(ring);
346 aqmq_en_reg.value = 0;
347 aqmq_en_reg.queue_enable = 1;
348 nitrox_write_csr(ndev, offset, aqmq_en_reg.value);
349 usleep_range(50, 100);
352 void nitrox_config_aqm_rings(struct nitrox_device *ndev)
356 for (ring = 0; ring < ndev->nr_queues; ring++) {
357 struct nitrox_cmdq *cmdq = ndev->aqmq[ring];
358 union aqmq_drbl drbl;
359 union aqmq_qsz qsize;
360 union aqmq_cmp_thr cmp_thr;
364 reset_aqm_ring(ndev, ring);
366 /* step 4: clear doorbell count of ring */
367 offset = AQMQ_DRBLX(ring);
369 drbl.dbell_count = 0xFFFFFFFF;
370 nitrox_write_csr(ndev, offset, drbl.value);
372 /* step 5: configure host ring details */
374 /* set host address for next command of ring */
375 offset = AQMQ_NXT_CMDX(ring);
376 nitrox_write_csr(ndev, offset, 0ULL);
378 /* set host address of ring base */
379 offset = AQMQ_BADRX(ring);
380 nitrox_write_csr(ndev, offset, cmdq->dma);
383 offset = AQMQ_QSZX(ring);
385 qsize.host_queue_size = ndev->qlen;
386 nitrox_write_csr(ndev, offset, qsize.value);
388 /* set command completion threshold */
389 offset = AQMQ_CMP_THRX(ring);
391 cmp_thr.commands_completed_threshold = 1;
392 nitrox_write_csr(ndev, offset, cmp_thr.value);
394 /* step 6: enable the queue */
395 enable_aqm_ring(ndev, ring);
399 static void enable_aqm_interrupts(struct nitrox_device *ndev)
401 /* clear interrupt enable bits */
402 nitrox_write_csr(ndev, AQM_DBELL_OVF_LO_ENA_W1S, (~0ULL));
403 nitrox_write_csr(ndev, AQM_DBELL_OVF_HI_ENA_W1S, (~0ULL));
404 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_LO_ENA_W1S, (~0ULL));
405 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_HI_ENA_W1S, (~0ULL));
406 nitrox_write_csr(ndev, AQM_EXEC_NA_LO_ENA_W1S, (~0ULL));
407 nitrox_write_csr(ndev, AQM_EXEC_NA_HI_ENA_W1S, (~0ULL));
408 nitrox_write_csr(ndev, AQM_EXEC_ERR_LO_ENA_W1S, (~0ULL));
409 nitrox_write_csr(ndev, AQM_EXEC_ERR_HI_ENA_W1S, (~0ULL));
412 void nitrox_config_aqm_unit(struct nitrox_device *ndev)
414 /* config aqm command queues */
415 nitrox_config_aqm_rings(ndev);
417 /* enable aqm interrupts */
418 enable_aqm_interrupts(ndev);
421 void nitrox_config_pom_unit(struct nitrox_device *ndev)
423 union pom_int_ena_w1s pom_int;
426 /* enable pom interrupts */
428 pom_int.s.illegal_dport = 1;
429 nitrox_write_csr(ndev, POM_INT_ENA_W1S, pom_int.value);
431 /* enable perf counters */
432 for (i = 0; i < ndev->hw.se_cores; i++)
433 nitrox_write_csr(ndev, POM_PERF_CTL, BIT_ULL(i));
437 * nitrox_config_rand_unit - enable NITROX random number unit
438 * @ndev: NITROX device
440 void nitrox_config_rand_unit(struct nitrox_device *ndev)
442 union efl_rnm_ctl_status efl_rnm_ctl;
445 offset = EFL_RNM_CTL_STATUS;
446 efl_rnm_ctl.value = nitrox_read_csr(ndev, offset);
447 efl_rnm_ctl.s.ent_en = 1;
448 efl_rnm_ctl.s.rng_en = 1;
449 nitrox_write_csr(ndev, offset, efl_rnm_ctl.value);
452 void nitrox_config_efl_unit(struct nitrox_device *ndev)
456 for (i = 0; i < NR_CLUSTERS; i++) {
457 union efl_core_int_ena_w1s efl_core_int;
460 /* EFL core interrupts */
461 offset = EFL_CORE_INT_ENA_W1SX(i);
462 efl_core_int.value = 0;
463 efl_core_int.s.len_ovr = 1;
464 efl_core_int.s.d_left = 1;
465 efl_core_int.s.epci_decode_err = 1;
466 nitrox_write_csr(ndev, offset, efl_core_int.value);
468 offset = EFL_CORE_VF_ERR_INT0_ENA_W1SX(i);
469 nitrox_write_csr(ndev, offset, (~0ULL));
470 offset = EFL_CORE_VF_ERR_INT1_ENA_W1SX(i);
471 nitrox_write_csr(ndev, offset, (~0ULL));
475 void nitrox_config_bmi_unit(struct nitrox_device *ndev)
477 union bmi_ctl bmi_ctl;
478 union bmi_int_ena_w1s bmi_int_ena;
481 /* no threshold limits for PCIe */
483 bmi_ctl.value = nitrox_read_csr(ndev, offset);
484 bmi_ctl.s.max_pkt_len = 0xff;
485 bmi_ctl.s.nps_free_thrsh = 0xff;
486 bmi_ctl.s.nps_hdrq_thrsh = 0x7a;
487 nitrox_write_csr(ndev, offset, bmi_ctl.value);
489 /* enable interrupts */
490 offset = BMI_INT_ENA_W1S;
491 bmi_int_ena.value = 0;
492 bmi_int_ena.s.max_len_err_nps = 1;
493 bmi_int_ena.s.pkt_rcv_err_nps = 1;
494 bmi_int_ena.s.fpf_undrrn = 1;
495 nitrox_write_csr(ndev, offset, bmi_int_ena.value);
498 void nitrox_config_bmo_unit(struct nitrox_device *ndev)
500 union bmo_ctl2 bmo_ctl2;
503 /* no threshold limits for PCIe */
505 bmo_ctl2.value = nitrox_read_csr(ndev, offset);
506 bmo_ctl2.s.nps_slc_buf_thrsh = 0xff;
507 nitrox_write_csr(ndev, offset, bmo_ctl2.value);
510 void invalidate_lbc(struct nitrox_device *ndev)
512 union lbc_inval_ctl lbc_ctl;
513 union lbc_inval_status lbc_stat;
514 int max_retries = MAX_CSR_RETRIES;
518 offset = LBC_INVAL_CTL;
519 lbc_ctl.value = nitrox_read_csr(ndev, offset);
520 lbc_ctl.s.cam_inval_start = 1;
521 nitrox_write_csr(ndev, offset, lbc_ctl.value);
523 offset = LBC_INVAL_STATUS;
525 lbc_stat.value = nitrox_read_csr(ndev, offset);
529 } while (max_retries--);
532 void nitrox_config_lbc_unit(struct nitrox_device *ndev)
534 union lbc_int_ena_w1s lbc_int_ena;
537 invalidate_lbc(ndev);
539 /* enable interrupts */
540 offset = LBC_INT_ENA_W1S;
541 lbc_int_ena.value = 0;
542 lbc_int_ena.s.dma_rd_err = 1;
543 lbc_int_ena.s.over_fetch_err = 1;
544 lbc_int_ena.s.cam_inval_abort = 1;
545 lbc_int_ena.s.cam_hard_err = 1;
546 nitrox_write_csr(ndev, offset, lbc_int_ena.value);
548 offset = LBC_PLM_VF1_64_INT_ENA_W1S;
549 nitrox_write_csr(ndev, offset, (~0ULL));
550 offset = LBC_PLM_VF65_128_INT_ENA_W1S;
551 nitrox_write_csr(ndev, offset, (~0ULL));
553 offset = LBC_ELM_VF1_64_INT_ENA_W1S;
554 nitrox_write_csr(ndev, offset, (~0ULL));
555 offset = LBC_ELM_VF65_128_INT_ENA_W1S;
556 nitrox_write_csr(ndev, offset, (~0ULL));
559 void config_nps_core_vfcfg_mode(struct nitrox_device *ndev, enum vf_mode mode)
561 union nps_core_gbl_vfcfg vfcfg;
563 vfcfg.value = nitrox_read_csr(ndev, NPS_CORE_GBL_VFCFG);
564 vfcfg.s.cfg = mode & 0x7;
566 nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, vfcfg.value);
569 static const char *get_core_option(u8 se_cores, u8 ae_cores)
571 const char *option = "";
573 if (ae_cores == AE_MAX_CORES) {
582 } else if (ae_cores == (AE_MAX_CORES / 2)) {
591 static const char *get_feature_option(u8 zip_cores, int core_freq)
595 else if (zip_cores < ZIP_MAX_CORES)
598 if (core_freq >= 850)
600 else if (core_freq >= 750)
602 else if (core_freq >= 550)
608 void nitrox_get_hwinfo(struct nitrox_device *ndev)
610 union emu_fuse_map emu_fuse;
611 union rst_boot rst_boot;
612 union fus_dat1 fus_dat1;
613 unsigned char name[IFNAMSIZ * 2] = {};
617 /* get core frequency */
619 rst_boot.value = nitrox_read_csr(ndev, offset);
620 ndev->hw.freq = (rst_boot.pnr_mul + 3) * PLL_REF_CLK;
622 for (i = 0; i < NR_CLUSTERS; i++) {
623 offset = EMU_FUSE_MAPX(i);
624 emu_fuse.value = nitrox_read_csr(ndev, offset);
625 if (emu_fuse.s.valid) {
626 dead_cores = hweight32(emu_fuse.s.ae_fuse);
627 ndev->hw.ae_cores += AE_CORES_PER_CLUSTER - dead_cores;
628 dead_cores = hweight16(emu_fuse.s.se_fuse);
629 ndev->hw.se_cores += SE_CORES_PER_CLUSTER - dead_cores;
632 /* find zip hardware availability */
634 fus_dat1.value = nitrox_read_csr(ndev, offset);
635 if (!fus_dat1.nozip) {
636 dead_cores = hweight8(fus_dat1.zip_info);
637 ndev->hw.zip_cores = ZIP_MAX_CORES - dead_cores;
640 /* determine the partname
641 * CNN55<core option>-<freq><pincount>-<feature option>-<rev>
643 snprintf(name, sizeof(name), "CNN55%s-%3dBG676%s-1.%u",
644 get_core_option(ndev->hw.se_cores, ndev->hw.ae_cores),
646 get_feature_option(ndev->hw.zip_cores, ndev->hw.freq),
647 ndev->hw.revision_id);
650 strncpy(ndev->hw.partname, name, sizeof(ndev->hw.partname));
653 void enable_pf2vf_mbox_interrupts(struct nitrox_device *ndev)
658 /* Mailbox interrupt low enable set register */
659 reg_addr = NPS_PKT_MBOX_INT_LO_ENA_W1S;
660 nitrox_write_csr(ndev, reg_addr, value);
662 /* Mailbox interrupt high enable set register */
663 reg_addr = NPS_PKT_MBOX_INT_HI_ENA_W1S;
664 nitrox_write_csr(ndev, reg_addr, value);
667 void disable_pf2vf_mbox_interrupts(struct nitrox_device *ndev)
672 /* Mailbox interrupt low enable clear register */
673 reg_addr = NPS_PKT_MBOX_INT_LO_ENA_W1C;
674 nitrox_write_csr(ndev, reg_addr, value);
676 /* Mailbox interrupt high enable clear register */
677 reg_addr = NPS_PKT_MBOX_INT_HI_ENA_W1C;
678 nitrox_write_csr(ndev, reg_addr, value);