1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/dma-mapping.h>
6 #include <linux/interrupt.h>
10 #define VERSION_LEN 32
11 /* Maximum queues in PF mode */
12 #define MAX_PF_QUEUES 64
13 /* Maximum device queues */
14 #define MAX_DEV_QUEUES (MAX_PF_QUEUES)
15 /* Maximum UCD Blocks */
16 #define CNN55XX_MAX_UCD_BLOCKS 8
19 * struct nitrox_cmdq - NITROX command queue
20 * @cmd_qlock: command queue lock
21 * @resp_qlock: response queue lock
22 * @backlog_qlock: backlog queue lock
23 * @ndev: NITROX device
24 * @response_head: submitted request list
25 * @backlog_head: backlog queue
26 * @dbell_csr_addr: doorbell register address for this queue
27 * @compl_cnt_csr_addr: completion count register address of the slc port
28 * @base: command queue base address
29 * @dma: dma address of the base
30 * @pending_count: request pending at device
31 * @backlog_count: backlog request count
32 * @write_idx: next write index for the command
33 * @instr_size: command size
34 * @qno: command queue number
35 * @qsize: command queue size
36 * @unalign_base: unaligned base address
37 * @unalign_dma: unaligned dma address
41 spinlock_t resp_qlock;
42 spinlock_t backlog_qlock;
44 struct nitrox_device *ndev;
45 struct list_head response_head;
46 struct list_head backlog_head;
48 u8 __iomem *dbell_csr_addr;
49 u8 __iomem *compl_cnt_csr_addr;
53 struct work_struct backlog_qflush;
55 atomic_t pending_count;
56 atomic_t backlog_count;
64 dma_addr_t unalign_dma;
68 * struct nitrox_hw - NITROX hardware information
69 * @partname: partname ex: CNN55xxx-xxx
70 * @fw_name: firmware version
71 * @freq: NITROX frequency
72 * @vendor_id: vendor ID
73 * @device_id: device ID
74 * @revision_id: revision ID
75 * @se_cores: number of symmetric cores
76 * @ae_cores: number of asymmetric cores
77 * @zip_cores: number of zip cores
80 char partname[IFNAMSIZ * 2];
81 char fw_name[CNN55XX_MAX_UCD_BLOCKS][VERSION_LEN];
101 struct nitrox_q_vector {
102 char name[IRQ_NAMESZ];
105 struct tasklet_struct resp_tasklet;
107 struct nitrox_cmdq *cmdq;
108 struct nitrox_device *ndev;
120 * mbox_msg - Mailbox message data
121 * @type: message type
122 * @opcode: message opcode
123 * @data: message data
149 * nitrox_vfdev - NITROX VF device instance in PF
150 * @state: VF device state
152 * @nr_queues: number of queues enabled in VF
153 * @ring: ring to communicate with VF
154 * @msg: Mailbox message data from VF
155 * @mbx_resp: Mailbox counters
157 struct nitrox_vfdev {
167 * struct nitrox_iov - SR-IOV information
168 * @num_vfs: number of VF(s) enabled
169 * @max_vf_queues: Maximum number of queues allowed for VF
170 * @vfdev: VF(s) devices
171 * @pf2vf_wq: workqueue for PF2VF communication
172 * @msix: MSI-X entry for PF in SR-IOV case
177 struct nitrox_vfdev *vfdev;
178 struct workqueue_struct *pf2vf_wq;
179 struct msix_entry msix;
183 * NITROX Device states
191 /* NITROX support modes for VF(s) */
200 #define __NDEV_SRIOV_BIT 0
202 /* command queue size */
203 #define DEFAULT_CMD_QLEN 2048
204 /* command timeout in milliseconds */
205 #define CMD_TIMEOUT 2000
207 #define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev))
209 #define NITROX_CSR_ADDR(ndev, offset) \
210 ((ndev)->bar_addr + (offset))
213 * struct nitrox_device - NITROX Device Information.
214 * @list: pointer to linked list of devices
215 * @bar_addr: iomap address
216 * @pdev: PCI device information
217 * @state: NITROX device state
218 * @flags: flags to indicate device the features
219 * @timeout: Request timeout in jiffies
220 * @refcnt: Device usage count
221 * @idx: device index (0..N)
222 * @node: NUMA node id attached
223 * @qlen: Command queue length
224 * @nr_queues: Number of command queues
225 * @mode: Device mode PF/VF
226 * @ctx_pool: DMA pool for crypto context
227 * @pkt_inq: Packet input rings
228 * @aqmq: AQM command queues
229 * @qvec: MSI-X queue vectors information
230 * @iov: SR-IOV informatin
231 * @num_vecs: number of MSI-X vectors
232 * @stats: request statistics
233 * @hw: hardware information
234 * @debugfs_dir: debugfs directory
236 struct nitrox_device {
237 struct list_head list;
239 u8 __iomem *bar_addr;
240 struct pci_dev *pdev;
244 unsigned long timeout;
253 struct dma_pool *ctx_pool;
254 struct nitrox_cmdq *pkt_inq;
255 struct nitrox_cmdq *aqmq[MAX_DEV_QUEUES] ____cacheline_aligned_in_smp;
257 struct nitrox_q_vector *qvec;
258 struct nitrox_iov iov;
261 struct nitrox_stats stats;
263 #if IS_ENABLED(CONFIG_DEBUG_FS)
264 struct dentry *debugfs_dir;
269 * nitrox_read_csr - Read from device register
270 * @ndev: NITROX device
271 * @offset: offset of the register to read
273 * Returns: value read
275 static inline u64 nitrox_read_csr(struct nitrox_device *ndev, u64 offset)
277 return readq(ndev->bar_addr + offset);
281 * nitrox_write_csr - Write to device register
282 * @ndev: NITROX device
283 * @offset: offset of the register to write
284 * @value: value to write
286 static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset,
289 writeq(value, (ndev->bar_addr + offset));
292 static inline bool nitrox_ready(struct nitrox_device *ndev)
294 return atomic_read(&ndev->state) == __NDEV_READY;
297 static inline bool nitrox_vfdev_ready(struct nitrox_vfdev *vfdev)
299 return atomic_read(&vfdev->state) == __NDEV_READY;
302 #endif /* __NITROX_DEV_H */