1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2016 Cavium, Inc.
6 #ifndef __CPT_HW_TYPES_H
7 #define __CPT_HW_TYPES_H
9 #include "cpt_common.h"
12 * Enumeration cpt_comp_e
14 * CPT Completion Enumeration
15 * Enumerates the values of CPT_RES_S[COMPCODE].
18 CPT_COMP_E_NOTDONE = 0x00,
19 CPT_COMP_E_GOOD = 0x01,
20 CPT_COMP_E_FAULT = 0x02,
21 CPT_COMP_E_SWERR = 0x03,
22 CPT_COMP_E_LAST_ENTRY = 0xFF
26 * Structure cpt_inst_s
28 * CPT Instruction Structure
29 * This structure specifies the instruction layout. Instructions are
30 * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
33 * doneint:1 Done interrupt.
34 * 0 = No interrupts related to this instruction.
35 * 1 = When the instruction completes, CPT()_VQ()_DONE[DONE] will be
36 * incremented,and based on the rules described there an interrupt may
39 * res_addr [127: 64] Result IOVA.
40 * If nonzero, specifies where to write CPT_RES_S.
41 * If zero, no result structure will be written.
42 * Address must be 16-byte aligned.
43 * Bits <63:49> are ignored by hardware; software should use a
44 * sign-extended bit <48> for forward compatibility.
46 * grp:10 [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to use when
47 * CPT submits work SSO.
48 * For the SSO to not discard the add-work request, FPA_PF_MAP() must map
49 * [GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.
50 * tt:2 [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use when CPT
52 * tag:32 [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when CPT
53 * submits work to SSO.
55 * wq_ptr [255:192] If [WQ_PTR] is nonzero, it is a pointer to a
56 * work-queue entry that CPT submits work to SSO after all context,
57 * output data, and result write operations are visible to other
58 * CNXXXX units and the cores. Bits <2:0> must be zero.
59 * Bits <63:49> are ignored by hardware; software should
60 * use a sign-extended bit <48> for forward compatibility.
62 * Bits <63:49>, <2:0> are ignored by hardware, treated as always 0x0.
64 * ei0; [319:256] Engine instruction word 0. Passed to the AE/SE.
66 * ei1; [383:320] Engine instruction word 1. Passed to the AE/SE.
68 * ei2; [447:384] Engine instruction word 1. Passed to the AE/SE.
70 * ei3; [511:448] Engine instruction word 1. Passed to the AE/SE.
76 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
77 u64 reserved_17_63:47;
80 #else /* Word 0 - Little Endian */
83 u64 reserved_17_63:47;
84 #endif /* Word 0 - End */
86 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 2 - Big Endian */
87 u64 reserved_172_19:20;
91 #else /* Word 2 - Little Endian */
95 u64 reserved_172_191:20;
96 #endif /* Word 2 - End */
106 * Structure cpt_res_s
108 * CPT Result Structure
109 * The CPT coprocessor writes the result structure after it completes a
110 * CPT_INST_S instruction. The result structure is exactly 16 bytes, and
111 * each instruction completion produces exactly one result structure.
113 * This structure is stored in memory as little-endian unless
114 * CPT()_PF_Q()_CTL[INST_BE] is set.
117 * doneint:1 [16:16] Done interrupt. This bit is copied from the
118 * corresponding instruction's CPT_INST_S[DONEINT].
119 * compcode:8 [7:0] Indicates completion/error status of the CPT coprocessor
120 * for the associated instruction, as enumerated by CPT_COMP_E.
121 * Core software may write the memory location containing [COMPCODE] to
122 * 0x0 before ringing the doorbell, and then poll for completion by
123 * checking for a nonzero value.
124 * Once the core observes a nonzero [COMPCODE] value in this case,the CPT
125 * coprocessor will have also completed L2/DRAM write operations.
133 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
134 u64 reserved_17_63:47;
138 #else /* Word 0 - Little Endian */
142 u64 reserved_17_63:47;
143 #endif /* Word 0 - End */
149 * Register (NCB) cpt#_pf_bist_status
151 * CPT PF Control Bist Status Register
152 * This register has the BIST status of memories. Each bit is the BIST result
153 * of an individual memory (per bit, 0 = pass and 1 = fail).
154 * cptx_pf_bist_status_s
156 * bstatus [29:0](RO/H) BIST status. One bit per memory, enumerated by
159 union cptx_pf_bist_status {
161 struct cptx_pf_bist_status_s {
162 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
163 u64 reserved_30_63:34;
165 #else /* Word 0 - Little Endian */
167 u64 reserved_30_63:34;
168 #endif /* Word 0 - End */
173 * Register (NCB) cpt#_pf_constants
175 * CPT PF Constants Register
176 * This register contains implementation-related parameters of CPT in CNXXXX.
177 * cptx_pf_constants_s
179 * reserved_40_63:24 [63:40] Reserved.
180 * epcis:8 [39:32](RO) Number of EPCI busses.
181 * grps:8 [31:24](RO) Number of engine groups implemented.
182 * ae:8 [23:16](RO/H) Number of AEs. In CNXXXX, for CPT0 returns 0x0,
183 * for CPT1 returns 0x18, or less if there are fuse-disables.
184 * se:8 [15:8](RO/H) Number of SEs. In CNXXXX, for CPT0 returns 0x30,
185 * or less if there are fuse-disables, for CPT1 returns 0x0.
186 * vq:8 [7:0](RO) Number of VQs.
188 union cptx_pf_constants {
190 struct cptx_pf_constants_s {
191 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
192 u64 reserved_40_63:24;
198 #else /* Word 0 - Little Endian */
204 u64 reserved_40_63:24;
205 #endif /* Word 0 - End */
210 * Register (NCB) cpt#_pf_exe_bist_status
212 * CPT PF Engine Bist Status Register
213 * This register has the BIST status of each engine. Each bit is the
214 * BIST result of an individual engine (per bit, 0 = pass and 1 = fail).
215 * cptx_pf_exe_bist_status_s
217 * reserved_48_63:16 [63:48] reserved
218 * bstatus:48 [47:0](RO/H) BIST status. One bit per engine.
221 union cptx_pf_exe_bist_status {
223 struct cptx_pf_exe_bist_status_s {
224 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
225 u64 reserved_48_63:16;
227 #else /* Word 0 - Little Endian */
229 u64 reserved_48_63:16;
230 #endif /* Word 0 - End */
235 * Register (NCB) cpt#_pf_q#_ctl
237 * CPT Queue Control Register
238 * This register configures queues. This register should be changed only
239 * when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).
242 * reserved_60_63:4 [63:60] reserved.
243 * aura:12; [59:48](R/W) Guest-aura for returning this queue's
244 * instruction-chunk buffers to FPA. Only used when [INST_FREE] is set.
245 * For the FPA to not discard the request, FPA_PF_MAP() must map
246 * [AURA] and CPT()_PF_Q()_GMCTL[GMID] as valid.
247 * reserved_45_47:3 [47:45] reserved.
248 * size:13 [44:32](R/W) Command-buffer size, in number of 64-bit words per
249 * command buffer segment. Must be 8*n + 1, where n is the number of
250 * instructions per buffer segment.
251 * reserved_11_31:21 [31:11] Reserved.
252 * cont_err:1 [10:10](R/W) Continue on error.
253 * 0 = When CPT()_VQ()_MISC_INT[NWRP], CPT()_VQ()_MISC_INT[IRDE] or
254 * CPT()_VQ()_MISC_INT[DOVF] are set by hardware or software via
255 * CPT()_VQ()_MISC_INT_W1S, then CPT()_VQ()_CTL[ENA] is cleared. Due to
256 * pipelining, additional instructions may have been processed between the
257 * instruction causing the error and the next instruction in the disabled
258 * queue (the instruction at CPT()_VQ()_SADDR).
259 * 1 = Ignore errors and continue processing instructions.
260 * For diagnostic use only.
261 * inst_free:1 [9:9](R/W) Instruction FPA free. When set, when CPT reaches the
262 * end of an instruction chunk, that chunk will be freed to the FPA.
263 * inst_be:1 [8:8](R/W) Instruction big-endian control. When set, instructions,
264 * instruction next chunk pointers, and result structures are stored in
265 * big-endian format in memory.
266 * iqb_ldwb:1 [7:7](R/W) Instruction load don't write back.
267 * 0 = The hardware issues NCB transient load (LDT) towards the cache,
268 * which if the line hits and is is dirty will cause the line to be
269 * written back before being replaced.
270 * 1 = The hardware issues NCB LDWB read-and-invalidate command towards
271 * the cache when fetching the last word of instructions; as a result the
272 * line will not be written back when replaced. This improves
273 * performance, but software must not read the instructions after they are
274 * posted to the hardware. Reads that do not consume the last word of a
275 * cache line always use LDI.
276 * reserved_4_6:3 [6:4] Reserved.
277 * grp:3; [3:1](R/W) Engine group.
278 * pri:1; [0:0](R/W) Queue priority.
279 * 1 = This queue has higher priority. Round-robin between higher
281 * 0 = This queue has lower priority. Round-robin between lower
284 union cptx_pf_qx_ctl {
286 struct cptx_pf_qx_ctl_s {
287 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
288 u64 reserved_60_63:4;
290 u64 reserved_45_47:3;
292 u64 reserved_11_31:21;
300 #else /* Word 0 - Little Endian */
308 u64 reserved_11_31:21;
310 u64 reserved_45_47:3;
312 u64 reserved_60_63:4;
313 #endif /* Word 0 - End */
318 * Register (NCB) cpt#_vq#_saddr
320 * CPT Queue Starting Buffer Address Registers
321 * These registers set the instruction buffer starting address.
324 * reserved_49_63:15 [63:49] Reserved.
325 * ptr:43 [48:6](R/W/H) Instruction buffer IOVA <48:6> (64-byte aligned).
326 * When written, it is the initial buffer starting address; when read,
327 * it is the next read pointer to be requested from L2C. The PTR field
328 * is overwritten with the next pointer each time that the command buffer
329 * segment is exhausted. New commands will then be read from the newly
330 * specified command buffer pointer.
331 * reserved_0_5:6 [5:0] Reserved.
334 union cptx_vqx_saddr {
336 struct cptx_vqx_saddr_s {
337 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
338 u64 reserved_49_63:15;
341 #else /* Word 0 - Little Endian */
344 u64 reserved_49_63:15;
345 #endif /* Word 0 - End */
350 * Register (NCB) cpt#_vq#_misc_ena_w1s
352 * CPT Queue Misc Interrupt Enable Set Register
353 * This register sets interrupt enable bits.
354 * cptx_vqx_misc_ena_w1s_s
356 * reserved_5_63:59 [63:5] Reserved.
357 * swerr:1 [4:4](R/W1S/H) Reads or sets enable for
358 * CPT(0..1)_VQ(0..63)_MISC_INT[SWERR].
359 * nwrp:1 [3:3](R/W1S/H) Reads or sets enable for
360 * CPT(0..1)_VQ(0..63)_MISC_INT[NWRP].
361 * irde:1 [2:2](R/W1S/H) Reads or sets enable for
362 * CPT(0..1)_VQ(0..63)_MISC_INT[IRDE].
363 * dovf:1 [1:1](R/W1S/H) Reads or sets enable for
364 * CPT(0..1)_VQ(0..63)_MISC_INT[DOVF].
365 * mbox:1 [0:0](R/W1S/H) Reads or sets enable for
366 * CPT(0..1)_VQ(0..63)_MISC_INT[MBOX].
369 union cptx_vqx_misc_ena_w1s {
371 struct cptx_vqx_misc_ena_w1s_s {
372 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
373 u64 reserved_5_63:59;
379 #else /* Word 0 - Little Endian */
385 u64 reserved_5_63:59;
386 #endif /* Word 0 - End */
391 * Register (NCB) cpt#_vq#_doorbell
393 * CPT Queue Doorbell Registers
394 * Doorbells for the CPT instruction queues.
395 * cptx_vqx_doorbell_s
397 * reserved_20_63:44 [63:20] Reserved.
398 * dbell_cnt:20 [19:0](R/W/H) Number of instruction queue 64-bit words to add
399 * to the CPT instruction doorbell count. Readback value is the the
400 * current number of pending doorbell requests. If counter overflows
401 * CPT()_VQ()_MISC_INT[DBELL_DOVF] is set. To reset the count back to
402 * zero, write one to clear CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF],
403 * then write a value of 2^20 minus the read [DBELL_CNT], then write one
404 * to CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and
405 * CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF]. Must be a multiple of 8.
406 * All CPT instructions are 8 words and require a doorbell count of
409 union cptx_vqx_doorbell {
411 struct cptx_vqx_doorbell_s {
412 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
413 u64 reserved_20_63:44;
415 #else /* Word 0 - Little Endian */
417 u64 reserved_20_63:44;
418 #endif /* Word 0 - End */
423 * Register (NCB) cpt#_vq#_inprog
425 * CPT Queue In Progress Count Registers
426 * These registers contain the per-queue instruction in flight registers.
429 * reserved_8_63:56 [63:8] Reserved.
430 * inflight:8 [7:0](RO/H) Inflight count. Counts the number of instructions
431 * for the VF for which CPT is fetching, executing or responding to
432 * instructions. However this does not include any interrupts that are
433 * awaiting software handling (CPT()_VQ()_DONE[DONE] != 0x0).
434 * A queue may not be reconfigured until:
435 * 1. CPT()_VQ()_CTL[ENA] is cleared by software.
436 * 2. [INFLIGHT] is polled until equals to zero.
438 union cptx_vqx_inprog {
440 struct cptx_vqx_inprog_s {
441 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
442 u64 reserved_8_63:56;
444 #else /* Word 0 - Little Endian */
446 u64 reserved_8_63:56;
447 #endif /* Word 0 - End */
452 * Register (NCB) cpt#_vq#_misc_int
454 * CPT Queue Misc Interrupt Register
455 * These registers contain the per-queue miscellaneous interrupts.
456 * cptx_vqx_misc_int_s
458 * reserved_5_63:59 [63:5] Reserved.
459 * swerr:1 [4:4](R/W1C/H) Software error from engines.
460 * nwrp:1 [3:3](R/W1C/H) NCB result write response error.
461 * irde:1 [2:2](R/W1C/H) Instruction NCB read response error.
462 * dovf:1 [1:1](R/W1C/H) Doorbell overflow.
463 * mbox:1 [0:0](R/W1C/H) PF to VF mailbox interrupt. Set when
464 * CPT()_VF()_PF_MBOX(0) is written.
467 union cptx_vqx_misc_int {
469 struct cptx_vqx_misc_int_s {
470 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
471 u64 reserved_5_63:59;
477 #else /* Word 0 - Little Endian */
483 u64 reserved_5_63:59;
484 #endif /* Word 0 - End */
489 * Register (NCB) cpt#_vq#_done_ack
491 * CPT Queue Done Count Ack Registers
492 * This register is written by software to acknowledge interrupts.
493 * cptx_vqx_done_ack_s
495 * reserved_20_63:44 [63:20] Reserved.
496 * done_ack:20 [19:0](R/W/H) Number of decrements to CPT()_VQ()_DONE[DONE].
497 * Reads CPT()_VQ()_DONE[DONE]. Written by software to acknowledge
498 * interrupts. If CPT()_VQ()_DONE[DONE] is still nonzero the interrupt
499 * will be re-sent if the conditions described in CPT()_VQ()_DONE[DONE]
503 union cptx_vqx_done_ack {
505 struct cptx_vqx_done_ack_s {
506 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
507 u64 reserved_20_63:44;
509 #else /* Word 0 - Little Endian */
511 u64 reserved_20_63:44;
512 #endif /* Word 0 - End */
517 * Register (NCB) cpt#_vq#_done
519 * CPT Queue Done Count Registers
520 * These registers contain the per-queue instruction done count.
523 * reserved_20_63:44 [63:20] Reserved.
524 * done:20 [19:0](R/W/H) Done count. When CPT_INST_S[DONEINT] set and that
525 * instruction completes, CPT()_VQ()_DONE[DONE] is incremented when the
526 * instruction finishes. Write to this field are for diagnostic use only;
527 * instead software writes CPT()_VQ()_DONE_ACK with the number of
528 * decrements for this field.
529 * Interrupts are sent as follows:
530 * * When CPT()_VQ()_DONE[DONE] = 0, then no results are pending, the
531 * interrupt coalescing timer is held to zero, and an interrupt is not
533 * * When CPT()_VQ()_DONE[DONE] != 0, then the interrupt coalescing timer
534 * counts. If the counter is >= CPT()_VQ()_DONE_WAIT[TIME_WAIT]*1024, or
535 * CPT()_VQ()_DONE[DONE] >= CPT()_VQ()_DONE_WAIT[NUM_WAIT], i.e. enough
536 * time has passed or enough results have arrived, then the interrupt is
538 * * When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is written
539 * but this is not typical), the interrupt coalescing timer restarts.
540 * Note after decrementing this interrupt equation is recomputed,
541 * for example if CPT()_VQ()_DONE[DONE] >= CPT()_VQ()_DONE_WAIT[NUM_WAIT]
542 * and because the timer is zero, the interrupt will be resent immediately.
543 * (This covers the race case between software acknowledging an interrupt
544 * and a result returning.)
545 * * When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not sent,
546 * but the counting described above still occurs.
547 * Since CPT instructions complete out-of-order, if software is using
548 * completion interrupts the suggested scheme is to request a DONEINT on
549 * each request, and when an interrupt arrives perform a "greedy" scan for
550 * completions; even if a later command is acknowledged first this will
551 * not result in missing a completion.
552 * Software is responsible for making sure [DONE] does not overflow;
553 * for example by insuring there are not more than 2^20-1 instructions in
554 * flight that may request interrupts.
557 union cptx_vqx_done {
559 struct cptx_vqx_done_s {
560 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
561 u64 reserved_20_63:44;
563 #else /* Word 0 - Little Endian */
565 u64 reserved_20_63:44;
566 #endif /* Word 0 - End */
571 * Register (NCB) cpt#_vq#_done_wait
573 * CPT Queue Done Interrupt Coalescing Wait Registers
574 * Specifies the per queue interrupt coalescing settings.
575 * cptx_vqx_done_wait_s
577 * reserved_48_63:16 [63:48] Reserved.
578 * time_wait:16; [47:32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] = 0
579 * or CPT()_VQ()_DONE_ACK is written a timer is cleared. When the timer
580 * reaches [TIME_WAIT]*1024 then interrupt coalescing ends.
581 * see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is disabled.
582 * reserved_20_31:12 [31:20] Reserved.
583 * num_wait:20 [19:0](R/W) Number of messages hold-off.
584 * When CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing ends
585 * see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as 0x1.
588 union cptx_vqx_done_wait {
590 struct cptx_vqx_done_wait_s {
591 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
592 u64 reserved_48_63:16;
594 u64 reserved_20_31:12;
596 #else /* Word 0 - Little Endian */
598 u64 reserved_20_31:12;
600 u64 reserved_48_63:16;
601 #endif /* Word 0 - End */
606 * Register (NCB) cpt#_vq#_done_ena_w1s
608 * CPT Queue Done Interrupt Enable Set Registers
609 * Write 1 to these registers will enable the DONEINT interrupt for the queue.
610 * cptx_vqx_done_ena_w1s_s
612 * reserved_1_63:63 [63:1] Reserved.
613 * done:1 [0:0](R/W1S/H) Write 1 will enable DONEINT for this queue.
614 * Write 0 has no effect. Read will return the enable bit.
616 union cptx_vqx_done_ena_w1s {
618 struct cptx_vqx_done_ena_w1s_s {
619 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
620 u64 reserved_1_63:63;
622 #else /* Word 0 - Little Endian */
624 u64 reserved_1_63:63;
625 #endif /* Word 0 - End */
630 * Register (NCB) cpt#_vq#_ctl
632 * CPT VF Queue Control Registers
633 * This register configures queues. This register should be changed (other than
634 * clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).
637 * reserved_1_63:63 [63:1] Reserved.
638 * ena:1 [0:0](R/W/H) Enables the logical instruction queue.
639 * See also CPT()_PF_Q()_CTL[CONT_ERR] and CPT()_VQ()_INPROG[INFLIGHT].
640 * 1 = Queue is enabled.
641 * 0 = Queue is disabled.
645 struct cptx_vqx_ctl_s {
646 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
647 u64 reserved_1_63:63;
649 #else /* Word 0 - Little Endian */
651 u64 reserved_1_63:63;
652 #endif /* Word 0 - End */
655 #endif /*__CPT_HW_TYPES_H*/